[coreboot] r3981 - in trunk/coreboot-v2/src: arch/i386/include/arch arch/i386/lib config devices include/device northbridge/amd/amdfam10 northbridge/intel/i945
svn at coreboot.org
svn at coreboot.org
Fri Mar 6 20:11:52 CET 2009
Author: stepan
Date: 2009-03-06 20:11:52 +0100 (Fri, 06 Mar 2009)
New Revision: 3981
Modified:
trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h
trunk/coreboot-v2/src/arch/i386/lib/pci_ops_mmconf.c
trunk/coreboot-v2/src/config/Options.lb
trunk/coreboot-v2/src/devices/pci_ops.c
trunk/coreboot-v2/src/include/device/pci_ops.h
trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c
trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c
Log:
Fix mmconf (PCIe memory mapped config space access) support in v2. It was
horribly broken and thus never used by any platform. This needs to get
straightened out so current chipsets drivers can use the full feature set.
Create wrapper functions similar to the io pci config space ones.
Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Myles Watson <mylesgw at gmail.com>
Modified: trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h
===================================================================
--- trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h 2009-03-06 18:39:54 UTC (rev 3980)
+++ trunk/coreboot-v2/src/arch/i386/include/arch/romcc_io.h 2009-03-06 19:11:52 UTC (rev 3981)
@@ -105,13 +105,13 @@
static inline __attribute__((always_inline)) uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
{
unsigned addr;
- addr = dev | where;
+ addr = MMCONF_BASE_ADDRESS | dev | where;
return read8x(addr);
}
#endif
static inline __attribute__((always_inline)) uint8_t pci_read_config8(device_t dev, unsigned where)
{
-#if MMCONF_SUPPORT
+#if MMCONF_SUPPORT_DEFAULT
return pci_mmio_read_config8(dev, where);
#else
return pci_io_read_config8(dev, where);
@@ -134,14 +134,14 @@
static inline __attribute__((always_inline)) uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
{
unsigned addr;
- addr = dev | where;
+ addr = MMCONF_BASE_ADDRESS | dev | where;
return read16x(addr);
}
#endif
static inline __attribute__((always_inline)) uint16_t pci_read_config16(device_t dev, unsigned where)
{
-#if MMCONF_SUPPORT
+#if MMCONF_SUPPORT_DEFAULT
return pci_mmio_read_config16(dev, where);
#else
return pci_io_read_config16(dev, where);
@@ -165,14 +165,14 @@
static inline __attribute__((always_inline)) uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
{
unsigned addr;
- addr = dev | where;
+ addr = MMCONF_BASE_ADDRESS | dev | where;
return read32x(addr);
}
#endif
static inline __attribute__((always_inline)) uint32_t pci_read_config32(device_t dev, unsigned where)
{
-#if MMCONF_SUPPORT
+#if MMCONF_SUPPORT_DEFAULT
return pci_mmio_read_config32(dev, where);
#else
return pci_io_read_config32(dev, where);
@@ -195,14 +195,14 @@
static inline __attribute__((always_inline)) void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t value)
{
unsigned addr;
- addr = dev | where;
+ addr = MMCONF_BASE_ADDRESS | dev | where;
write8x(addr, value);
}
#endif
static inline __attribute__((always_inline)) void pci_write_config8(device_t dev, unsigned where, uint8_t value)
{
-#if MMCONF_SUPPORT
+#if MMCONF_SUPPORT_DEFAULT
pci_mmio_write_config8(dev, where, value);
#else
pci_io_write_config8(dev, where, value);
@@ -226,14 +226,14 @@
static inline __attribute__((always_inline)) void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t value)
{
unsigned addr;
- addr = dev | where;
+ addr = MMCONF_BASE_ADDRESS | dev | where;
write16x(addr, value);
}
#endif
static inline __attribute__((always_inline)) void pci_write_config16(device_t dev, unsigned where, uint16_t value)
{
-#if MMCONF_SUPPORT
+#if MMCONF_SUPPORT_DEFAULT
pci_mmio_write_config16(dev, where, value);
#else
pci_io_write_config16(dev, where, value);
@@ -257,14 +257,14 @@
static inline __attribute__((always_inline)) void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t value)
{
unsigned addr;
- addr = dev | where;
+ addr = MMCONF_BASE_ADDRESS | dev | where;
write32x(addr, value);
}
#endif
static inline __attribute__((always_inline)) void pci_write_config32(device_t dev, unsigned where, uint32_t value)
{
-#if MMCONF_SUPPORT
+#if MMCONF_SUPPORT_DEFAULT
pci_mmio_write_config32(dev, where, value);
#else
pci_io_write_config32(dev, where, value);
Modified: trunk/coreboot-v2/src/arch/i386/lib/pci_ops_mmconf.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/pci_ops_mmconf.c 2009-03-06 18:39:54 UTC (rev 3980)
+++ trunk/coreboot-v2/src/arch/i386/lib/pci_ops_mmconf.c 2009-03-06 19:11:52 UTC (rev 3981)
@@ -13,6 +13,7 @@
*/
#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE) ( \
+ MMCONF_BASE_ADDRESS | \
(((SEGBUS) & 0xFFF) << 20) | \
(((DEVFN) & 0xFF) << 12) | \
((WHERE) & 0xFFF))
Modified: trunk/coreboot-v2/src/config/Options.lb
===================================================================
--- trunk/coreboot-v2/src/config/Options.lb 2009-03-06 18:39:54 UTC (rev 3980)
+++ trunk/coreboot-v2/src/config/Options.lb 2009-03-06 19:11:52 UTC (rev 3981)
@@ -983,6 +983,13 @@
comment "enable mmconfig for pci conf"
end
+define MMCONF_BASE_ADDRESS
+ default none
+ format "0x%x"
+ export used
+ comment "enable mmconfig base address"
+end
+
define HW_MEM_HOLE_SIZEK
default 0
export always
Modified: trunk/coreboot-v2/src/devices/pci_ops.c
===================================================================
--- trunk/coreboot-v2/src/devices/pci_ops.c 2009-03-06 18:39:54 UTC (rev 3980)
+++ trunk/coreboot-v2/src/devices/pci_ops.c 2009-03-06 19:11:52 UTC (rev 3981)
@@ -3,6 +3,7 @@
*
* Copyright (C) 2004 Linux Networx
* (Written by Eric Biederman <ebiederman at lnxi.com> for Linux Networx)
+ * Copyright (C) 2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -79,3 +80,41 @@
struct bus *pbus = get_pbus(dev);
ops_pci_bus(pbus)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
}
+
+#if MMCONF_SUPPORT
+uint8_t pci_mmio_read_config8(device_t dev, unsigned where)
+{
+ struct bus *pbus = get_pbus(dev);
+ return pci_ops_mmconf.read8(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
+}
+
+uint16_t pci_mmio_read_config16(device_t dev, unsigned where)
+{
+ struct bus *pbus = get_pbus(dev);
+ return pci_ops_mmconf.read16(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
+}
+
+uint32_t pci_mmio_read_config32(device_t dev, unsigned where)
+{
+ struct bus *pbus = get_pbus(dev);
+ return pci_ops_mmconf.read32(pbus, dev->bus->secondary, dev->path.pci.devfn, where);
+}
+
+void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t val)
+{
+ struct bus *pbus = get_pbus(dev);
+ pci_ops_mmconf.write8(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
+}
+
+void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t val)
+{
+ struct bus *pbus = get_pbus(dev);
+ pci_ops_mmconf.write16(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
+}
+
+void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t val)
+{
+ struct bus *pbus = get_pbus(dev);
+ pci_ops_mmconf.write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val);
+}
+#endif
Modified: trunk/coreboot-v2/src/include/device/pci_ops.h
===================================================================
--- trunk/coreboot-v2/src/include/device/pci_ops.h 2009-03-06 18:39:54 UTC (rev 3980)
+++ trunk/coreboot-v2/src/include/device/pci_ops.h 2009-03-06 19:11:52 UTC (rev 3981)
@@ -12,4 +12,13 @@
void pci_write_config16(device_t dev, unsigned where, uint16_t val);
void pci_write_config32(device_t dev, unsigned where, uint32_t val);
+#if MMCONF_SUPPORT
+uint8_t pci_mmio_read_config8(device_t dev, unsigned where);
+uint16_t pci_mmio_read_config16(device_t dev, unsigned where);
+uint32_t pci_mmio_read_config32(device_t dev, unsigned where);
+void pci_mmio_write_config8(device_t dev, unsigned where, uint8_t val);
+void pci_mmio_write_config16(device_t dev, unsigned where, uint16_t val);
+void pci_mmio_write_config32(device_t dev, unsigned where, uint32_t val);
+#endif
+
#endif /* PCI_OPS_H */
Modified: trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-03-06 18:39:54 UTC (rev 3980)
+++ trunk/coreboot-v2/src/northbridge/amd/amdfam10/northbridge.c 2009-03-06 19:11:52 UTC (rev 3981)
@@ -1176,7 +1176,7 @@
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
-#if MMCONF_SUPPORT
+#if MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf,
#else
.ops_pci_bus = &pci_cf8_conf1,
Modified: trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c 2009-03-06 18:39:54 UTC (rev 3980)
+++ trunk/coreboot-v2/src/northbridge/intel/i945/northbridge.c 2009-03-06 19:11:52 UTC (rev 3981)
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -199,7 +199,11 @@
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
- .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
+#if MMCONF_SUPPORT_DEFAULT
+ .ops_pci_bus = &pci_ops_mmconf,
+#else
+ .ops_pci_bus = &pci_cf8_conf1,
+#endif
};
static void mc_read_resources(device_t dev)
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