[coreboot] [PATCH] YABEL: fix 32 bit IO accesses

Pattrick Hueper phueper at hueper.net
Wed Mar 4 23:09:07 CET 2009


Hi,

i just found that 32 bit PCI Accesses thru ports 0xCF8/0xCFC will not
work in YABEL. This fixes it:

Signed-off-by: Pattrick Hueper <phueper at hueper.net>
---
 util/x86emu/yabel/io.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/util/x86emu/yabel/io.c b/util/x86emu/yabel/io.c
index a69e5e6..6f481a7 100644
--- a/util/x86emu/yabel/io.c
+++ b/util/x86emu/yabel/io.c
@@ -348,7 +348,7 @@ u32
 pci_cfg_read(X86EMU_pioAddr addr, u8 size)
 {
        u32 rval = 0xFFFFFFFF;
-       if ((addr >= 0xCFC) && ((addr + size) <= 0xCFF)) {
+       if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) {
                // PCI Configuration Mechanism 1 step 1
                // write to 0xCF8, sets bus, device, function and
Config Space offset
                // later read from 0xCFC-0xCFF returns the value...
@@ -404,7 +404,7 @@ pci_cfg_read(X86EMU_pioAddr addr, u8 size)
 void
 pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size)
 {
-       if ((addr >= 0xCFC) && ((addr + size) <= 0xCFF)) {
+       if ((addr >= 0xCFC) && ((addr + size) <= 0xD00)) {
                // PCI Configuration Mechanism 1 step 1
                // write to 0xCF8, sets bus, device, function and
Config Space offset
                // later write to 0xCFC-0xCFF sets the value...
--
1.6.1.2




More information about the coreboot mailing list