[coreboot] Intel Eagle Height evaluation board support

[Thomas JOURDAN]

Hi

This series of patches add support in coreboot-v2 for the Intel Eagle
Heights evaluation board
(http://www.intel.com/design/intarch/manuals/316639.pdf). This board
has a Core 2 Duo Mobile SL9380 (FSB 800Mhz - 45nm) processor with a
SCH i3100 chipset (northbridge and southbridge in the same package).
It has 2 GB of ECC memory, 6 USB, 6 Sata, 2 serial, 1 parallel, PS/2
keyboard and mouse, 3 PCIe 4x slots and 1 PCI 32bits/33Mhz slot.

Features :
* CAR
* CBFS
* a little bit of ACPI
* AHCI sata (legacy IDE mode available).

Things that work :
* Ram with ECC (memtest ok)
* All PCI / PCIe slot
* All sata ports,
* serial ports, PS/2 keyboard

Things not tested (but should work) :
* PS/2 mouse
* parallel port
* hpet
* virtualization

Things broken :
* reset (the config file only has a fallback image and don't really
understand the concept of failover / fallback / normal image)
* vga rom -> The evaluation board comes with a PCIe 1x Matrox G550
graphics card. Coreboot fails to execute the vga rom (either x86emu,
yabel or real mode). There is an exception 0x06 and everything will
freeze. It could be the loadall instruction
(http://en.wikipedia.org/wiki/LOADALL). I'll investigate tomorrow with
a probe to understand what happens.

Some remarks :
- the mptable is based on the RCBA interrupt routing config registers,
but not the acpi table
- the mmconf is hardcoded to 0xE0000000 but I don't understand how the
resource allocate can properly handle it. If you change the mmconf
address in the northbridge code, don't forget to adjust the associated
motherboard resource in the DSDT.

For lucky people (like me) who owns the board and wants to give it a
try, flashrom won't work with the original bios. The board has a
SST49LF008A (FWH 1MB) on a PLCC32 socket, which is cool. But the
default bios will lock down half of the chip. Flashrom will fail to
properly detect it. To bypass this, I forced flashrom to detect the
chip as a 49LF004A (512KB). This way, I can write a first 512KB
coreboot file. After, no more problems, the full 1MB are available in
flashrom. Of course, no problem if you use an external flasher.

Regards,
Thomas
-------------- next part --------------
A non-text attachment was scrubbed...
Name: bga956.patch
Type: text/x-patch
Size: 975 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090623/67c4b58e/attachment.patch>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: eagleheights.patch
Type: text/x-patch
Size: 103497 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090623/67c4b58e/attachment-0001.patch>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: i3100_northbridge.patch
Type: text/x-patch
Size: 1919 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090623/67c4b58e/attachment-0002.patch>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: i3100_southbridge.patch
Type: text/x-patch
Size: 11580 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090623/67c4b58e/attachment-0003.patch>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: lpc47m172.patch
Type: text/x-patch
Size: 2035 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090623/67c4b58e/attachment-0004.patch>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: model_1067x.patch
Type: text/x-patch
Size: 18812 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20090623/67c4b58e/attachment-0005.patch>