[coreboot] flashrom: Non-power-of-2 chip sizes, registers and external programmers

[Carl-Daniel Hailfinger]

This mail is about two separate problems with a very similar cause:
- Non-power-of-2 chip sizes.
- Flash register space.

General remark:
Addressing chips in x86 mainboards means their address space is
top-aligned. However, the same chips in external programmers have
bottom-aligned addressing.


------Non-power-of-2 chip sizes--------
Flashrom currently supports a few chips with sizes which are not powers
of 2. Most notably, some 3 Mbit (384 kByte) chips.

Example addresses in binary for onboard 384 KByte flash:
Nothing mapped:
11111111111110000000000000000000
to
11111111111110011111111111111111

Bottom 128 kByte:
11111111111110100000000000000000
to
11111111111110111111111111111111

Middle 128 kByte:
11111111111111000000000000000000
to
11111111111111011111111111111111

Top 128 kByte:
11111111111111100000000000000000
to
11111111111111111111111111111111

If we ignore the leading ones (the chip ignores them as well) and write
the lowest significant bits as X, the example addresses can be written
like this:
Nothing mapped: 00X
Bottom 128 kByte: 01X
Middle 128 kByte: 10X
Top 128 kByte: 11X

Flashrom will use address 01X-11X to access the flash chip, giving us a
readback result of Bottom,Middle,Top.
If we accept the addresses above as canonical, an external programmer
with bottom-aligned addressing will use addresses 00X-10X instead,
giving us a readback result of Nothing,Bottom,Middle. Notice the Nothing
at the start of the readback and the missing Top.

There are two ways to fix this:
1. Have all programmers use top-aligned addresses.
2. Force the user to specify alignment manually.

Option 1 causes problems for all machines with bottom-aligned flash
(PowerPC?, maybe some PCI option ROMs), but is the right thing to do if
the chip should be used for x86 BIOS.
Option 2 causes problems for x86 BIOS chips in external programmers
because manual intervention is necessary.

Chips with power-of-two sizes are totally unaffected by the problem above.


------Flash register space--------
Flash chips with register space usually provide access that register
space if a specific bit in the address is zero. That bit is almost
always bit 22.

External programmers currently have bottom-aligned addressing, so the
register selection bit is always zero. This can cause reads and writes
of chips with separate register space to fail, possibly even confusing
the chip until it doesn't respond anymore.

Using top-aligned addresses for external programmers would fix the
register space issue completely for all chips where register selection
bit bein zero means register access.
However, it is entirely possible that there are chips where the register
selection bit has opposite logic. No such chips seem to be usable on x86
mainboards, so I'm not too worried about this.


Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/