[coreboot] Flashrom support for EPIA-N(L) - patch for review

[Uwe Hermann]

Hi,

On Thu, Jun 18, 2009 at 12:40:39AM +0200, Luc Verhaegen wrote:
> > See below patch for flashrom to add support for EPIA-N(L) Programming.
> > 
> > This has been built against R599 and tested for read, write and verify
> > on an EPIA-NL 800

Nice, thanks!


> >  Index: util/flashrom/board_enable.c
> > ===================================================================
> > --- util/flashrom/board_enable.c	(revision 599)
> > +++ util/flashrom/board_enable.c	(working copy)
> > @@ -270,6 +270,44 @@
> >  }
> >  
> >  /**
> > + * Suited for VIAs EPIA N & NL.
> > + */
> > +static int board_via_epia_n(const char *name)
> > +{
> > +	struct pci_dev *dev;
> > +	uint16_t base;
> > +	uint8_t val;
> > +
> > +	dev = pci_dev_find(0x1106, 0x3227);	/* VT8237R ISA bridge */
> > +	if (!dev) {
> > +		fprintf(stderr, "\nERROR: VT8237R ISA bridge not
> > found.\n");
> > +		return -1;
> > +	}
> > +
> > +	/* All memory cycles, not just ROM ones, go to LPC */
> > +	val = pci_read_byte(dev, 0x59);
> > +	val &= ~0x80;
> > +	pci_write_byte(dev, 0x59, val);
> > +	
> > +	/* GPIO9 -> output */
> > +	val = pci_read_byte(dev, 0xE4);
> > +	//printf("GPO Pin Select Reg = 0x%02X\n", val);
> > +	val |= 0x20;
> > +	pci_write_byte(dev, 0xE4, val);
> > +
> > +	/* Get Power Management IO address. */
> > +	base = pci_read_word(dev, 0x88) & 0xFF80;
> > +
> > +	/* Enable GPIO9 which is connected to write protect. */
> > +	val = INB(base + 0x4D);
> > +	//printf("PMM GPIO = 0x%02X\n", val);
> > +	val |= 0x02;
> > +	OUTB(val, base + 0x4D);
> > +
> > +	return 0;
> > +}
> > +
> 
> Please use
> 	vt823x_set_all_writes_to_lpc
> and
> 	vt823x_gpio_set

Yep.

Also, please add a Signed-off-by to all the patches you submit,
see http://www.coreboot.org/Development_Guidelines#Sign-off_Procedure


Thanks, Uwe.
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