[coreboot] [v2] r4357 - in trunk/coreboot-v2: src/arch/i386/init src/lib src/mainboard/emulation/qemu-x86 src/pc80 targets/emulation/qemu-x86
svn at coreboot.org
svn at coreboot.org
Tue Jun 16 17:02:53 CEST 2009
Author: rminnich
Date: 2009-06-16 17:02:52 +0200 (Tue, 16 Jun 2009)
New Revision: 4357
Added:
trunk/coreboot-v2/src/arch/i386/init/car.S
trunk/coreboot-v2/src/arch/i386/init/entry.S
trunk/coreboot-v2/src/arch/i386/init/ldscript.ld
trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/rom.c
trunk/coreboot-v2/targets/emulation/qemu-x86/Config-car.lb
Modified:
trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback_cbfs.lb
trunk/coreboot-v2/src/lib/Config.lb
trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb
trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb
trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/failover.c
trunk/coreboot-v2/src/pc80/Config.lb
trunk/coreboot-v2/src/pc80/serial.c
trunk/coreboot-v2/targets/emulation/qemu-x86/Config.lb
Log:
These changes implement car in qemu. The implementation is in several
ways superior to v3, while lacking its completeness. But, one nice
thing: no more included .S or .c files. It's all separate compilation.
That should allow our Makefiles to work much better.
Note that the current non-CAR implementation is the default and
continues to work (tested FILO boot to Linux on both CAR and non-CAR).
Index: src/mainboard/emulation/qemu-x86/Config.lb
Change this to be sensitive to USE_DCACHE_RAM. All settings etc. that
depend on this variable are grouped in one if, and the other parts
(romcc etc.) are in the else. This change is a model of how we should be
able to do other motherboards.
Index: src/mainboard/emulation/qemu-x86/Options.lb
add needed options.
Index: src/mainboard/emulation/qemu-x86/failover.c
remove code inclusion from this not-yet-used file.
Index: src/mainboard/emulation/qemu-x86/rom.c
This is the entry point for the rom-based code. Called stage1.c in v3.
Index: src/lib/Config.lb
change initobject to a .o from a .c; this fixed a build problem.
Index: src/pc80/serial.c
make uart_init non-static.
Index: src/pc80/Config.lb
add initobject
Index: src/arch/i386/init/entry.S
Entry point. Unify a bunch of files that were fiddly lttle includes. From v3.
Index: src/arch/i386/init/ldscript.ld
new file. The goal is to hang all init changes for CAR here, to minimize other changes to any
other ldscript. Besides, putting this in init makes sense; entry and car are manage init.
Index: src/arch/i386/init/car.S
generic i386 car code from v3.
Index: src/arch/i386/init/ldscript_fallback_cbfs.lb
Fix what looks like a bug: this was not including the init.text section.
Index: targets/emulation/qemu-x86/Config.lb
push up the console loglevel. qemu is for debugging so we might as well
get all the debugging we can.
Index: targets/emulation/qemu-x86/Config-car.lb
For CAR bullds.
Signed-off-by: Ronald G. minnich <rminnich at gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Added: trunk/coreboot-v2/src/arch/i386/init/car.S
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/car.S (rev 0)
+++ trunk/coreboot-v2/src/arch/i386/init/car.S 2009-06-16 15:02:52 UTC (rev 4357)
@@ -0,0 +1,357 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2005 Eswar Nallusamy, LANL
+ * Copyright (C) 2005 Tyan
+ * (Written by Yinghai Lu <yhlu at tyan.com> for Tyan)
+ * Copyright (C) 2007 coresystems GmbH
+ * (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Init code - Switch CPU to protected mode and enable Cache-as-Ram (CAR). */
+
+#include <arch/intel.h>
+
+#define ROM_CODE_SEG 0x08
+#define ROM_DATA_SEG 0x10
+
+#define CACHE_RAM_CODE_SEG 0x18
+#define CACHE_RAM_DATA_SEG 0x20
+
+ /* When we come here we are in protected mode. We expand the stack
+ * and copy the data segment from ROM to the memory.
+ *
+ * After that, we call the chipset bootstrap routine that
+ * does what is left of the chipset initialization.
+ *
+ * NOTE: Aligned to 4 so that we are sure that the prefetch
+ * cache will be reloaded.
+ */
+ .section .rom.text
+ .align 4
+ .globl protected_stage0
+protected_stage0:
+ lgdt %cs:gdtptr
+ ljmp $ROM_CODE_SEG, $__protected_stage0
+
+.globl __protected_stage0
+__protected_stage0:
+ /* Save the BIST result. */
+ movl %eax, %ebp
+
+ intel_chip_post_macro(0x01)
+
+ movw $ROM_DATA_SEG, %ax
+ movw %ax, %ds
+ movw %ax, %es
+ movw %ax, %ss
+ movw %ax, %fs
+ movw %ax, %gs
+
+ /* Restore the BIST value to %eax. */
+ movl %ebp, %eax
+
+.align 4
+
+/* disable HyperThreading is done by eswar
+ * the other is very similar to the AMD CAR, except remove amd specific msr
+ */
+
+#define CacheSize DCACHE_RAM_SIZE
+#define CacheBase DCACHE_RAM_BASE
+
+#include <cpu/x86/mtrr.h>
+
+ /* Save the BIST result */
+ movl %eax, %ebp
+
+CacheAsRam:
+ /* Check whether the processor has HT capability */
+ movl $01, %eax
+ cpuid
+ btl $28, %edx
+ jnc NotHtProcessor
+ bswapl %ebx
+ cmpb $01, %bh
+ jbe NotHtProcessor
+
+ /* It is a HT processor; Send SIPI to the other logical processor
+ * within this processor so that the CAR related common system
+ * registers are programmed accordingly
+ */
+
+ /* Use some register that is common to both logical processors
+ * as semaphore. Refer Appendix B, Vol.3
+ */
+
+ xorl %eax, %eax
+ xorl %edx, %edx
+ movl $0x250, %ecx
+ wrmsr
+
+ /* Figure out the logical AP's APIC ID; the following logic will work
+ * only for processors with 2 threads.
+ *
+ * Refer to Vol 3. Table 7-1 for details about this logic
+ */
+ movl $0xFEE00020, %esi
+ movl (%esi), %ebx
+ andl $0xFF000000, %ebx
+ bswapl %ebx
+ btl $0, %ebx
+ jnc LogicalAP0
+ andb $0xFE, %bl
+ jmp SendSIPI
+LogicalAP0:
+ orb $0x01, %bl
+SendSIPI:
+ bswapl %ebx /* ebx - logical AP's APIC ID */
+
+ /* Fill up the IPI command registers in the Local APIC mapped to
+ * default address and issue SIPI to the other logical processor
+ * within this processor die.
+ */
+
+RetrySIPI:
+ movl %ebx, %eax
+ movl $0xFEE00310, %esi
+ movl %eax, (%esi)
+
+ /* SIPI vector - F900:0000 */
+ movl $0x000006F9, %eax
+ movl $0xFEE00300, %esi
+ movl %eax, (%esi)
+
+ movl $0x30, %ecx
+SIPIDelay:
+ pause
+ decl %ecx
+ jnz SIPIDelay
+
+ movl (%esi), %eax
+ andl $0x00001000, %eax
+ jnz RetrySIPI
+
+ /* Wait for the Logical AP to complete initialization */
+LogicalAPSIPINotdone:
+ movl $0x250, %ecx
+ rdmsr
+ orl %eax, %eax
+ jz LogicalAPSIPINotdone
+
+
+
+NotHtProcessor:
+ /* Set the default memory type and enable fixed and variable MTRRs */
+ movl $MTRRdefType_MSR, %ecx
+ xorl %edx, %edx
+ /* Enable Variable and Fixed MTRRs */
+ movl $0x00000c00, %eax
+ wrmsr
+
+ /* Clear all MTRRs */
+ xorl %edx, %edx
+ movl $fixed_mtrr_msr, %esi
+
+clear_fixed_var_mtrr:
+ lodsl (%esi), %eax
+ testl %eax, %eax
+ jz clear_fixed_var_mtrr_out
+
+ movl %eax, %ecx
+ xorl %eax, %eax
+ wrmsr
+
+ jmp clear_fixed_var_mtrr
+clear_fixed_var_mtrr_out:
+
+/* 0x06 is the WB IO type for a given 4k segment.
+ * segs is the number of 4k segments in the area of the particular
+ * register we want to use for CAR.
+ * reg is the register where the IO type should be stored.
+ */
+.macro extractmask segs, reg
+.if \segs <= 0
+ /* The xorl here is superfluous because at the point of first execution
+ * of this macro, %eax and %edx are cleared. Later invocations of this
+ * macro will have a monotonically increasing segs parameter.
+ */
+ xorl \reg, \reg
+.elseif \segs == 1
+ movl $0x06000000, \reg /* WB IO type */
+.elseif \segs == 2
+ movl $0x06060000, \reg /* WB IO type */
+.elseif \segs == 3
+ movl $0x06060600, \reg /* WB IO type */
+.elseif \segs >= 4
+ movl $0x06060606, \reg /* WB IO type */
+.endif
+.endm
+
+/* size is the cache size in bytes we want to use for CAR.
+ * windowoffset is the 32k-aligned window into CAR size
+ */
+.macro simplemask carsize, windowoffset
+/* DO NOT CHANGE THE FORMATTING of the two lines below! Whitespace is
+ * interpreted as an argument delimiter by some versions of GNU as. */
+ extractmask (((\carsize-\windowoffset)/0x1000)-4), %eax
+ extractmask (((\carsize-\windowoffset)/0x1000)), %edx
+.endm
+
+#if CacheSize > 0x10000
+#error Invalid CAR size, must be at most 64k.
+#endif
+#if CacheSize < 0x1000
+#error Invalid CAR size, must be at least 4k. This is a processor limitation.
+#endif
+#if (CacheSize & (0x1000 - 1))
+#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
+#endif
+
+#if CacheSize > 0x8000
+ /* enable caching for 32K-64K using fixed mtrr */
+ movl $0x268, %ecx /* fix4k_c0000*/
+ simplemask CacheSize, 0x8000
+ wrmsr
+#endif
+
+ /* enable caching for 0-32K using fixed mtrr */
+ movl $0x269, %ecx /* fix4k_c8000*/
+ simplemask CacheSize, 0
+ wrmsr
+
+#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+ /* enable write base caching so we can do execute in place
+ * on the flash rom.
+ */
+ movl $0x202, %ecx
+ xorl %edx, %edx
+ movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ wrmsr
+
+ movl $0x203, %ecx
+ movl $0x0000000f, %edx
+ movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
+ wrmsr
+#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
+
+ /* enable cache */
+ movl %cr0, %eax
+ andl $0x9fffffff,%eax
+ movl %eax, %cr0
+
+ /* Read the range with lodsl*/
+ movl $CacheBase, %esi
+ cld
+ movl $(CacheSize>>2), %ecx
+ rep lodsl
+
+ /* Clear the range */
+ movl $CacheBase, %edi
+ movl $(CacheSize>>2), %ecx
+ xorl %eax, %eax
+ rep stosl
+
+
+ /* TODO: make this a config variable */
+#if CONFIG_CARTEST
+ /* check the cache as ram */
+ movl $CacheBase, %esi
+ movl $(CacheSize>>2), %ecx
+.xin1:
+ movl %esi, %eax
+ movl %eax, (%esi)
+ decl %ecx
+ je .xout1
+ add $4, %esi
+ jmp .xin1
+.xout1:
+
+ movl $CacheBase, %esi
+// movl $(CacheSize>>2), %ecx
+ movl $4, %ecx
+.xin1x:
+ movl %esi, %eax
+
+ movl $0x4000, %edx
+ movb %ah, %al
+.testx1:
+ outb %al, $0x80
+ decl %edx
+ jnz .testx1
+
+ movl (%esi), %eax
+ cmpb 0xff, %al
+ je .xin2 /* dont show */
+
+ movl $0x4000, %edx
+.testx2:
+ outb %al, $0x80
+ decl %edx
+ jnz .testx2
+
+.xin2: decl %ecx
+ je .xout1x
+ add $4, %esi
+ jmp .xin1x
+.xout1x:
+
+#endif
+
+ movl $(CacheBase+CacheSize-4), %eax
+ movl %eax, %esp
+
+ /* Load a different set of data segments */
+ movw $CACHE_RAM_DATA_SEG, %ax
+ movw %ax, %ds
+ movw %ax, %es
+ movw %ax, %ss
+
+lout:
+ /* Store zero for the pointer to the global variables. */
+ pushl $0
+
+ /* Restore the BIST result. */
+ movl %ebp, %eax
+
+ /* We need to set ebp? No need. */
+ movl %esp, %ebp
+
+ /* Third parameter: cpu #: 0 == BSP all other are APs.
+ * 0 until SMP support is added.
+ */
+ pushl $0
+ /* Second parameter: init_detected */
+ /* Store zero for the unused init_detected parameter. */
+ pushl $0
+ /* First parameter: bist */
+ pushl %eax
+ call main
+ /* We will not go back. */
+
+fixed_mtrr_msr:
+ .long 0x250, 0x258, 0x259
+ .long 0x268, 0x269, 0x26A
+ .long 0x26B, 0x26C, 0x26D
+ .long 0x26E, 0x26F
+var_mtrr_msr:
+ .long 0x200, 0x201, 0x202, 0x203
+ .long 0x204, 0x205, 0x206, 0x207
+ .long 0x208, 0x209, 0x20A, 0x20B
+ .long 0x20C, 0x20D, 0x20E, 0x20F
+ .long 0x000 /* NULL, end of table */
Added: trunk/coreboot-v2/src/arch/i386/init/entry.S
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/entry.S (rev 0)
+++ trunk/coreboot-v2/src/arch/i386/init/entry.S 2009-06-16 15:02:52 UTC (rev 4357)
@@ -0,0 +1,156 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 1999 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <arch/rom_segs.h>
+ .code16
+ .globl _stage0
+_stage0:
+ cli
+
+ /* Save the BIST result. */
+ movl %eax, %ebp;
+
+ /* thanks to kmliu at sis.com.tw for this TLB fix */
+ /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
+ * executing any further code. Even though paging is disabled we
+ * could still get false address translations due to the TLB if we
+ * didn't invalidate it.
+ */
+ xorl %eax, %eax
+ movl %eax, %cr3 /* Invalidate TLB. */
+
+ /* Switch to protected mode. */
+
+ /* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
+ * using BFD version 2.15.94.0.2.2 20041220 this works fine without all
+ * the ld hackery and other things. So leave it as is with this comment.
+ */
+
+ data32 lgdt %cs:gdtptr
+
+ movl %cr0, %eax
+ andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */
+ orl $0x60000001, %eax /* CD, NW, PE = 1 */
+ movl %eax, %cr0
+
+ /* Restore BIST result. */
+ movl %ebp, %eax
+
+ // port80_post(0x23)
+ /* Now we are in protected mode. Jump to a 32 bit code segment. */
+ data32 ljmp $ROM_CODE_SEG, $protected_stage0
+
+ /* I am leaving this weird jump in here in the event that future gas
+ * bugs force it to be used.
+ */
+ /* .byte 0x66 */
+ .code32
+ /* ljmp $ROM_CODE_SEG, $protected_stage0 */
+
+ /* .code16 */
+ .align 4
+ .globl gdt16
+gdt16 = . - _stage0
+gdt16x:
+ .word gdt16xend - gdt16x -1 /* Compute the table limit. */
+ .long gdt16x
+ .word 0
+
+ /* selgdt 0x08, flat code segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xcf, 0x00
+
+ /* selgdt 0x10, flat data segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x93, 0xcf, 0x00
+gdt16xend:
+
+ /* From now on we are 32 bit. */
+ .code32
+
+ /* We have two gdts where we could have one. That is ok.
+ *
+ * Let's not worry about this -- optimizing gdt is pointless since
+ * we're only in it for a little bit.
+ *
+ * Btw. note the trick below: The GDT points to ITSELF, and the first
+ * good descriptor is at offset 8. So you word-align the table, and
+ * then because you chose 8, you get a nice 64-bit aligned GDT entry,
+ * which is good as this is the size of the entry.
+ * Just in case you ever wonder why people do this.
+ */
+ .align 4
+ .globl gdtptr
+ .globl gdt_limit
+gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */
+
+gdt:
+gdtptr:
+ .word gdt_end - gdt -1 /* Compute the table limit. */
+ .long gdt /* We know the offset. */
+ .word 0
+
+ /* selgdt 0x08, flat code segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xcf, 0x00
+
+ /* selgdt 0x10, flat data segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x93, 0xcf, 0x00
+
+ /* selgdt 0x18, flat code segment for CAR */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xcf, 0x00
+
+ /* selgdt 0x20, flat data segment for CAR */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x93, 0xcf, 0x00
+gdt_end:
+
+/* Reset vector. */
+
+/*
+ * RVECTOR: Size of reset vector, default is 0x10.
+ * RESRVED: Size of vpd code, default is 0xf0.
+ * BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b).
+ */
+
+SEGMENT_SIZE = 0x10000
+RVECTOR = 0x00010
+
+/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here.
+ * I think we should leave it this way forever, as the bugs come and
+ * go -- and come again.
+ *
+ * .code16
+ * .section ".rom.text"
+ */
+.section ".reset", "ax"
+ .globl _resetjump
+_resetjump:
+ /* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */
+ /* jmp _stage0 */
+ .byte 0xe9
+ .int _stage0 - ( . + 2 )
+
+ /* Note: The above jump is hand coded to work around bugs in binutils.
+ * 5 bytes are used for a 3 byte instruction. This works because x86
+ * is little endian and allows us to use supported 32 bit relocations
+ * instead of the weird 16 bit relocations that binutils does not
+ * handle consistenly between versions because they are used so rarely.
+ */
Added: trunk/coreboot-v2/src/arch/i386/init/ldscript.ld
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript.ld (rev 0)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript.ld 2009-06-16 15:02:52 UTC (rev 4357)
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+TARGET(binary)
+SECTIONS
+{
+ /DISCARD/ : {
+ *(.comment)
+ *(.note.*)
+ *(.note)
+ }
+}
+
+SECTIONS {
+ _ROMTOP = 0xfffffff0;
+ . = _ROMTOP;
+ .resetvector . : {
+ *(.reset)
+ . = 15 ;
+ BYTE(0x00);
+ }
+}
+
Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback_cbfs.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback_cbfs.lb 2009-06-12 14:20:27 UTC (rev 4356)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback_cbfs.lb 2009-06-16 15:02:52 UTC (rev 4357)
@@ -46,6 +46,7 @@
*(.rom.text);
*(.rom.data);
*(.init.rodata.*);
+ *(.init.text);
*(.rodata.*);
*(.rom.data.*);
. = ALIGN(16);
Modified: trunk/coreboot-v2/src/lib/Config.lb
===================================================================
--- trunk/coreboot-v2/src/lib/Config.lb 2009-06-12 14:20:27 UTC (rev 4356)
+++ trunk/coreboot-v2/src/lib/Config.lb 2009-06-16 15:02:52 UTC (rev 4357)
@@ -20,7 +20,7 @@
# Force version.o to recompile every time
makedefine .PHONY : version.o
-initobject uart8250.c
+initobject uart8250.o
initobject memset.o
initobject memcpy.o
initobject memcmp.o
Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb 2009-06-12 14:20:27 UTC (rev 4356)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Config.lb 2009-06-16 15:02:52 UTC (rev 4357)
@@ -1,3 +1,5 @@
+## we don't use USE_DCACHE_RAM by default
+default USE_DCACHE_RAM=0
##
## Compute the location and size of where this firmware image
## (coreboot plus bootloader) will live in the boot rom chip.
@@ -42,62 +44,79 @@
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
+## ALL dependencies for USE_DCACHE_RAM go here.
+## That way, later, we can simply yank them if we wish.
+## We include the old-fashioned entry code in the ! USE_DCACHE_RAM case.
+## we do not use failover yet in this case. This is a work in progress.
+if USE_DCACHE_RAM
+ ##
+ ##
+ mainboardinit arch/i386/init/entry.S
+ mainboardinit arch/i386/init/car.S
+ ldscript /arch/i386/init/ldscript.ld
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
+ ## The main code for the rom section is called rom.c
+ initobject rom.o
+else
+ ##
+ ## Romcc output
+ ##
+ makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c ../romcc"
+ action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ end
+
+ makerule ./failover.inc
+ depends "$(MAINBOARD)/failover.c ../romcc"
+ action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ end
+
+ makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ end
+ makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ end
+
+ ##
+ ## Build our 16 bit and 32 bit coreboot entry code
+ ##
+ mainboardinit cpu/x86/16bit/entry16.inc
+ mainboardinit cpu/x86/32bit/entry32.inc
+ ldscript /cpu/x86/16bit/entry16.lds
+ ldscript /cpu/x86/32bit/entry32.lds
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
+ ##
+ ## Build our reset vector (This is where coreboot is entered)
+ ##
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+
+ ### Should this be in the northbridge code?
+ mainboardinit arch/i386/lib/cpu_reset.inc
+ ##
+ ## Setup RAM
+ ##
+ mainboardinit cpu/x86/fpu/enable_fpu.inc
+ mainboardinit ./auto.inc
+
+ ## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future.
+ ##
+ ## Include an id string (For safe flashing)
+ ##
+ mainboardinit arch/i386/lib/id.inc
+ ldscript /arch/i386/lib/id.lds
+
##
-## Build our reset vector (This is where coreboot is entered)
+## end of USE_DCACHE_RAM bits.
##
-mainboardinit cpu/x86/16bit/reset16.inc
-ldscript /cpu/x86/16bit/reset16.lds
+end
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit ./auto.inc
-
-##
## Include the secondary Configuration files
##
dir /pc80
Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-06-12 14:20:27 UTC (rev 4356)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Options.lb 2009-06-16 15:02:52 UTC (rev 4357)
@@ -41,8 +41,11 @@
uses CONFIG_CONSOLE_SERIAL8250
uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses CONFIG_USE_INIT
+uses CONFIG_USE_PRINTK_IN_CAR
-
uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CBFS
@@ -128,4 +131,12 @@
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
+##
+## known-good settings for qemu
+default DCACHE_RAM_BASE=0x8f000
+default DCACHE_RAM_SIZE=0x1000
+
+
+
+
end
Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/failover.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/failover.c 2009-06-12 14:20:27 UTC (rev 4356)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/failover.c 2009-06-16 15:02:52 UTC (rev 4357)
@@ -1,16 +1,14 @@
-#define ASSEMBLY 1
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
-#include "pc80/mc146818rtc_early.c"
-#include "cpu/x86/lapic/boot_cpu.c"
+/* no code inclusion allowed */
+//#include "pc80/mc146818rtc_early.c"
+//#include "cpu/x86/lapic/boot_cpu.c"
static void main(void)
{
- /* for now, just always assume failure */
-
#if 0
/* Is this a cpu reset? */
if (cpu_init_detected()) {
@@ -27,3 +25,4 @@
}
#endif
}
+
Added: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/rom.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/rom.c (rev 0)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/rom.c 2009-06-16 15:02:52 UTC (rev 4357)
@@ -0,0 +1,30 @@
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include <cbfs.h>
+
+/*
+ */
+void udelay(int usecs)
+{
+ int i;
+ for(i = 0; i < usecs; i++)
+ outb(i&0xff, 0x80);
+}
+
+void main(void)
+{
+ int i;
+ void uart_init(void);
+ void (*start_address)();
+ outb(5, 0x80);
+
+ uart_init();
+ start_address = cbfs_load_stage("fallback/coreboot_ram");
+ start_address();
+
+}
Modified: trunk/coreboot-v2/src/pc80/Config.lb
===================================================================
--- trunk/coreboot-v2/src/pc80/Config.lb 2009-06-12 14:20:27 UTC (rev 4356)
+++ trunk/coreboot-v2/src/pc80/Config.lb 2009-06-16 15:02:52 UTC (rev 4357)
@@ -17,3 +17,7 @@
dir vga
object keyboard.o
+
+if CONFIG_USE_INIT
+ initobject serial.o
+end
Modified: trunk/coreboot-v2/src/pc80/serial.c
===================================================================
--- trunk/coreboot-v2/src/pc80/serial.c 2009-06-12 14:20:27 UTC (rev 4356)
+++ trunk/coreboot-v2/src/pc80/serial.c 2009-06-16 15:02:52 UTC (rev 4357)
@@ -96,7 +96,7 @@
/* CONFIG_USE_PRINTK_IN_CAR == 1 */
extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
-static void uart_init(void)
+void uart_init(void)
{
#if USE_OPTION_TABLE == 1
static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 };
Added: trunk/coreboot-v2/targets/emulation/qemu-x86/Config-car.lb
===================================================================
--- trunk/coreboot-v2/targets/emulation/qemu-x86/Config-car.lb (rev 0)
+++ trunk/coreboot-v2/targets/emulation/qemu-x86/Config-car.lb 2009-06-16 15:02:52 UTC (rev 4357)
@@ -0,0 +1,26 @@
+# This will make a target directory of ./emulation_qemu-x86
+
+target qemu-x86-car
+mainboard emulation/qemu-x86
+
+option USE_DCACHE_RAM=1
+option CONFIG_USE_INIT=1
+option ROM_SIZE=512*1024
+option CONFIG_USE_INIT=1
+option CONFIG_USE_PRINTK_IN_CAR=1
+
+option CC="gcc -m32"
+
+option HAVE_PIRQ_TABLE=1
+option IRQ_SLOT_COUNT=6
+
+romimage "fallback"
+ option USE_FALLBACK_IMAGE=1
+ option ROM_IMAGE_SIZE=0x10000
+ option COREBOOT_EXTRA_VERSION="-GRUB2"
+# payload /home/stepan/core.img
+ payload ../payload.elf
+end
+
+buildrom ./coreboot.rom ROM_SIZE "fallback"
+
Modified: trunk/coreboot-v2/targets/emulation/qemu-x86/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/emulation/qemu-x86/Config.lb 2009-06-12 14:20:27 UTC (rev 4356)
+++ trunk/coreboot-v2/targets/emulation/qemu-x86/Config.lb 2009-06-16 15:02:52 UTC (rev 4357)
@@ -9,6 +9,8 @@
option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=6
+option DEFAULT_CONSOLE_LOGLEVEL=9
+option MAXIMUM_CONSOLE_LOGLEVEL=9
romimage "normal"
option COREBOOT_EXTRA_VERSION="-GRUB2"
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