[coreboot] Found information on i810 ram init
joe at settoplinux.org
Fri Jun 12 19:46:14 CEST 2009
I found a doc that explains ram init on the Intel 810 chipset, thought it
may be of use to someone.
MEMORY DETECTION AND CONFIGURATION
This system uses the Serial Presence Detect (SPD) method of determining the
configuration. The BIOS communicates with an EEPROM on each DIMM through an
bus to obtain data on the following DIMM parameters:
* Timing/CAS latency
NOTE: Refer to Chapter 3, “Processor/Memory Subsystem” for the SPD
format and DIMM
data specific to this system.
The BIOS performs memory detection and configuration with the following
1. Set Memory Buffer Strength – The memory controller must be configured
for correct buffer
drive strength. The BIOS provides this function by reading the number of
ECC enable/disable status, and SDRAM width data from the DIMMs and
data to the memory controller. SPD bytes checked: 5, 11, 13
2. Determine DIMM Presence/Type – The BIOS checks each memory socket for
presence. If present, the DIMM type and CAS latency is determined. SPD
bytes checked: 2,
9, 10, 18, 23, 24.
a. SPD byte 2 is read for all slots first. A failed read or returned
value of other than 02h
(EDO) or 04h (SDRAM) results in the slot marked as empty. If mixed types
then only SDRAMs are used (see chapter 3 for details).
b. SPD byte 18 is read for maximum CAS latency, followed by reads of
bytes 9 and 10 for
bus speed compatibility. A DIMM detected as too-slow results in an error.
c. If the DIMM can handle the memory bus speed at maximum CAS latency
then bytes 23
and 24 are checked to see if the DIMM can work maximum CAS latency minus 1.
all slots are checked, the greatest CAS latency (2 or 3) is used. A DIMM
incompatible will result in a bit in CMOS being set and the Num Lock LED on
keyboard will blink for a short time. Depending on the progress of the BIOS
POST message may be displayed before the system locks up.
3. Initialize SDRAM – If SDRAM are installed then each row containing
SDRAM will be
initialized. This step includes pre-charging all banks, sending a
sending a Mode-Register-Set-Enable command, reading DIMM location/CAS
and sending a Normal Op command.
4. Memory Sizing – The SPD bytes 3, 4, and 17 are checked for number of
row and column
addresses and (for SDRAM) the number of internal banks.
5. Memory Timing – For SDRAM, the memory controller requires the RAS
and the RAS-to-CAS delay time. SPD bytes checked: 27and 29.
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