[coreboot] write/verify bug

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Fri Jun 12 18:24:24 CEST 2009

On 12.06.2009 17:57, Richard Smith wrote:
> Urja Rannikko wrote:
>> * Verifies erase
>> * Writes each page, verifying each page after writing
> When using an external programmer verifying after each page will
> increase your programming time considerably due to the turn around
> time of the read.  On our USB 4232H based programmer each extra
> separate USB operation costs you about 1ms due to various bits of
> setup overhead.
> On the 8Mbit OLPC part with 256 byte pages that 4096 pages.  So 4
> about seconds for each additional USB transaction.

The idea is to check if the erase worked after each erase operation.
Basically, if you have an eraseblock size of 64 kByte, there should be
exactly one 64 kByte read after erasing. I have not yet seen SPI chips
with 256 Byte eraseblock size, but if you did, please tell me the part
number so I can take a look at the data sheet.

For writes, this is a bit different since writing is more complicated
than erasing. There are SPI chips which only write one byte at a time...
that also means we have 1 M write transactions alone for an 8 Mbit chip.
Since recovering from a failed write is not as simple as writing again
(you may have to erase the chip), performing a full-chip verify after a
full-chip write would address your latency concerns and still be a
sensible solution AFAICS.



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