[coreboot] Raminit help
stepan at coresystems.de
Tue Jun 9 19:06:41 CEST 2009
On 09.06.2009 18:48 Uhr, Myles Watson wrote:
> I've yanked all of the sdram initialization from my s2895 so that I
> can use my HT device as RAM. I've set up the BARs in the device and
> in the Opteron so that I should have access to 0-2GB. It hangs here:
> testx = 5a5a5a5a
> Copying data from cache to RAM -- switching to use RAM as stack...
> Somehow the memory accesses aren't reaching my device. I added some
> debugging, and this line before the debugging:
> set_var_mtrr(0, 0x08000000, 0x10000000, MTRR_TYPE_WRBACK);
Hm.. doesn't the base address need at least an alignment of size?
Have you tried disabling caching completely for the area?
> // Try to force the values out of the cache.
If you are trying to avoid the accesses from being cached, they need to
cross a cache line.
On the core duo a cache line is 0x40 bytes, so I used an offset of 0x80
for a dual channel interleaving system between memory accesses in order
to make sure that I read from the same DIMM and still cross the cache
> *((volatile u32 *)0x08180000) = 0x5a5a5a50;
> *((volatile u32 *)0x08180008) = 0x5a5a5a51;
> *((volatile u32 *)0x08180010) = 0x5a5a5a52;
> *((volatile u32 *)0x08180018) = 0x5a5a5a53;
> *((volatile u32 *)0x08180020) = 0x5a5a5a54;
> *((volatile u32 *)0x08180028) = 0x5a5a5a55;
> *((volatile u32 *)0x08180030) = 0x5a5a5a56;
> *((volatile u32 *)0x08180038) = 0x5a5a5a57;
> *((volatile u32 *)0x08180040) = 0x5a5a5a58;
The above accesses would imho not cross a cache line, unless a cache
line on opteron is as small as 8 byte, which I find hard to believe.
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