[coreboot] Via EPIA-N(L) C3/CN400 Support - Help Wanted

Harrison, Jon (SELEX GALILEO, UK) jon.harrison at selexgalileo.com
Tue Jun 9 09:35:14 CEST 2009


Myles,

Thanks for the link, that's exactly what I've been looking for! I seem
to have been looking round the coreboot pages for days on end and
managed to miss this.

I've not had a play with qemu, but have seen it mentioned on the list.

I think that's my next port of call. I'll have more of a tinker first.

Regards,
Jon 

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Sent: 09 June 2009 07:29
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Subject: coreboot Digest, Vol 52, Issue 65

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Today's Topics:

   1. Re: Via EPIA-N(L) C3/CN400 Support - Help Wanted (Myles Watson)
   2. Re: Is this boar/chipset combination supported? (saueimer)
   3. Re: Is this boar/chipset combination supported? (Stefan Reinauer)
   4. Re: [v3] r1170 - coreboot-v3/util/x86emu (ron minnich)
   5. Re: Is this boar/chipset combination supported? (ron minnich)
   6. Re: Via EPIA-N(L) C3/CN400 Support - Help Wanted (bari)
   7. VIA VT8235 + SST39SF020A problem (Murawski Mateusz)
   8. Re: [v3] r1170 - coreboot-v3/util/x86emu (Stefan Reinauer)


----------------------------------------------------------------------

Message: 1
Date: Mon, 8 Jun 2009 15:09:15 -0600
From: Myles Watson <mylesgw at gmail.com>
To: Jon Harrison <bothlyn at blueyonder.co.uk>
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] Via EPIA-N(L) C3/CN400 Support - Help Wanted
Message-ID:
	<2831fecf0906081409i3c9ce565t5166997f40949d74 at mail.gmail.com>
Content-Type: text/plain; charset=ISO-8859-1

> I'm currently working on porting coreboot to the Via EPIA-N(L) i.e.
> C3/CN400/VT8237R/Winbond SuperIO.

Welcome!

> I'm a fairly competent embedded systems designer/coder, and I'm aiming
to
> get to the point where I can use the EPIA to run a small linux kernel
and
> custom service from flash to act as a data logger from a custom
perpheral to
> a SATA disk.
>
> I'm not NDAd with Via (spent months trying to do this and gave up
?after
> getting the run around for so long) ?but have aquired some data on the
CN400
> that has allowed me to get this far. I don't have the BIOS Porting
Guide,
> which suspect would be quite illuminating, if there is anyone out
there who
> does have this and could review/correct my code for errors I'd
appreciate
> it.
I'm not the right person for that, but hopefully this will help a little
anyway.

> I've got to the point where I have flashrom programming the board, I
have a
> working build environment for V2 which is running the early romcc
compiled
> code and seems to have done the CN400 meminit stuff OK, near as I can
tell I
> am able to access SDRAM OK from romcc code (the early serial stuff is
up and
> running OK, and i can get debug out that way), but I'm getting strange
> things happening when jumping to copy_and_run_core.

A log file would probably be helpful.

> I think that the basic problem is a linking/location problem.
>
> Options.lb doesn't seem to let me turn on print_spew in the gcc code
but
> works OK in the romcc code, and

> the .map file looks suspicious to me with
> loads of constants all defined at the same location.

It's probably fine, but you can compare with the map file of a working
board to see what it looks like.  There are several constants defined
at the same location, and the build process will usually fail if
they're wrong.

> I'm happy to do the leg work if someone can give me a steer into how
all of
> the different ROM_SIZE, ROM_SECTION_SIZE PAYLOAD_SIZE, FALLBACK_SIZE
etc.
> etc. relate to the linking and location of code. I'm finding this a
bit
> impenetrable at the moment.

Have you seen this page?
http://www.coreboot.org/Anatomy_of_a_Failover_coreboot_v2_Image

You probably want an image that only contains fallback, which makes
life simpler anyway.

Have you played around with qemu?  It has a single image solution
implemented with CBFS (which is new) or you can go back a few
revisions to before CBFS.

Thanks,
Myles



------------------------------

Message: 2
Date: Mon, 8 Jun 2009 23:01:19 +0200
From: saueimer <saueimer at googlemail.com>
To: coreboot at coreboot.org
Subject: Re: [coreboot] Is this boar/chipset combination supported?
Message-ID:
	<51ec7b340906081401r592aa780h41beddd0a9510763 at mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"

Hi again,

how about the
VIA EPIA EX15000G, CX700M2 (PC2-4200U DDR2)
mainboard? Is or will this be supported? I am trying to build up a PC
for
my car so I need a ITX-motherboard and a DVI-Port. Coreboot in
cobination
with a SSD as harddisk would ensure a very quick boot ;) So if anyone
could advise some board to me, if the upper one is not supported,
I would really apprechiate it!

Thanks in advance!

2009/6/5 Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

> Hi,
>
> On 05.06.2009 12:59, saueimer wrote:
> > Jetway JNC62K SocketAM2/AM2+ Mini-ITX
> >
>
> Unfortunately the NVidia MCP78S chipset is not supported yet and it is
> unlikely we'll support it in the future because we don't have the
needed
> data sheets and programming information.
>
> Regards,
> Carl-Daniel
>
> --
> http://www.hailfinger.org/
>
>
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Message: 3
Date: Mon, 08 Jun 2009 23:50:30 +0200
From: Stefan Reinauer <stepan at coresystems.de>
To: saueimer <saueimer at googlemail.com>
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] Is this boar/chipset combination supported?
Message-ID: <4A2D87A6.4050608 at coresystems.de>
Content-Type: text/plain; charset="utf-8"

On 08.06.2009 23:01 Uhr, saueimer wrote:
> Hi again,
>
> how about the
>
>
>       VIA EPIA EX15000G, CX700M2 (PC2-4200U DDR2)
>
>
> mainboard? Is or will this be supported? I am trying to build up a PC
for
> my car so I need a ITX-motherboard and a DVI-Port. Coreboot in
cobination
> with a SSD as harddisk would ensure a very quick boot ;) So if anyone
> could advise some board to me, if the upper one is not supported,
> I would really apprechiate it!
>
The chipset is supported, we released it a while back. Check the
via/vt8454c target for a mainboard using that chipset.

Best regards,

Stefan



-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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Message: 4
Date: Mon, 8 Jun 2009 15:52:26 -0700
From: ron minnich <rminnich at gmail.com>
To: Joseph Smith <joe at settoplinux.org>
Cc: Stefan Reinauer <stepan at coresystems.de>, Ren? Reuter
	<reuter.rene at googlemail.com>,	coreboot at coreboot.org
Subject: Re: [coreboot] [v3] r1170 - coreboot-v3/util/x86emu
Message-ID:
	<13426df10906081552i5ad95395lf392643b61593361 at mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"

Fix attached for qemu.

It would be nice to know if this causes trouble for real hardware,
but it should not.

ron
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Message: 5
Date: Mon, 8 Jun 2009 15:53:49 -0700
From: ron minnich <rminnich at gmail.com>
To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Cc: saueimer <saueimer at googlemail.com>, coreboot at coreboot.org
Subject: Re: [coreboot] Is this boar/chipset combination supported?
Message-ID:
	<13426df10906081553x1a16aa5p539dcb5ace65415e at mail.gmail.com>
Content-Type: text/plain; charset=ISO-8859-1

On Fri, Jun 5, 2009 at 4:54 AM, Carl-Daniel
Hailfinger<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> Unfortunately the NVidia MCP78S chipset is not supported yet and it is
> unlikely we'll support it in the future because we don't have the
needed
> data sheets and programming information.


Actually, depending on how complex that chipset is, serialice might
let us figure out what we need to know ...

ron



------------------------------

Message: 6
Date: Mon, 08 Jun 2009 18:11:31 -0500
From: bari <bari at onelabs.com>
To: Jon Harrison <bothlyn at blueyonder.co.uk>
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] Via EPIA-N(L) C3/CN400 Support - Help Wanted
Message-ID: <4A2D9AA3.80200 at onelabs.com>
Content-Type: text/plain; charset=ISO-8859-1; format=flowed

Jon Harrison wrote:
> Hi Guys,
> 
> I'm currently working on porting coreboot to the Via EPIA-N(L) i.e. 
> C3/CN400/VT8237R/Winbond SuperIO.

I have a few SP13000's sitting in storage and all the docs but no time. 
The cn400 is EOLed by VIA.

I may be of some help if you post an LSPCI and I may be able to answer a

few questions. The C3 and vt8327r is already supported.

-Bari



------------------------------

Message: 7
Date: Tue, 09 Jun 2009 01:19:39 +0200
From: Murawski Mateusz <matowy at tlen.pl>
To: Coreboot <coreboot at coreboot.org>
Subject: [coreboot] VIA VT8235 + SST39SF020A problem
Message-ID: <4A2D9C8B.8050404 at tlen.pl>
Content-Type: text/plain; charset=ISO-8859-2; format=flowed

Hi
I have Albatron PM266A PRO motherboard (VIA P4M266A/8235 + SST39SF020A)
http://www.albatron.com.tw/English/product/mb/pro_detail.asp?rlink=Speci
fication&no=56
http://www.sst.com/downloads/datasheet/S71147.pdf

Flashrom rev 580 can't detect flash chip.
SST39SF020A is marked as OK_PREW
http://coreboot.pastebin.com/m779fa4b8



------------------------------

Message: 8
Date: Tue, 09 Jun 2009 08:29:04 +0200
From: Stefan Reinauer <stepan at coresystems.de>
To: ron minnich <rminnich at gmail.com>
Cc: Joseph Smith <joe at settoplinux.org>, Ren? Reuter
	<reuter.rene at googlemail.com>,	Peter Stuge <peter at stuge.se>,
Alexander
	Graf <alex at csgraf.de>,	coreboot at coreboot.org
Subject: Re: [coreboot] [v3] r1170 - coreboot-v3/util/x86emu
Message-ID: <4A2E0130.7010703 at coresystems.de>
Content-Type: text/plain; charset="utf-8"

On 09.06.2009 0:52 Uhr, ron minnich wrote:
> Fix attached for qemu.
>
>   
Awesome! Thanks for spotting this!

> It would be nice to know if this causes trouble for real hardware,
> but it should not.
>
> ron
>   
>
------------------------------------------------------------------------
>
> There are some problems with the way these interrrupts were managed.
First, the CLI erases
> any knowledge of whether interrupts were enabled or disabled. Second,
the STI
> works badly on qemu; we get an immediate INT #0 as soon as the STI
happens.
>
>   

Is this a Qemu bug?

> This doesn't happen on real hardware but, that said, I don't think
> this code should be doing cli and sti.
>   

Peter Stuge brought this up, and I think I remembered seeing somewhere
that loading the IDT and some other stuff should be guarded by  cli+sti
because otherwise an interrupt could happen during the switch?!? Not
sure. It looks highly unlikely that this would happen for us.

Peter? Alex? Do you guys have more insight?

> This change fixes the observed qemu failures.
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>
>   

I hope we find out why this is a problem, because a combination of
cli+sti should never cause an interrupt that would not exist without
cli+sti. If we can't I suggest we commit this in a few days (Acked-by:
Stefan Reinauer <stepan at coresystems.de>) since it fixes the problem.


-- 
coresystems GmbH ? Brahmsstr. 16 ? D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 ? Fax: +49 761 7664613
Email: info at coresystems.de  ? http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg ? HRB 7656
Gesch?ftsf?hrer: Stefan Reinauer ? Ust-IdNr.: DE245674866

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