[coreboot] Looking for pci-e memory

Myles Watson mylesgw at gmail.com
Fri Jun 5 19:21:36 CEST 2009

On Fri, Jun 5, 2009 at 11:15 AM, ron minnich <rminnich at gmail.com> wrote:
> Ah, well, I want to set up all the RAM for a system to have the kind
> of timing that PCM FLASH has. This can't be done with any existing ram
> controller, but it could be done with a two-socket opteron system with
> an FPGA in one socket .
Yes.  So you want to just have an artificial delay which varies based
on write/read, possibly address if you have some caching, etc.

Very doable, I think.

The problem I'm having right now is with unaligned writes.  I was
hoping that the Opteron would allocate a cache line on a miss to
cacheable memory space, and therefore never write partial lines.  So
far I haven't gotten that to work.  Reads are aligned, but partial
writes are easy to generate.

Am I forgetting something?  TLB settings maybe?  Opteron settings for
allocate on write?


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