[coreboot] [patch] some obvious bugs in rs690
Bao, Zheng
Zheng.Bao at amd.com
Wed Jun 3 08:22:48 CEST 2009
This patch is about some noticeable bugs which are made by no reason.
1. In rs690_cmn.c, mask the lower 4 bits of the BAR3. No doubt, right?
2. In rs690_pcie.c,
(1) Obviously, the mask should be 0xF, and bit 19 should be set to 1
(in comment).
In rpr 5.10.2, step 2, step 2.1 & step 2.6
(2) The dynamic buffer allocation is enabled by setting bit 11 of
PCIEIND: 0x20,
instead of PCIEIND_P: 0x20.
In rpr 5.10.2, step 5. Dynamic Slave CPL Buffer Allocation
Signed-off-by: Zheng Bao <zheng.bao at amd.com>
------------------
diff -Nuar -x .svn ./src/southbridge/amd/rs690/rs690_cmn.c
../coreboot-v2-current/src/southbridge/amd/rs690/rs690_cmn.c
--- ./src/southbridge/amd/rs690/rs690_cmn.c 2009-05-12
17:32:24.000000000 +0800
+++ ../coreboot-v2-current/src/southbridge/amd/rs690/rs690_cmn.c
2009-06-02 16:58:01.000000000 +0800
@@ -49,7 +49,7 @@
u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg)
{
/*get BAR3 base address for nbcfg0x1c */
- u32 addr = pci_read_config32(nb_dev, 0x1c);
+ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
printk_debug("addr=%x,bus=%x,devfn=%x\n", addr,
dev->bus->secondary,
dev->path.pci.devfn);
addr |= dev->bus->secondary << 20 | /* bus num */
@@ -62,7 +62,7 @@
u32 reg_old, reg;
/*get BAR3 base address for nbcfg0x1c */
- u32 addr = pci_read_config32(nb_dev, 0x1c);
+ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
/*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr,
dev->bus->secondary,
dev->path.pci.devfn);*/
addr |= dev->bus->secondary << 20 | /* bus num */
diff -Nuar -x .svn ./src/southbridge/amd/rs690/rs690_pcie.c
../coreboot-v2-current/src/southbridge/amd/rs690/rs690_pcie.c
--- ./src/southbridge/amd/rs690/rs690_pcie.c 2009-06-03
12:01:42.000000000 +0800
+++ ../coreboot-v2-current/src/southbridge/amd/rs690/rs690_pcie.c
2009-06-03 14:40:00.000000000 +0800
@@ -212,8 +212,8 @@
set_pcie_enable_bits(nb_dev, 0x02 | PCIE_CORE_INDEX_GPPSB, 1 <<
0, 1 << 0); /* no description in datasheet. */
/* init GPPSB port */
- /* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101
and shortens the enumeration timer by setting bit[19] to 0*/
- set_pcie_enable_bits(dev, 0x70, 7 << 16, 0xd << 16);
+ /* Sets RCB timeout to be 100ms by setting bits[18:16] to 3 b101
and shortens the enumeration timer by setting bit[19] to 1*/
+ set_pcie_enable_bits(dev, 0x70, 0xF << 16, 0xd << 16);
/* PCIE initialization 5.10.2: rpr 2.4 */
set_pcie_enable_bits(dev, 0x02, ~0xffffffff, 1 << 14);
/* Do not gate the electrical idle from the PHY and enables the
escape from L1L23 */
@@ -240,7 +240,7 @@
}
/* step 5: dynamic slave CPL buffer allocation */
- set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11);
+ set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 <<
11, 1 << 11);
/* step 5a: Training for GPP devices */
/* init GPP */
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