[coreboot] IOAPIC Initialisation - How much do you have to do ??

[Harrison, Jon (SELEX GALILEO, UK)]

Hi Rudolf,

Thanks for the reply.

I agree that it seems very like a resource conflict or the irq delivery
method
that is wrong.

See below for detailed responses.

Jon

-----Original Message-----
From: Rudolf Marek [mailto:r.marek at assembler.cz] 
Sent: 23 July 2009 17:05
To: Harrison, Jon (SELEX GALILEO, UK)
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] IOAPIC Initialisation - How much do you have to
do ??

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Hi,

I will leave for a holiday today. Its difficult to answer that without
the patch
 at hand.

The ..TIMER: vector=0x31 apic1=0 pin1=2 apic2=-1 pin2=-1
..MP-BIOS bug: 8254 timer not connected to IO-APIC

Means that:

ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)

For some reason this is wrong. You have same line in the orig bios?
[Yes]
If yes there is still smth wrong with APIC. Please check:

Assigned: PCI: 00:10.4 10 *  [0xfebffd00 - 0xfebffdff] mem
Assigned: PCI: 00:10.5 10 *  [0xfebffe00 - 0xfebffeff] mem
Assigned: PCI: 00:12.0 14 *  [0xfebfff00 - 0xfebfffff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fec00000 size: 300
align: 8
gran: 0 done <-- This is a reservation for the IOAPIC

This looks like the mem resources are setup from too high overlaping the
IOAPIC
with some hardware. No good. Move all resource bases bellow f0000000.
You will
need to adjust the northbridge.c and put the PCI resource limit to the
address
above most likely. Others can help here.

--> Don't think this is the issue IOAPIC starts at 0xfecxxxxx and is
reserved
--> correctly. Perhaps the allocation is unecessary / confusing though.

Also it seems that you created something in half:

ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 6 7 *10 11 12)
ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 6 7 10 *11 12)
ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 6 7 10 11 *12)
ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 6 7 10 *11 12), disabled.
ACPI: PCI Interrupt Link [ATAI] (IRQs *20)
ACPI: PCI Interrupt Link [USBI] (IRQs *21)
ACPI: PCI Interrupt Link [VT8I] (IRQs *22)
ACPI: PCI Interrupt Link [NICI] (IRQs *23)

This means you route half of IRQs through APIC and second half through
the 8259.
Why not route all of them through APIC. Check M2V-MX se board _PRT
methods.

INTA# to IRQ16
INTB# to IRQ17
INTC# to IRQ18
INTD# to IRQ19

--> It might look that way but the they are routed to GSI 10 to 12 
--> on the IOAPIC. The only rationale is that this matches what 
--> Award does on this board. I guess I could change this but
--> not convinced that it'll make any difference.

uhci_hcd 0000:00:10.0: Unlink after no-IRQ?  Controller is probably
using the wrong IRQ.  <<---- Whoops !!

Yes maybe but I think all USBs are routed to IRQ21 so it must be smth
else. Like
the resource conflict I mentioned above. If VT8237R apic is enabled (and
it is)
this is routed like this:

IDE (Native Mode)/SATA IRQ & INTE to IRQ20
USB IRQ (all 5 functions) and INTF to IRQ21
AC'97 / MC'97 IRQ and INTG to IRQ22
LAN IRQ and INTH to IRQ23

So I would recommend to boot now with init=/bin/bash
and provide

cat /proc/iomem
cat /proc/interrupts
lspci -vvvxxx

--> Ok. Good idea. I guess this may reveal something.

I'm going to be most likely AFK for a week so hopefully others can try
to help.

Most likely is the resource conflict in game. Also check if the APIC
messages
should be routed by extra bus or as part of FSB messages (there is some
bit for
that on 0xfec000smth) I think FSB routing is fine for VIA CPU too but
not sure.

--> Yes this sound most likely to me. Reg dump from Award config says
VT8237R
--> uses serial bus rather than FSB. Which I've copied and makes me
think that
--> there is some other setup in IOAPIC or LAPIC that needs to match.

rest looks OK to me. Please provide the WIP patch next time so one can
see how
you set things up.

--> Will do. Didn't do it this time because the patch is pretty unwieldy
at 
--> this time.

Thanks,


Rudolf





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