[coreboot] [FILO] EPIA-NL/CN400 Port.... FILO Booting kernel, init probs

[Harrison, Jon (SELEX GALILEO, UK)]

Hi Rudolf,

Thanks for the help.

I've been going for the second approach i.e. _PRT in dsdt.

I think I'd missed the need for messing with the LPC setup to fix the
routing.

I'll look at the VT8235 code as, I'm basing my work on the EPIA-M which
uses _PRT and the VT8235.

Thanks,
Jon

-----Original Message-----
From: Rudolf Marek [mailto:r.marek at assembler.cz] 
Sent: 14 July 2009 22:32
To: Harrison, Jon (SELEX GALILEO, UK)
Cc: coreboot at coreboot.org
Subject: Re: [coreboot] [FILO] EPIA-NL/CN400 Port.... FILO Booting
kernel, init probs

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Harrison, Jon (SELEX GALILEO, UK) wrote:
> Hi Folks,
> 
> I've added initial ACPI support to my EPIA-NL/CN400 Port.

Hmm pity is that it is not here so mine help is limited.

> I think the issues are concerned with the South Bridge Init (VT8237R),
There
> a bunch of USB UHCI problems reported and then the boot hangs
> configuring/mounting sda1

Perhaps it seems that PCI routing does not work. Does the CPU lacks
APIC? I
think PIC only mode needs some tuning to PCI router.

I dont know how you have done the LNKA etc devices in ACPI but you need
to
change the 0x55-0x57 in SB to reflect current settings.

You will need to implement _CRS and _SRS for that. Also there is some in
kernel
quirk that IRQ routing (non APIC) works only if the 0x3c is written with
right
value. Kernel will fix that.


 OperationRegion (SREG, PCI_Config, Zero, ...
                Field (SREG, ByteAcc, NoLock, Preserve)
                {
                    Offset (0x55),.
                        ,   4,.
                    PIRA,   4,.
                    PIRB,   4,.
                    PIRC,   4,.

and then for LNKA for example:

_SRS will need to parse the the IRQ resource from OS, which is stored as
bitmap.
Using findsetright bit/dec create a IRQ nr and store it in the PIRA ;)

Something could be taken from amd8111_pic.asl

Second possibility would be to create a PIR table and store the right
routing
values in the SB init code + ECLR should be modified. I never finished
this code
for VT8237R. Check VT8235 vt8235_lpc.c for details pci_routing_fixup.

Rudolf
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