[coreboot] [v2] r4425 - trunk/coreboot-v2/src/southbridge/amd/sb600

svn at coreboot.org svn at coreboot.org
Tue Jul 14 21:10:11 CEST 2009


Author: stepan
Date: 2009-07-14 21:10:10 +0200 (Tue, 14 Jul 2009)
New Revision: 4425

Modified:
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c
Log:
trivial fixes to function declarations (and build system test)

Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
Acked-by: Stefan Reinauer <stepan at coresystems.de>



Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c	2009-07-12 14:24:06 UTC (rev 4424)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c	2009-07-14 19:10:10 UTC (rev 4425)
@@ -38,7 +38,7 @@
 }
 
 /* Get SB ASIC Revision.*/
-static u8 get_sb600_revision()
+static u8 get_sb600_revision(void)
 {
 	device_t dev;
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
@@ -123,7 +123,7 @@
 }
 
 
-static u8 dual_core()
+static u8 dual_core(void)
 {
 	return (pci_read_config32(PCI_DEV(0, 0x18, 3), 0xE8) & (0x3<<12)) != 0;
 }
@@ -205,7 +205,7 @@
 }
 
 
-static void sb600_pci_port80()
+static void sb600_pci_port80(void)
 {
 	u8 byte;
 	device_t dev;
@@ -271,7 +271,7 @@
 
 
 /* sbDevicesPorInitTable */
-static void sb600_devices_por_init()
+static void sb600_devices_por_init(void)
 {
 	device_t dev;
 	u8 byte;
@@ -467,7 +467,7 @@
 * The index address is first programmed into IO reg 0xcd6.
 * Read or write values are accessed through IO reg 0xcd7.
 */
-static void sb600_pmio_por_init()
+static void sb600_pmio_por_init(void)
 {
 	u8 byte;
 
@@ -556,7 +556,7 @@
 * Compliant with CIM_48's sbPciCfg.
 * Add any south bridge setting.
 */
-static void sb600_pci_cfg()
+static void sb600_pci_cfg(void)
 {
 	device_t dev;
 	u8 byte;
@@ -645,7 +645,7 @@
 /*
 * Compliant with CIM_48's ATSBPowerOnResetInitJSP
 */
-static void sb600_por_init()
+static void sb600_por_init(void)
 {
 	/* sbDevicesPorInitTable + sbK8PorInitTable */
 	sb600_devices_por_init();
@@ -658,7 +658,7 @@
 * Compliant with CIM_48's AtiSbBeforePciInit
 * It should be called during early POST after memory detection and BIOS shadowing but before PCI bus enumeration.
 */
-static void sb600_before_pci_init()
+static void sb600_before_pci_init(void)
 {
 	sb600_pci_cfg();
 }





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