[coreboot] [PATCH] Fix out{b,l} buglets
Ed Swierk
eswierk at aristanetworks.com
Fri Jul 10 08:32:13 CEST 2009
Apparently I'm not the only one who forgets which way the outb and outl
arguments go.
Signed-off-by: Ed Swierk <eswierk at aristanetworks.com>
---
Index: coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
===================================================================
--- coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c (revision 4415)
+++ coreboot-v2/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c (working copy)
@@ -38,7 +38,7 @@
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
}
if( byte != byte_old) {
- outb(0x70, byte);
+ outb(byte, 0x70);
}
Index: coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c
===================================================================
--- coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c (revision 4415)
+++ coreboot-v2/src/southbridge/nvidia/ck804/ck804_lpc.c (working copy)
@@ -245,7 +245,7 @@
byte |= (1 << 7); /* Can't mask NMI from PCI-E and NMI_NOW. */
}
if (byte != byte_old)
- outb(0x70, byte);
+ outb(byte, 0x70);
/* Initialize the real time clock (RTC). */
rtc_init(0);
Index: coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
===================================================================
--- coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c (revision 4415)
+++ coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c (working copy)
@@ -230,7 +230,7 @@
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
}
if( byte != byte_old) {
- outb(0x70, byte);
+ outb(byte, 0x70);
}
/* Initialize the real time clock */
Index: coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c
===================================================================
--- coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c (revision 4415)
+++ coreboot-v2/src/southbridge/sis/sis966/sis966_lpc.c (working copy)
@@ -220,7 +220,7 @@
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
}
if( byte != byte_old) {
- outb(0x70, byte);
+ outb(byte, 0x70);
}
/* Initialize the real time clock */
Index: coreboot-v2/src/cpu/amd/sc520/raminit.c
===================================================================
--- coreboot-v2/src/cpu/amd/sc520/raminit.c (revision 4415)
+++ coreboot-v2/src/cpu/amd/sc520/raminit.c (working copy)
@@ -183,16 +183,16 @@
/* Stepan says: This needs to go to the msm586seg code */
/* "enumerate" the PCI. Mainly set the interrupt bits on the PCnetFast. */
- outl(0xcf8, 0x08000683c);
- outl(0xcfc, 0xc); /* set the interrupt line */
+ outl(0x08000683c, 0xcf8);
+ outl(0xc, 0xcfc); /* set the interrupt line */
/* Set the SC520 PCI host bridge to target mode to
* allow external bus mastering events
*/
/* index the status command register on device 0*/
- outl(0x0cf8,0x080000004);
- outl(0xcfc, 0x2); /*set the memory access enable bit*/
+ outl(0x080000004, 0x0cf8);
+ outl(0x2, 0xcfc); /*set the memory access enable bit*/
OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */
}
More information about the coreboot
mailing list