[coreboot] generic cpu detection proposal

[Holger Hesselbarth]

sorry for this rather long post. it's an update on the generic cpu detection and 
initialization source. this update makes it a lot easier to understand what i'm 
trying to achive (hello Stefan ;)). there are still some essential things 
missing but that's merely due to unavailable information. if there are questions 
left don't bother asking!

microcode loading could be nicely inserted into the switch-statement in 
configure_cpu() in config_intel.c this is where model-specific things should go, 
too.

next thing i'm going to write is the L2 cache initalization. to understand the 
idea of my L2 cache initialization routine take a look at

Intel® 64 and IA-32 Architectures Software Developer's Manual
Volume 3B: System Programming Guide, Part 2

page B.155ff for reference. i'll be calling the registers by the names given in 
the reference. according to my understanding the following steps have to be 
taken for a generic P6 L2 cache algorithm:

1. read IA32_PLATFORM_ID to obtain L2 Cache Latency and Clock Frequency Ratio 
(we can save Platform Id, too. we'll need it for the microcode update!)
2. read BBL_CR_CTL3 and check L2 Hardware Disable. if set the L2 cache is 
hardware disabled. nothing we can do about that, so just exit the routine.
3. set L2 Physical Address Range, L2 Enabled, L2 Cache Latency; clear L2 
Configured and write BBL_CR_CTL3 back
4. fill the L2 cache with 0 and mark the whole cache invalid by using 
BBL_CR_ADDR, BBL_CR_D[0:3], BBL_CR_CTL and the table pointer(s) from 
query_cache_size()
5. read BBL_CR_CTL3, set L2 Configured and write BBL_CR_CTL3 back
6. done :)

unanswered questions:
- what happens if there's more than one L2 cache type found? shouldn't happen on 
the P6 architecture, but what about Core/Core2/Nehalem?
- L2 cache pointer array in cpu.h has a fixed size of 8. on the P6 architecture 
we would only need one pointer because they only have one L2 cache array per 
core. not sure what we need for Core/Core2/Nehalem. the routines writing to the 
array (in query_cache_size()) don't check for any boundaries. this is 
potentially dangerous. is there a need to care about this?
- is there a default value for L2 Physical Address Range? 4GB?
- what about L2 ECC? i've no idea how it's intended to work.
- some intel cpus support verbose processor identification strings (like 
Intel(R) Pentium(R) 4 CPU 1500MHz) others use a brand index table from which a 
verbose identification string can be build. do we need this? we could also 
display family, model, stepping and some additional information (cache size, 
cache speed and cpu core speed). should we display anything at all?
- is there a need to know the cpu core multiplier and the system bus frequency? 
they are on EBL_CR_POWERON.
- what about L1 cache? do we need to know its size to display it? what about L3 
cache? i've currently no information on configuring L3 cache.

what i currently need:
- values of msr IA32_PLATFORM_ID, EBL_CR_POWERON and BBL_CR_CTL3 when booted 
with coreboot (e.g. untouched). does inteltool support dumping msrs? Uwe, can 
you report back with those values?

anyone with L2/L3 cache register information on anything newer than the intel P6 
architecture? i guess there's a document on L2/L3 cache detection and init 
available from intel. at least if you are AWARD/Phoenix or AMI.
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