[coreboot] MTRR setup strategy

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Sun Jan 25 01:45:57 CET 2009

On 25.01.2009 00:43, Stefan Reinauer wrote:
> On 24.01.2009 23:21 Uhr, Carl-Daniel Hailfinger wrote:
>> On 24.01.2009 20:58, Stefan Reinauer wrote:  
>>> Carl-Daniel Hailfinger wrote:
>>>> Example:
>>>> We want to cache 0MB - (2G-64M-64k).
>>> Where do the 64k come from?
>> That was specific to Jason's setup. IIRC the 64k were ACPI memory or
>> somesuch.
> Any reason why that shouldn't be cachable?

No idea. Maybe nonserialized concurrent accesses by multicore APCI
interpreters? (Is that even possible?)

> From a memory perspective, it's just normal memory, not graphics memory
> or some such.

That would certainly reduce the number of MTRRs needed quite a lot.

> This might even be caused by my high tables patch from recently, but it
> looks like a bug to me.

The tables should be cacheable as well, right?

We need a really LOUD SCREAMING (probably CRIT/EMERG) warning if we run
out of MTRRs.



More information about the coreboot mailing list