[coreboot] MTRR setup strategy

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Sat Jan 24 23:10:43 CET 2009

On 24.01.2009 22:47, Corey Osgood wrote:
> I've already been working on it for v3, along with handling the cached flash
> area.


> Quick question though, what would happen if, for a few instructions,
> both MTRR0 and MTRR1 covered the flash area?

The AMD64 documentation says you can have as many overlapping MTRRs as
you want (subject to the number of available MTRRs). However, the MTRR
with the "worst" (uncached) memory type will always win. That means a
purely subtractive setup with 3 GB RAM makes it impossible to cache the
flash area.

So what do you do if you want 3 GB RAM and 1 MB ROM cached?
MTRR0: 0-2048 MB, size 2048 MB (writeback)
MTRR1: 2048-3072 MB, size 1024 MB (writeback)
MTRR2: 4095-4096 MB, size 1 MB (writeback)
MTRR default type: (uncached)

What does not work?
MTRR0: 0-4096 MB, size 4096 MB (writeback)
MTRR1: 3072-4096 MB, size 1024 MB (uncached)
MTRR2: 4095-4096 MB, size 1 MB (writeback)
MTRR default type: (uncached)
Here MTRR2 has no effect because it is overridden by the "worse" type of

> Also, I've been extremely busy
> lately and haven't had much time for coreboot, so I won't be offended if
> someone beats me to fixing this.

I'm glad you were working on this. Do you already have any code we can
use as a basis?



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