[coreboot] v3 bug report: Error base address register of UART in vt1211

[JasonZhao at viatech.com.cn]

-jasonzhao 

> -----Original Message-----
> From: ron minnich [mailto:rminnich at gmail.com]
> Sent: Tuesday, January 13, 2009 12:09 AM
> To: Jason Zhao
> Cc: c-d.hailfinger.devel.2006 at gmx.net; coreboot at coreboot.org
> Subject: Re: [coreboot] v3 bug report: Error base address register of UART in
> vt1211
> 
> On Sun, Jan 11, 2009 at 10:40 PM,  <JasonZhao at viatech.com.cn> wrote:
> > Hi Carl,
> > I find a bug need to fix in superior/via/vt1211/Stage1.c
> >        rawpnp_set_iobase(dev, 2, (iobase >> 2) & 0xff);
> >    should be
> >        rawpnp_set_iobase(dev, 0x60, ((iobase >> 2) & 0xff)<<8);
> 
> I Understand the 0x60. I don't understand this part:
> ((iobase >> 2) & 0xff)<<8)
Something copied from vt1211 spec:
5.1.1.1 UART1_RX60: Serial Port 1 Base Address  
Attribute: RW         Default Value: FEh 
Bit Description 
[7:1] ADR9~ADR3 
[0]  Must be 0
This will help to under stand why >>2,  and   <<8 is because the definition of function rawpnp_set_iobase：

void rawpnp_set_iobase(u16 port, u8 index, u16 iobase)
{
	rawpnp_write_config(port, index + 0, (iobase >> 8) & 0xff); /* MSB */
	rawpnp_write_config(port, index + 1, iobase & 0xff);	    /* LSB */
}
The rawpnp_set_iobase suppose the MSB of "iobase" is written into register 0x60, however vt1211 spec(above) says bit[3-9] should be written into this 0x60.

> 
> Is that correct? Not just (iobase >> 8)&0xff (although the &0xff is
> not really needed)
> 
> thanks
> 
> ron