[coreboot] [PATCH 1/2] cs5536: Add a NAND device and do the IDE PCI header disabling on time.

[Peter Stuge]

Mart Raudsepp wrote:
> Sorry, I meant that no existing board supported by coreboot has IDE
> and Flash interface wired at the same time currently.

Ah right! No, I haven't seen that. Seems a little unlikely because
IDE would be PIO only.


> Does your comment still apply then in relation to enable_ide
> existence perhaps?

Guess not. I think the motivation for enable_ide is simply one of
consistency. Most chipsets do not allow the IDE PCI device to be
hidden completely so enable_ide was added to control how it gets
configured.


> How is the selection between CF and IDE header done on those ALIX
> boards?

They're just parallell, and there's a master/slave jumper for the CF.


//Peter