[coreboot] Coreboot patches for v2 with SeaBIOS

Stefan Reinauer stepan at coresystems.de
Sat Feb 28 00:15:02 CET 2009

Myles Watson wrote:
> Does this work for you with 4G of RAM? 
My boards don't support that much.. :-( Have to try on the AMD boards
some time. But I guess if the chipset supports more than 4G you'd have
to put the high_table_base to the top of low memory (default would be
below 3G I guess) There's no structural problem that would disallow
using the mechanism with any amount of RAM.

>  I don't have a Kontron board,
> but I copied the implementation to the amdk8 northbridge code.  It
> works for me when I have the RAM "boosted" and it works when I boot
> with less than 4G, but if I boot with 4G it tries to put the high
> tables in the PCI decode space since they overlap.
> Besides that the patch is working well for me, and I'd like to see it merged.
> If it works in the 4G case and I just didn't implement it right for K8:
> Acked-by: Myles Watson <mylesgw at gmail.com>

Thanks, r3960

coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: info at coresystems.dehttp://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

More information about the coreboot mailing list