[coreboot] Coreboot patches for v2 with SeaBIOS

Marc Jones marcj303 at gmail.com
Fri Feb 27 18:50:39 CET 2009

On Fri, Feb 27, 2009 at 10:42 AM, Myles Watson <mylesgw at gmail.com> wrote:

> Does this work for you with 4G of RAM?  I don't have a Kontron board,
> but I copied the implementation to the amdk8 northbridge code.  It
> works for me when I have the RAM "boosted" and it works when I boot
> with less than 4G, but if I boot with 4G it tries to put the high
> tables in the PCI decode space since they overlap.
> Besides that the patch is working well for me, and I'd like to see it merged.
> If it works in the 4G case and I just didn't implement it right for K8:
> Acked-by: Myles Watson <mylesgw at gmail.com>

Do you have an off by 1 problem? That would cause the problem @ 4GB as
you described.


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