[coreboot] slow load times
mylesgw at gmail.com
Thu Feb 19 04:42:04 CET 2009
> -----Original Message-----
> From: Kevin O'Connor [mailto:kevin at koconnor.net]
> Sent: Wednesday, February 18, 2009 8:31 PM
> To: Myles Watson
> Cc: coreboot at coreboot.org
> Subject: Re: [coreboot] slow load times
> On Wed, Feb 18, 2009 at 07:51:33PM -0700, Myles Watson wrote:
> > > > > #define CONFIG_OPTIONROMS_DEPLOYED 0
> > Maybe we should modify buildrom so that this is the default when using
> > SeaBIOS.
> I think we should.
> > > The current code is in src/pci.h in the foreachpci macro and in
> > > src/pci.c in the pci_next() function. If there is a better way to
> > > scan, please let me know.
> > It's a fine way to scan. The problem is that there is no logical
> > from bus 0 to bus 0x40 on my machine. It happens because there are
> > links on the Opterons. For desktop machines, many times there is only
> > link that goes to the chipset, but servers and workstations sometimes
> > more.
> Well, that's a pain.
> I'm surprised they didn't just put a dummy
> bridge entry on bus 0 that points to bus 0x40 -- it'd make scanning
Part of the problem is that some of the buses are there only when the second
Opteron is installed. Nothing can be simple :)
You can read the Opteron's registers to know which other buses there are,
and the Opterons are always on bus 0. It's just not a general solution.
> You could change the pciforeach macro from:
> for (MAX=0x0100, BDF=pci_next(0, &MAX) \
> for (MAX=0x4000, BDF=pci_next(0, &MAX) \
For my own use I can hard code something pretty easily. The general case is
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