[coreboot] Coreboot patches for v2 with SeaBIOS

[Myles Watson]

On Fri, Feb 13, 2009 at 3:58 PM, Rudolf Marek <r.marek at assembler.cz> wrote:
> Hi,
>>>
>>> +       current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t
>>> *)
>>> +                                               current, 0, 9, 9, 0xF);
>>
>> This one matches the factory BIOS, but I'll try the other one.

Just to make sure, I added the override for 2.

 ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
 ACPI: BIOS IRQ0 pin2 override ignored.

> It should be OK to leave it as it is. You dont have another IRQ overrides?
> Perhaps there must be some for timer IRQ...

I don't know.  In the mptable, I see an interrupt from 0x0 t0 0x2, but
it is on bus 0x82, not bus 0.  It doesn't make too much sense to me.

add intsrc srcbus 0x82 srcbusirq 0x0, dstapic 0x4, dstirq 0x0
add intsrc srcbus 0x82 srcbusirq 0x1, dstapic 0x4, dstirq 0x1
add intsrc srcbus 0x82 srcbusirq 0x0, dstapic 0x4, dstirq 0x2
add intsrc srcbus 0x82 srcbusirq 0x3, dstapic 0x4, dstirq 0x3
add intsrc srcbus 0x82 srcbusirq 0x4, dstapic 0x4, dstirq 0x4
add intsrc srcbus 0x82 srcbusirq 0x6, dstapic 0x4, dstirq 0x6
add intsrc srcbus 0x82 srcbusirq 0x7, dstapic 0x4, dstirq 0x7
add intsrc srcbus 0x82 srcbusirq 0x8, dstapic 0x4, dstirq 0x8
add intsrc srcbus 0x82 srcbusirq 0xc, dstapic 0x4, dstirq 0xc
add intsrc srcbus 0x82 srcbusirq 0xd, dstapic 0x4, dstirq 0xd
add intsrc srcbus 0x82 srcbusirq 0xe, dstapic 0x4, dstirq 0xe
add intsrc srcbus 0x82 srcbusirq 0xf, dstapic 0x4, dstirq 0xf
add intsrc srcbus 0x0 srcbusirq 0x5, dstapic 0x4, dstirq 0xa
add intsrc srcbus 0x0 srcbusirq 0x8, dstapic 0x4, dstirq 0x15
add intsrc srcbus 0x0 srcbusirq 0x9, dstapic 0x4, dstirq 0x14
add intsrc srcbus 0x0 srcbusirq 0x10, dstapic 0x4, dstirq 0x14
add intsrc srcbus 0x0 srcbusirq 0x1c, dstapic 0x4, dstirq 0x17
add intsrc srcbus 0x0 srcbusirq 0x20, dstapic 0x4, dstirq 0x16
add intsrc srcbus 0x0 srcbusirq 0x28, dstapic 0x4, dstirq 0x15
add intsrc srcbus 0x2 srcbusirq 0x0, dstapic 0x4, dstirq 0x12
add intsrc srcbus 0x2 srcbusirq 0x1, dstapic 0x4, dstirq 0x13
add intsrc srcbus 0x2 srcbusirq 0x2, dstapic 0x4, dstirq 0x10
add intsrc srcbus 0x2 srcbusirq 0x3, dstapic 0x4, dstirq 0x11
add intsrc srcbus 0x1 srcbusirq 0x14, dstapic 0x4, dstirq 0x13
add intsrc srcbus 0x1 srcbusirq 0x10, dstapic 0x4, dstirq 0x10
add intsrc srcbus 0x1 srcbusirq 0x11, dstapic 0x4, dstirq 0x11
add intsrc srcbus 0x1 srcbusirq 0x12, dstapic 0x4, dstirq 0x12
add intsrc srcbus 0x1 srcbusirq 0x13, dstapic 0x4, dstirq 0x13
add intsrc srcbus 0x80 srcbusirq 0x28, dstapic 0x7, dstirq 0x15
add intsrc srcbus 0x81 srcbusirq 0x0, dstapic 0x7, dstirq 0x12
add intsrc srcbus 0x81 srcbusirq 0x1, dstapic 0x7, dstirq 0x13
add intsrc srcbus 0x81 srcbusirq 0x2, dstapic 0x7, dstirq 0x10
add intsrc srcbus 0x81 srcbusirq 0x3, dstapic 0x7, dstirq 0x11
add intsrc srcbus 0x41 srcbusirq 0x10, dstapic 0x6, dstirq 0x0
add intsrc srcbus 0x41 srcbusirq 0x11, dstapic 0x6, dstirq 0x1
add intsrc srcbus 0x41 srcbusirq 0x12, dstapic 0x6, dstirq 0x2
add intsrc srcbus 0x41 srcbusirq 0x13, dstapic 0x6, dstirq 0x3
add intsrc srcbus 0x41 srcbusirq 0x24, dstapic 0x6, dstirq 0x1
add intsrc srcbus 0x41 srcbusirq 0x25, dstapic 0x6, dstirq 0x2
add intsrc srcbus 0x41 srcbusirq 0x26, dstapic 0x6, dstirq 0x3
add intsrc srcbus 0x41 srcbusirq 0x27, dstapic 0x6, dstirq 0x0
add intsrc srcbus 0x41 srcbusirq 0x18, dstapic 0x6, dstirq 0x2
add intsrc srcbus 0x41 srcbusirq 0x19, dstapic 0x6, dstirq 0x3
add intsrc srcbus 0x41 srcbusirq 0x10, dstapic 0x5, dstirq 0x0
add intsrc srcbus 0x41 srcbusirq 0x11, dstapic 0x5, dstirq 0x1
add intsrc srcbus 0x41 srcbusirq 0x12, dstapic 0x5, dstirq 0x2
add intsrc srcbus 0x41 srcbusirq 0x13, dstapic 0x5, dstirq 0x3
add intsrc srcbus 0x82 srcbusirq 0x0, dstapic 0xff, dstirq 0x0
add intsrc srcbus 0x82 srcbusirq 0x0, dstapic 0xff, dstirq 0x1

Looking at this made me remember that only PCI0 gets parsed by the
kernel.  I don't know why it skips the other root buses.
 ACPI: bus type pci registered
 PCI: Using configuration type 1 for base access
 ACPI: EC: Look up EC in DSDT
 ACPI: Interpreter enabled
 ACPI: (supports S0 S5)
 ACPI: Using IOAPIC for interrupt routing
 ACPI: PCI Root Bridge [PCI0] (0000:00)
 PCI: 0000:00:01.0 reg 10 io port: [2400, 247f]
 PCI: 0000:00:01.0 reg 14 32bit mmio: [f5200000, f5200fff]
...
 PCI: 0000:02:00.0 reg 30 32bit mmio: [f5000000, f501ffff]
 PCI: bridge 0000:00:0e.0 32bit mmio: [f0000000, f50fffff]
 PCI: bridge 0000:00:0e.0 64bit mmio pref: [e0000000, efffffff]
 ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
 ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCIL._PRT]
 ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PE16._PRT]
 Linux Plug and Play Support v0.97 (c) Adam Belay
 pnp: PnP ACPI init
 ACPI: bus type pnp registered

I was expecting to see entries for PCI1 and PCI2.  When I run acpiexec
I can see them with the namespace command.

>
>> They are now identical except for the headers and the addresses of the
>> IOAPICs.
>
> hmm this is strange... maybe we can leave there the only irq9 override for
> now. But you will need to put APIC to virtual wire mode maybe.

As long as I make it match the mptable, shouldn't it just work?

Right now I can't get it to match because the other busses are never
parsed so those PRT entries are ignored.

Thanks,
Myles