[coreboot] r1125 - coreboot-v3/southbridge/amd/cs5536
svn at coreboot.org
svn at coreboot.org
Mon Feb 9 17:10:58 CET 2009
Date: 2009-02-09 17:10:58 +0100 (Mon, 09 Feb 2009)
New Revision: 1125
cs5536: Fix NAND Flash setup.
A NAND device may never be mapped above 0xEFFFFFFF, as these addresses never reach
the NAND controller. Only NAND controller, as the only DIVIL component that is
allowed to be memory mapped, is affected - other Geode LX and CS5536 peripherals
(that are separate GLIU devices outside DIVIL component) can use addresses above
that limit (see in-code comment for details).
In combination with a new VSA2 version 1.02 or newer, this makes NAND flash
finally work in coreboot v3.
Signed-off-by: Mart Raudsepp <mart.raudsepp at artecdesign.ee>
Signed-off-by: Anti Sullin <anti.sullin at artecdesign.ee>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
--- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2009-02-09 13:40:10 UTC (rev 1124)
+++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2009-02-09 16:10:58 UTC (rev 1125)
@@ -114,6 +114,26 @@
+static void nand_read_resources(struct device *dev)
+ /* All memory accesses in the range of 0xF0000000 - 0xFFFFFFFF routed to
+ * Diverse Integration Logic (DIVIL) get always sent to the device inside
+ * DIVIL as set in DIVIL_BALL_OPTS PRI_BOOT_LOC and SEC_BOOT_LOC bits
+ * (see CS5536 data book chapter 184.108.40.206 DIVIL_BALL_OPTS PRI_BOOT_LOC
+ * description).
+ * The virtual PCI address limit test gives us a false upper limit of
+ * 0xFFFFFFFF for this device, but we do not want NAND Flash to be using
+ * memory addresses 0xF0000000 and above as those accesses would end up
+ * somewhere else instead. Therefore if VSA2 gave us a MMIO resource for
+ * NAND Flash, patch this (fixed) resources higher bound to 0xEFFFFFFF.
+ if ((dev->resources >= 1) && (dev->resource.flags & IORESOURCE_MEM) &&
+ (dev->resource.limit > 0xefffffff))
+ dev->resource.limit = 0xefffffff;
* Power button setup.
@@ -737,7 +757,7 @@
.constructor = default_device_constructor,
.phase2_fixup = nand_phase2,
.phase3_scan = 0,
- .phase4_read_resources = pci_dev_read_resources,
+ .phase4_read_resources = nand_read_resources,
.phase4_set_resources = pci_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = 0, /* No Option ROMs */
More information about the coreboot