[coreboot] [v3][patch] Add early MTRR setup

Peter Stuge peter at stuge.se
Sat Feb 7 00:26:48 CET 2009

Marc Jones wrote:
> Setup the MTRRs in stage1 so that memory and cache are available throughout
> stage2. This fixes problems with VGA graphics ROMs access to 0xA0000-0xBFFFF.
> It also sets all system memory to WriteBack cached and sets the ROM
> area to cached.
> Signed-off-by: Marc Jones <marcj303 at gmail.com>

Acked-by: Peter Stuge <peter at stuge.se>

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