[coreboot] cached SMI handler

Stefan Reinauer stepan at coresystems.de
Fri Feb 6 23:50:26 CET 2009

ron minnich wrote:
> On Thu, Feb 5, 2009 at 5:43 PM,  <JasonZhao at viatech.com.cn> wrote:
>> I ask my colleague who work for EFI. He said in his EFI project, SMM
>> area should not be cached,  and he had tried to cache that area, but
>> cause system crashed.
>> I don't know if he is right, since I can not find any reason why SMM
>> area should not be cached.
> Stepan can tell us, since he has working smm on kontron, but I can not
> believe smm can not be cached.
Occasionally a CPU might do speculative readahead on the SMRAM memory
while not in SMM. The chipset will generate master aborts on the PCI
bus, so the cached data is incorrect (0xff) and upon SMM entry the CPU
goes to nirvana. The SMM area in ASEG is always uncached. The upper
SMRAM areas can be cached, but they must only be cached while in SMM. A
way to do this could be to set up an MTRR at the beginning of the SMI
handler and restoring it upon exit. When not in in the SMI handler, TSEG
or HSEG (high SMRAM and static address high SMRAM) must be uncached.


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