[coreboot] vga not working

Myles Watson mylesgw at gmail.com
Thu Aug 20 17:35:58 CEST 2009

> The ep80579 has two x4 lanes peripherals (00:02.0 and 00:03.0) both of
You mean the i3100 here, right?

> them having a register 0x3E. If you set
> ISAEN on 00:02.00 you have to set ISAEN on 00:03.00 as well. This is a
> requirement provided by Intel in fact.
> It makes sense as the address decoding is different as soon ISAEN is
> set. All th bridges should be set correctly.
> These two peripherals can be coupled together providing x8 lanes.
> Note that ISAEN is not set by the legacy BIOS, and the VGA output is
> working flawlessly. So in fact I just want
> to write 0x8 instead 0xb in register 0x3E. But this I can already do,
> just not at the correct place.
So where have you tried?  File and function?

It looks like if that's the bit you want to set you need to have your own
enable_resources function in pciexp_porta.c.  Right now you're using the

> With the GFX card connected to SLOT0, the PCIe is operating in coupled
> mode and actually configured as x8.
> This is because the current coreboot port does not set PEACAPA.SIMP to 1
> in both bridge. As soon both 00:02.0
> and  00:03.0 get PEACAPA.SIMP is set to 1, the two port are configured
> in x4. We can see that in
> PEALNKCAP.MLW. Checking legacy BIOS settings confirm PEACAPA.SIMP should
> be 1 in both PCIe
> ports.
So this should probably be done even earlier.  That's not something that is
fixed, right?  Or do you want it coupled (or not) depending on what card
gets plugged in?

> I guess the only thing left is that coreboot does not allocate a hole
> for the VGA, two holes are required I guess,
> MEM and IO. how can I check if a hole is actually reserved or not?
Look through the last resource tree in the boot log.  It should be there.

You can always add them in read_resources.


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