[coreboot] vga not working
arnaud.maye at 4dsp.com
Thu Aug 20 13:45:17 CEST 2009
ron minnich wrote:
> On Wed, Aug 19, 2009 at 12:27 AM, Arnaud Maye<arnaud.maye at 4dsp.com> wrote:
> OK, there's some things to talk about in here.
>> Well I've made the patch, added a 13100 specific pci_bus_enable_resources in
>> pciexp_porta.c and modified
>> the pcie_ops structure accordingly.
> Can we see the patch?
Well this is not making a lot of sense so far, The VGA is anyway not
working... I will provide a patch as soon I get everything to operate.
>> make clean, make. Any idea what could
>> go wrong here?
> hard to say without seeing code.
>> Actually the code in pci_device.c is setting the correct register in the
>> bridges, just the value is incorrect.
> What's that mean? What is right, and what is "incorrect", and what
> bridges, and what register?
>> It is setting the
>> ISA IO/MEM forwarding bit and we do not want this to happen.
> What? where? why? How? I'm lost again.
BCTRL has VGAEN and ISAEN, coreboot assign both of them to 1. The value
0xb is wrote to register 0x3E.
As you seem to like details, 0xb is 0b1100 which means bit 3 and 2 are
set to 1, which means VGAEEN and
ISAEN are both getting set to 1.
The ep80579 has two x4 lanes peripherals (00:02.0 and 00:03.0) both of
them having a register 0x3E. If you set
ISAEN on 00:02.00 you have to set ISAEN on 00:03.00 as well. This is a
requirement provided by Intel in fact.
It makes sense as the address decoding is different as soon ISAEN is
set. All th bridges should be set correctly.
These two peripherals can be coupled together providing x8 lanes.
Note that ISAEN is not set by the legacy BIOS, and the VGA output is
working flawlessly. So in fact I just want
to write 0x8 instead 0xb in register 0x3E. But this I can already do,
just not at the correct place.
> I confess to not knowing much about this part ... so am not sure
> what's happened here.
The description of the VGAEN bit is :
VGA Enable : Controls the routing of processor initiated transactions
targeting VGA compatible I/O and memory
address ranges. Actually access to these ranges forward to the PCIe port
instead the NSI ( North-South Interface ).
The PCIe port I am using is directly connected to a slot, there are no
other bridge or switch in the way. So in this
respect the correct bit is set in the bridge.
I have checked the base address of the various memory mapped register in
the ep80579 and none of them are
pointing a location conflicting with VGA memory ranges.
With the GFX card connected to SLOT0, the PCIe is operating in coupled
mode and actually configured as x8.
This is because the current coreboot port does not set PEACAPA.SIMP to 1
in both bridge. As soon both 00:02.0
and 00:03.0 get PEACAPA.SIMP is set to 1, the two port are configured
in x4. We can see that in
PEALNKCAP.MLW. Checking legacy BIOS settings confirm PEACAPA.SIMP should
be 1 in both PCIe
I guess the only thing left is that coreboot does not allocate a hole
for the VGA, two holes are required I guess,
MEM and IO. how can I check if a hole is actually reserved or not?
Any clue Ron, Myles or Kevin?
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