[coreboot] vga not working

[Arnaud Maye]

Hello Guys,

I've got the VGA to operating correctly in seabios. Actually it was as 
simple as enabling the VGA
forwarding on the pci root complex, in the northbridge. Actually during 
the coreboot boot, the VGA
output does not make much sense but as soon the OS boots, I can see the 
complete boot.

This bit can be set for one PCIe "port" or the other, actually two 
possible settings but both cannot
be enabled in the same time. So the bit to set depends where the GFX 
card is attached in fact.
Should we proceed with this "detection" to set the correct bit or can we 
assume the user connects
his card to PCIe SLOT0, in this case we hard code the correct bit 
setting for PCIe SLOT0?

So far I am doing this in the auto.c file after the RAM verification, 
and this is not the best place to do
that, I know. Where would be the best place to patch that in? In a  way 
we are only setting one bit nothing
more.

Thank you!

Arnaud


Kevin O'Connor wrote:
> On Thu, Jul 30, 2009 at 09:56:20AM -0600, Myles Watson wrote:
>   
>> On Wed, Jul 29, 2009 at 2:31 AM, Arnaud Maye <arnaud.maye at 4dsp.com> wrote:
>>     
>>> We are talking about the GFX cards legacy ranges, right? I think
>>> Myles looked at the PCI allocation already it seems everything is
>>> fine there.
>>>       
>> Actually I said that it wouldn't be related to the allocator because the
>> legacy VGA ranges are not aren't allocated there.  This is the place to
>> start to look for that:
>>     
> [...]
>   
>> 1. Make sure that that's the path to your graphics card.
>> 2. Make sure that the correct bits get set in each device so that the I/O to
>> the graphics card gets there.
>>   - The PCI_BRIDGE_CTL_VGA bit is in the device structure, so it doesn't
>> affect hardware
>>   - Many bridges need some bit set to decode those ranges
>>     
>
> In addition to making sure the legacy IO ranges are correct, you also
> need to verify the legacy vga memory range (0xa0000 - 0xc0000) is
> properly configured in the bridges.  Also, the chipset needs to have
> this range be a pci hole - it must not have memory mapped there.
>
> -Kevin
>
>   

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