[coreboot] [v2] r4534 - in trunk/coreboot-v2: . documentation src src/arch/i386 src/arch/i386/boot src/arch/i386/init src/arch/i386/lib src/arch/i386/smp src/arch/ppc src/boot src/console src/cpu src/cpu/amd src/cpu/amd/socket_F src/cpu/emulation src/cpu/emulation/qemu-x86 src/cpu/intel src/cpu/intel/hyperthreading src/cpu/intel/microcode src/cpu/intel/model_69x src/cpu/intel/model_6dx src/cpu/intel/model_6ex src/cpu/intel/model_6fx src/cpu/intel/model_6xx src/cpu/intel/socket_PGA370 src/cpu/intel/socket_mFCPGA478 src/cpu/intel/speedstep src/cpu/ppc src/cpu/simple_init src/cpu/via src/cpu/via/model_c7 src/cpu/x86 src/cpu/x86/cache src/cpu/x86/fpu src/cpu/x86/lapic src/cpu/x86/mmx src/cpu/x86/mtrr src/cpu/x86/smm src/cpu/x86/sse src/cpu/x86/tsc src/devices src/drivers src/drivers/pci src/drivers/pci/onboard src/lib src/mainboard src/mainboard/a-trend src/mainboard/a-trend/atc-6220 src/mainboard/a-trend/atc-6240 src/mainboard/abit src/mainboard/abit/be6-ii_v2_0 src/mainboard/advantech src/mainboard/advantech/pcm-5820 src/mainboard/amd src/mainboard/amd/db800 src/mainboard/amd/dbm690t src/mainboard/amd/norwich src/mainboard/amd/pistachio src/mainboard/amd/rumba src/mainboard/amd/serengeti_cheetah src/mainboard/amd/serengeti_cheetah_fam10 src/mainboard/arima src/mainboard/arima/hdama src/mainboard/artecgroup src/mainboard/artecgroup/dbe61 src/mainboard/asi src/mainboard/asi/mb_5blgp src/mainboard/asi/mb_5blmp src/mainboard/asus src/mainboard/asus/a8n_e src/mainboard/asus/a8v-e_se src/mainboard/asus/m2v-mx_se src/mainboard/asus/mew-am src/mainboard/asus/mew-vm src/mainboard/asus/p2b src/mainboard/asus/p2b-d src/mainboard/asus/p2b-ds src/mainboard/asus/p2b-f src/mainboard/asus/p3b-f src/mainboard/axus src/mainboard/axus/tc320 src/mainboard/azza src/mainboard/azza/pt-6ibd src/mainboard/bcom src/mainboard/bcom/winnet100 src/mainboard/bcom/winnetp680 src/mainboard/biostar src/mainboard/biostar/m6tba src/mainboard/broadcom src/mainboard/broadcom/blast src/mainboard/compaq src/mainboard/compaq/deskpro_en_sff_p600 src/mainboard/dell src/mainboard/dell/s1850 src/mainboard/digitallogic src/mainboard/digitallogic/adl855pc src/mainboard/digitallogic/msm586seg src/mainboard/digitallogic/msm800sev src/mainboard/eaglelion src/mainboard/eaglelion/5bcm src/mainboard/embeddedplanet src/mainboard/embeddedplanet/ep405pc src/mainboard/emulation src/mainboard/emulation/qemu-x86 src/mainboard/gigabyte src/mainboard/gigabyte/ga-6bxc src/mainboard/gigabyte/ga_2761gxdk src/mainboard/gigabyte/m57sli src/mainboard/hp src/mainboard/hp/dl145_g3 src/mainboard/ibm src/mainboard/ibm/e325 src/mainboard/ibm/e326 src/mainboard/iei src/mainboard/iei/juki-511p src/mainboard/iei/nova4899r src/mainboard/iei/pcisa-lx-800-r10 src/mainboard/intel src/mainboard/intel/jarrell src/mainboard/intel/mtarvon src/mainboard/intel/truxton src/mainboard/intel/xe7501devkit src/mainboard/iwill src/mainboard/iwill/dk8_htx src/mainboard/iwill/dk8s2 src/mainboard/iwill/dk8x src/mainboard/jetway src/mainboard/jetway/j7f24 src/mainboard/kontron src/mainboard/kontron/986lcd-m src/mainboard/lippert src/mainboard/lippert/frontrunner src/mainboard/lippert/roadrunner-lx src/mainboard/lippert/spacerunner-lx src/mainboard/mitac src/mainboard/motorola src/mainboard/motorola/sandpoint src/mainboard/motorola/sandpointx3_altimus_mpc7410 src/mainboard/msi src/mainboard/msi/ms6119 src/mainboard/msi/ms6147 src/mainboard/msi/ms6178 src/mainboard/msi/ms7135 src/mainboard/msi/ms7260 src/mainboard/msi/ms9185 src/mainboard/msi/ms9282 src/mainboard/nec src/mainboard/nec/powermate2000 src/mainboard/newisys src/mainboard/newisys/khepri src/mainboard/nvidia src/mainboard/nvidia/l1_2pvv src/mainboard/olpc src/mainboard/olpc/btest src/mainboard/olpc/rev_a src/mainboard/pcengines src/mainboard/pcengines/alix1c src/mainboard/rca src/mainboard/rca/rm4100 src/mainboard/soyo src/mainboard/sunw src/mainboard/sunw/ultra40 src/mainboard/supermicro src/mainboard/supermicro/h8dme src/mainboard/supermicro/h8dmr src/mainboard/supermicro/x6dai_g src/mainboard/supermicro/x6dhe_g src/mainboard/supermicro/x6dhe_g2 src/mainboard/supermicro/x6dhr_ig src/mainboard/supermicro/x6dhr_ig2 src/mainboard/technexion src/mainboard/technexion/tim8690 src/mainboard/technologic src/mainboard/technologic/ts5300 src/mainboard/televideo src/mainboard/televideo/tc7020 src/mainboard/thomson src/mainboard/thomson/ip1000 src/mainboard/totalimpact src/mainboard/totalimpact/briq src/mainboard/tyan src/mainboard/tyan/s1846 src/mainboard/tyan/s2735 src/mainboard/tyan/s2850 src/mainboard/tyan/s2875 src/mainboard/tyan/s2880 src/mainboard/tyan/s2881 src/mainboard/tyan/s2882 src/mainboard/tyan/s2885 src/mainboard/tyan/s2891 src/mainboard/tyan/s2892 src/mainboard/tyan/s2895 src/mainboard/tyan/s2912 src/mainboard/tyan/s2912_fam10 src/mainboard/tyan/s4880 src/mainboard/tyan/s4882 src/mainboard/via src/mainboard/via/epia src/mainboard/via/epia-cn src/mainboard/via/epia-m src/mainboard/via/epia-m700 src/mainboard/via/pc2500e src/mainboard/via/vt8454c src/northbridge src/northbridge/amd src/northbridge/amd/amdk8 src/northbridge/amd/amdk8/root_complex src/northbridge/ibm src/northbridge/intel src/northbridge/intel/i82810 src/northbridge/intel/i945 src/northbridge/motorola src/northbridge/via src/northbridge/via/cx700 src/pc80 src/southbridge src/southbridge/amd src/southbridge/amd/amd8111 src/southbridge/broadcom src/southbridge/intel src/southbridge/intel/i82371eb src/southbridge/intel/i82801gx src/southbridge/intel/i82801xx src/southbridge/nvidia src/southbridge/ricoh src/southbridge/sis src/southbridge/via src/southbridge/winbond src/superio src/superio/fintek src/superio/fintek/f71805f src/superio/intel src/superio/intel/i3100 src/superio/ite src/superio/ite/it8661f src/superio/ite/it8671f src/superio/ite/it8673f src/superio/ite/it8705f src/superio/ite/it8712f src/superio/ite/it8716f src/superio/ite/it8718f src/superio/nsc src/superio/nsc/pc8374 src/superio/nsc/pc87309 src/superio/nsc/pc87351 src/superio/nsc/pc87360 src/superio/nsc/pc87366 src/superio/nsc/pc87417 src/superio/nsc/pc87427 src/superio/nsc/pc97307 src/superio/nsc/pc97317 src/superio/serverengines src/superio/smsc src/superio/smsc/fdc37m60x src/superio/smsc/lpc47b272 src/superio/smsc/lpc47b397 src/superio/smsc/lpc47m10x src/superio/smsc/lpc47n217 src/superio/smsc/smscsuperio src/superio/via src/superio/via/vt1211 src/superio/winbond src/superio/winbond/w83627dhg src/superio/winbond/w83627ehg src/superio/winbond/w83627hf src/superio/winbond/w83627thf src/superio/winbond/w83627thg src/superio/winbond/w83627uhg src/superio/winbond/w83697hf src/superio/winbond/w83977f src/superio/winbond/w83977tf targets/kontron/986lcd-m util util/abuild util/cbfstool util/cbfstool/tools util/cbfstool/tools/lzma util/kconfig util/kconfig/lxdialog util/sconfig util/x86emu util/x86emu/pcbios util/x86emu/x86emu util/xcompile

svn at coreboot.org svn at coreboot.org
Wed Aug 12 17:00:51 CEST 2009


Author: rminnich
Date: 2009-08-12 17:00:51 +0200 (Wed, 12 Aug 2009)
New Revision: 4534

Added:
   trunk/coreboot-v2/Makefile
   trunk/coreboot-v2/documentation/Kconfig.tex
   trunk/coreboot-v2/src/Kconfig
   trunk/coreboot-v2/src/arch/i386/Kconfig
   trunk/coreboot-v2/src/arch/i386/Makefile.inc
   trunk/coreboot-v2/src/arch/i386/boot/Makefile.inc
   trunk/coreboot-v2/src/arch/i386/init/Makefile.inc
   trunk/coreboot-v2/src/arch/i386/lib/Makefile.inc
   trunk/coreboot-v2/src/arch/i386/smp/Makefile.inc
   trunk/coreboot-v2/src/arch/ppc/Kconfig
   trunk/coreboot-v2/src/boot/Makefile.inc
   trunk/coreboot-v2/src/console/Kconfig
   trunk/coreboot-v2/src/console/Makefile.inc
   trunk/coreboot-v2/src/cpu/Kconfig
   trunk/coreboot-v2/src/cpu/Makefile.inc
   trunk/coreboot-v2/src/cpu/amd/Kconfig
   trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig
   trunk/coreboot-v2/src/cpu/emulation/Kconfig
   trunk/coreboot-v2/src/cpu/emulation/Makefile.inc
   trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Kconfig
   trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Makefile.inc
   trunk/coreboot-v2/src/cpu/intel/Kconfig
   trunk/coreboot-v2/src/cpu/intel/Makefile.inc
   trunk/coreboot-v2/src/cpu/intel/hyperthreading/Makefile.inc
   trunk/coreboot-v2/src/cpu/intel/microcode/Makefile.inc
   trunk/coreboot-v2/src/cpu/intel/model_69x/Makefile.inc
   trunk/coreboot-v2/src/cpu/intel/model_6dx/Makefile.inc
   trunk/coreboot-v2/src/cpu/intel/model_6ex/Kconfig
   trunk/coreboot-v2/src/cpu/intel/model_6ex/Makefile.inc
   trunk/coreboot-v2/src/cpu/intel/model_6fx/Kconfig
   trunk/coreboot-v2/src/cpu/intel/model_6fx/Makefile.inc
   trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc
   trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig
   trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Makefile.inc
   trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Kconfig
   trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Makefile.inc
   trunk/coreboot-v2/src/cpu/intel/speedstep/Makefile.inc
   trunk/coreboot-v2/src/cpu/ppc/Kconfig
   trunk/coreboot-v2/src/cpu/ppc/Makefile.inc
   trunk/coreboot-v2/src/cpu/simple_init/Makefile.inc
   trunk/coreboot-v2/src/cpu/via/Kconfig
   trunk/coreboot-v2/src/cpu/via/Makefile.inc
   trunk/coreboot-v2/src/cpu/via/model_c7/Kconfig
   trunk/coreboot-v2/src/cpu/via/model_c7/Makefile.inc
   trunk/coreboot-v2/src/cpu/x86/Kconfig
   trunk/coreboot-v2/src/cpu/x86/cache/Makefile.inc
   trunk/coreboot-v2/src/cpu/x86/fpu/Makefile.inc
   trunk/coreboot-v2/src/cpu/x86/lapic/Makefile.inc
   trunk/coreboot-v2/src/cpu/x86/mmx/Makefile.inc
   trunk/coreboot-v2/src/cpu/x86/mtrr/Makefile.inc
   trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc
   trunk/coreboot-v2/src/cpu/x86/sse/Makefile.inc
   trunk/coreboot-v2/src/cpu/x86/tsc/Makefile.inc
   trunk/coreboot-v2/src/devices/Kconfig
   trunk/coreboot-v2/src/devices/Makefile.inc
   trunk/coreboot-v2/src/drivers/Makefile.inc
   trunk/coreboot-v2/src/drivers/pci/Makefile.inc
   trunk/coreboot-v2/src/drivers/pci/onboard/Makefile.inc
   trunk/coreboot-v2/src/lib/Makefile.inc
   trunk/coreboot-v2/src/mainboard/Kconfig
   trunk/coreboot-v2/src/mainboard/a-trend/Kconfig
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/devicetree.cb
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/devicetree.cb
   trunk/coreboot-v2/src/mainboard/abit/Kconfig
   trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/devicetree.cb
   trunk/coreboot-v2/src/mainboard/advantech/Kconfig
   trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/devicetree.cb
   trunk/coreboot-v2/src/mainboard/amd/Kconfig
   trunk/coreboot-v2/src/mainboard/amd/db800/devicetree.cb
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb
   trunk/coreboot-v2/src/mainboard/amd/norwich/devicetree.cb
   trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb
   trunk/coreboot-v2/src/mainboard/amd/rumba/devicetree.cb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Makefile.inc
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/devicetree.cb
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
   trunk/coreboot-v2/src/mainboard/arima/Kconfig
   trunk/coreboot-v2/src/mainboard/arima/hdama/devicetree.cb
   trunk/coreboot-v2/src/mainboard/artecgroup/Kconfig
   trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/devicetree.cb
   trunk/coreboot-v2/src/mainboard/asi/Kconfig
   trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/devicetree.cb
   trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/devicetree.cb
   trunk/coreboot-v2/src/mainboard/asus/Kconfig
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/devicetree.cb
   trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/devicetree.cb
   trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/devicetree.cb
   trunk/coreboot-v2/src/mainboard/asus/mew-am/devicetree.cb
   trunk/coreboot-v2/src/mainboard/asus/mew-vm/devicetree.cb
   trunk/coreboot-v2/src/mainboard/asus/p2b-d/devicetree.cb
   trunk/coreboot-v2/src/mainboard/asus/p2b-ds/devicetree.cb
   trunk/coreboot-v2/src/mainboard/asus/p2b-f/devicetree.cb
   trunk/coreboot-v2/src/mainboard/asus/p2b/devicetree.cb
   trunk/coreboot-v2/src/mainboard/asus/p3b-f/devicetree.cb
   trunk/coreboot-v2/src/mainboard/axus/Kconfig
   trunk/coreboot-v2/src/mainboard/axus/tc320/devicetree.cb
   trunk/coreboot-v2/src/mainboard/azza/Kconfig
   trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/devicetree.cb
   trunk/coreboot-v2/src/mainboard/bcom/Kconfig
   trunk/coreboot-v2/src/mainboard/bcom/winnet100/devicetree.cb
   trunk/coreboot-v2/src/mainboard/bcom/winnetp680/devicetree.cb
   trunk/coreboot-v2/src/mainboard/biostar/Kconfig
   trunk/coreboot-v2/src/mainboard/biostar/m6tba/devicetree.cb
   trunk/coreboot-v2/src/mainboard/broadcom/Kconfig
   trunk/coreboot-v2/src/mainboard/broadcom/blast/devicetree.cb
   trunk/coreboot-v2/src/mainboard/compaq/Kconfig
   trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb
   trunk/coreboot-v2/src/mainboard/dell/Kconfig
   trunk/coreboot-v2/src/mainboard/dell/s1850/devicetree.cb
   trunk/coreboot-v2/src/mainboard/digitallogic/Kconfig
   trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/devicetree.cb
   trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/devicetree.cb
   trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/devicetree.cb
   trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/devicetree.cb
   trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig
   trunk/coreboot-v2/src/mainboard/embeddedplanet/Kconfig
   trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/devicetree.cb
   trunk/coreboot-v2/src/mainboard/emulation/Kconfig
   trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Makefile.inc
   trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/devicetree.cb
   trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig
   trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/devicetree.cb
   trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb
   trunk/coreboot-v2/src/mainboard/hp/Kconfig
   trunk/coreboot-v2/src/mainboard/hp/dl145_g3/devicetree.cb
   trunk/coreboot-v2/src/mainboard/ibm/Kconfig
   trunk/coreboot-v2/src/mainboard/ibm/e325/devicetree.cb
   trunk/coreboot-v2/src/mainboard/ibm/e326/devicetree.cb
   trunk/coreboot-v2/src/mainboard/iei/Kconfig
   trunk/coreboot-v2/src/mainboard/iei/juki-511p/devicetree.cb
   trunk/coreboot-v2/src/mainboard/iei/nova4899r/devicetree.cb
   trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
   trunk/coreboot-v2/src/mainboard/intel/Kconfig
   trunk/coreboot-v2/src/mainboard/intel/jarrell/devicetree.cb
   trunk/coreboot-v2/src/mainboard/intel/mtarvon/devicetree.cb
   trunk/coreboot-v2/src/mainboard/intel/truxton/devicetree.cb
   trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/devicetree.cb
   trunk/coreboot-v2/src/mainboard/iwill/Kconfig
   trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/devicetree.cb
   trunk/coreboot-v2/src/mainboard/iwill/dk8s2/devicetree.cb
   trunk/coreboot-v2/src/mainboard/iwill/dk8x/devicetree.cb
   trunk/coreboot-v2/src/mainboard/jetway/Kconfig
   trunk/coreboot-v2/src/mainboard/jetway/j7f24/devicetree.cb
   trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Makefile.inc
   trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/devicetree.cb
   trunk/coreboot-v2/src/mainboard/kontron/Kconfig
   trunk/coreboot-v2/src/mainboard/lippert/Kconfig
   trunk/coreboot-v2/src/mainboard/lippert/frontrunner/devicetree.cb
   trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/devicetree.cb
   trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/devicetree.cb
   trunk/coreboot-v2/src/mainboard/mitac/Kconfig
   trunk/coreboot-v2/src/mainboard/motorola/Kconfig
   trunk/coreboot-v2/src/mainboard/motorola/sandpoint/devicetree.cb
   trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/devicetree.cb
   trunk/coreboot-v2/src/mainboard/msi/Kconfig
   trunk/coreboot-v2/src/mainboard/msi/ms6119/devicetree.cb
   trunk/coreboot-v2/src/mainboard/msi/ms6147/devicetree.cb
   trunk/coreboot-v2/src/mainboard/msi/ms6178/Makefile.inc
   trunk/coreboot-v2/src/mainboard/msi/ms6178/devicetree.cb
   trunk/coreboot-v2/src/mainboard/msi/ms7135/devicetree.cb
   trunk/coreboot-v2/src/mainboard/msi/ms7260/devicetree.cb
   trunk/coreboot-v2/src/mainboard/msi/ms9185/devicetree.cb
   trunk/coreboot-v2/src/mainboard/msi/ms9282/devicetree.cb
   trunk/coreboot-v2/src/mainboard/nec/Kconfig
   trunk/coreboot-v2/src/mainboard/nec/powermate2000/devicetree.cb
   trunk/coreboot-v2/src/mainboard/newisys/Kconfig
   trunk/coreboot-v2/src/mainboard/newisys/khepri/devicetree.cb
   trunk/coreboot-v2/src/mainboard/nvidia/Kconfig
   trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/devicetree.cb
   trunk/coreboot-v2/src/mainboard/olpc/Kconfig
   trunk/coreboot-v2/src/mainboard/olpc/btest/devicetree.cb
   trunk/coreboot-v2/src/mainboard/olpc/rev_a/devicetree.cb
   trunk/coreboot-v2/src/mainboard/pcengines/Kconfig
   trunk/coreboot-v2/src/mainboard/pcengines/alix1c/devicetree.cb
   trunk/coreboot-v2/src/mainboard/rca/Kconfig
   trunk/coreboot-v2/src/mainboard/rca/rm4100/devicetree.cb
   trunk/coreboot-v2/src/mainboard/soyo/Kconfig
   trunk/coreboot-v2/src/mainboard/sunw/Kconfig
   trunk/coreboot-v2/src/mainboard/sunw/ultra40/devicetree.cb
   trunk/coreboot-v2/src/mainboard/supermicro/Kconfig
   trunk/coreboot-v2/src/mainboard/supermicro/h8dme/devicetree.cb
   trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/devicetree.cb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/devicetree.cb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/devicetree.cb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
   trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
   trunk/coreboot-v2/src/mainboard/technexion/Kconfig
   trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb
   trunk/coreboot-v2/src/mainboard/technologic/Kconfig
   trunk/coreboot-v2/src/mainboard/technologic/ts5300/devicetree.cb
   trunk/coreboot-v2/src/mainboard/televideo/Kconfig
   trunk/coreboot-v2/src/mainboard/televideo/tc7020/devicetree.cb
   trunk/coreboot-v2/src/mainboard/thomson/Kconfig
   trunk/coreboot-v2/src/mainboard/thomson/ip1000/devicetree.cb
   trunk/coreboot-v2/src/mainboard/totalimpact/Kconfig
   trunk/coreboot-v2/src/mainboard/totalimpact/briq/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/Kconfig
   trunk/coreboot-v2/src/mainboard/tyan/s1846/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s2735/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s2850/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s2875/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s2880/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s2881/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s2882/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s2885/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s2891/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s2892/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s2895/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s2912/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s4880/devicetree.cb
   trunk/coreboot-v2/src/mainboard/tyan/s4882/devicetree.cb
   trunk/coreboot-v2/src/mainboard/via/Kconfig
   trunk/coreboot-v2/src/mainboard/via/epia-cn/devicetree.cb
   trunk/coreboot-v2/src/mainboard/via/epia-m/devicetree.cb
   trunk/coreboot-v2/src/mainboard/via/epia-m700/devicetree.cb
   trunk/coreboot-v2/src/mainboard/via/epia/devicetree.cb
   trunk/coreboot-v2/src/mainboard/via/pc2500e/devicetree.cb
   trunk/coreboot-v2/src/mainboard/via/vt8454c/Makefile.inc
   trunk/coreboot-v2/src/mainboard/via/vt8454c/devicetree.cb
   trunk/coreboot-v2/src/northbridge/Kconfig
   trunk/coreboot-v2/src/northbridge/Makefile.inc
   trunk/coreboot-v2/src/northbridge/amd/Kconfig
   trunk/coreboot-v2/src/northbridge/amd/Makefile.inc
   trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig
   trunk/coreboot-v2/src/northbridge/amd/amdk8/root_complex/Kconfig
   trunk/coreboot-v2/src/northbridge/ibm/Kconfig
   trunk/coreboot-v2/src/northbridge/ibm/Makefile.inc
   trunk/coreboot-v2/src/northbridge/intel/Kconfig
   trunk/coreboot-v2/src/northbridge/intel/Makefile.inc
   trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig
   trunk/coreboot-v2/src/northbridge/intel/i82810/Makefile.inc
   trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig
   trunk/coreboot-v2/src/northbridge/intel/i945/Makefile.inc
   trunk/coreboot-v2/src/northbridge/motorola/Kconfig
   trunk/coreboot-v2/src/northbridge/motorola/Makefile.inc
   trunk/coreboot-v2/src/northbridge/via/Kconfig
   trunk/coreboot-v2/src/northbridge/via/Makefile.inc
   trunk/coreboot-v2/src/northbridge/via/cx700/Kconfig
   trunk/coreboot-v2/src/northbridge/via/cx700/Makefile.inc
   trunk/coreboot-v2/src/pc80/Makefile.inc
   trunk/coreboot-v2/src/southbridge/Kconfig
   trunk/coreboot-v2/src/southbridge/Makefile.inc
   trunk/coreboot-v2/src/southbridge/amd/Kconfig
   trunk/coreboot-v2/src/southbridge/amd/Makefile.inc
   trunk/coreboot-v2/src/southbridge/amd/amd8111/Kconfig
   trunk/coreboot-v2/src/southbridge/broadcom/Kconfig
   trunk/coreboot-v2/src/southbridge/broadcom/Makefile.inc
   trunk/coreboot-v2/src/southbridge/intel/Kconfig
   trunk/coreboot-v2/src/southbridge/intel/Makefile.inc
   trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig
   trunk/coreboot-v2/src/southbridge/intel/i82371eb/Makefile.inc
   trunk/coreboot-v2/src/southbridge/intel/i82801gx/Kconfig
   trunk/coreboot-v2/src/southbridge/intel/i82801gx/Makefile.inc
   trunk/coreboot-v2/src/southbridge/intel/i82801xx/Kconfig
   trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc
   trunk/coreboot-v2/src/southbridge/nvidia/Kconfig
   trunk/coreboot-v2/src/southbridge/nvidia/Makefile.inc
   trunk/coreboot-v2/src/southbridge/ricoh/Kconfig
   trunk/coreboot-v2/src/southbridge/ricoh/Makefile.inc
   trunk/coreboot-v2/src/southbridge/sis/Kconfig
   trunk/coreboot-v2/src/southbridge/sis/Makefile.inc
   trunk/coreboot-v2/src/southbridge/via/Kconfig
   trunk/coreboot-v2/src/southbridge/via/Makefile.inc
   trunk/coreboot-v2/src/southbridge/winbond/Kconfig
   trunk/coreboot-v2/src/southbridge/winbond/Makefile.inc
   trunk/coreboot-v2/src/superio/Kconfig
   trunk/coreboot-v2/src/superio/Makefile.inc
   trunk/coreboot-v2/src/superio/fintek/Kconfig
   trunk/coreboot-v2/src/superio/fintek/Makefile.inc
   trunk/coreboot-v2/src/superio/fintek/f71805f/Makefile.inc
   trunk/coreboot-v2/src/superio/intel/Kconfig
   trunk/coreboot-v2/src/superio/intel/Makefile.inc
   trunk/coreboot-v2/src/superio/intel/i3100/Makefile.inc
   trunk/coreboot-v2/src/superio/ite/Kconfig
   trunk/coreboot-v2/src/superio/ite/Makefile.inc
   trunk/coreboot-v2/src/superio/ite/it8661f/Makefile.inc
   trunk/coreboot-v2/src/superio/ite/it8671f/Makefile.inc
   trunk/coreboot-v2/src/superio/ite/it8673f/Makefile.inc
   trunk/coreboot-v2/src/superio/ite/it8705f/Makefile.inc
   trunk/coreboot-v2/src/superio/ite/it8712f/Makefile.inc
   trunk/coreboot-v2/src/superio/ite/it8716f/Makefile.inc
   trunk/coreboot-v2/src/superio/ite/it8718f/Makefile.inc
   trunk/coreboot-v2/src/superio/nsc/Kconfig
   trunk/coreboot-v2/src/superio/nsc/Makefile.inc
   trunk/coreboot-v2/src/superio/nsc/pc8374/Makefile.inc
   trunk/coreboot-v2/src/superio/nsc/pc87309/Makefile.inc
   trunk/coreboot-v2/src/superio/nsc/pc87351/Makefile.inc
   trunk/coreboot-v2/src/superio/nsc/pc87360/Makefile.inc
   trunk/coreboot-v2/src/superio/nsc/pc87366/Makefile.inc
   trunk/coreboot-v2/src/superio/nsc/pc87417/Makefile.inc
   trunk/coreboot-v2/src/superio/nsc/pc87427/Makefile.inc
   trunk/coreboot-v2/src/superio/nsc/pc97307/Makefile.inc
   trunk/coreboot-v2/src/superio/nsc/pc97317/Makefile.inc
   trunk/coreboot-v2/src/superio/serverengines/Kconfig
   trunk/coreboot-v2/src/superio/smsc/Kconfig
   trunk/coreboot-v2/src/superio/smsc/Makefile.inc
   trunk/coreboot-v2/src/superio/smsc/fdc37m60x/Makefile.inc
   trunk/coreboot-v2/src/superio/smsc/lpc47b272/Makefile.inc
   trunk/coreboot-v2/src/superio/smsc/lpc47b397/Makefile.inc
   trunk/coreboot-v2/src/superio/smsc/lpc47m10x/Makefile.inc
   trunk/coreboot-v2/src/superio/smsc/lpc47n217/Makefile.inc
   trunk/coreboot-v2/src/superio/smsc/smscsuperio/Makefile.inc
   trunk/coreboot-v2/src/superio/via/Kconfig
   trunk/coreboot-v2/src/superio/via/Makefile.inc
   trunk/coreboot-v2/src/superio/via/vt1211/Makefile.inc
   trunk/coreboot-v2/src/superio/winbond/Kconfig
   trunk/coreboot-v2/src/superio/winbond/Makefile.inc
   trunk/coreboot-v2/src/superio/winbond/w83627dhg/Makefile.inc
   trunk/coreboot-v2/src/superio/winbond/w83627ehg/Makefile.inc
   trunk/coreboot-v2/src/superio/winbond/w83627hf/Makefile.inc
   trunk/coreboot-v2/src/superio/winbond/w83627thf/Makefile.inc
   trunk/coreboot-v2/src/superio/winbond/w83627thg/Makefile.inc
   trunk/coreboot-v2/src/superio/winbond/w83627uhg/Makefile.inc
   trunk/coreboot-v2/src/superio/winbond/w83697hf/Makefile.inc
   trunk/coreboot-v2/src/superio/winbond/w83977f/Makefile.inc
   trunk/coreboot-v2/src/superio/winbond/w83977tf/Makefile.inc
   trunk/coreboot-v2/util/cbfstool/Makefile.inc
   trunk/coreboot-v2/util/cbfstool/tools/Makefile.inc
   trunk/coreboot-v2/util/cbfstool/tools/lzma/Makefile.inc
   trunk/coreboot-v2/util/kconfig/
   trunk/coreboot-v2/util/kconfig/Makefile
   trunk/coreboot-v2/util/kconfig/POTFILES.in
   trunk/coreboot-v2/util/kconfig/check.sh
   trunk/coreboot-v2/util/kconfig/conf.c
   trunk/coreboot-v2/util/kconfig/confdata.c
   trunk/coreboot-v2/util/kconfig/expr.c
   trunk/coreboot-v2/util/kconfig/expr.h
   trunk/coreboot-v2/util/kconfig/gconf.c
   trunk/coreboot-v2/util/kconfig/gconf.glade
   trunk/coreboot-v2/util/kconfig/images.c
   trunk/coreboot-v2/util/kconfig/kconfig_load.c
   trunk/coreboot-v2/util/kconfig/kxgettext.c
   trunk/coreboot-v2/util/kconfig/lex.zconf.c_shipped
   trunk/coreboot-v2/util/kconfig/lkc.h
   trunk/coreboot-v2/util/kconfig/lkc_proto.h
   trunk/coreboot-v2/util/kconfig/lxdialog/
   trunk/coreboot-v2/util/kconfig/lxdialog/BIG.FAT.WARNING
   trunk/coreboot-v2/util/kconfig/lxdialog/check-lxdialog.sh
   trunk/coreboot-v2/util/kconfig/lxdialog/checklist.c
   trunk/coreboot-v2/util/kconfig/lxdialog/dialog.h
   trunk/coreboot-v2/util/kconfig/lxdialog/inputbox.c
   trunk/coreboot-v2/util/kconfig/lxdialog/menubox.c
   trunk/coreboot-v2/util/kconfig/lxdialog/textbox.c
   trunk/coreboot-v2/util/kconfig/lxdialog/util.c
   trunk/coreboot-v2/util/kconfig/lxdialog/yesno.c
   trunk/coreboot-v2/util/kconfig/mconf.c
   trunk/coreboot-v2/util/kconfig/menu.c
   trunk/coreboot-v2/util/kconfig/qconf.cc
   trunk/coreboot-v2/util/kconfig/qconf.h
   trunk/coreboot-v2/util/kconfig/symbol.c
   trunk/coreboot-v2/util/kconfig/util.c
   trunk/coreboot-v2/util/kconfig/zconf.gperf
   trunk/coreboot-v2/util/kconfig/zconf.hash.c_shipped
   trunk/coreboot-v2/util/kconfig/zconf.l
   trunk/coreboot-v2/util/kconfig/zconf.tab.c_shipped
   trunk/coreboot-v2/util/kconfig/zconf.y
   trunk/coreboot-v2/util/sconfig/
   trunk/coreboot-v2/util/sconfig/LICENSE
   trunk/coreboot-v2/util/sconfig/Makefile
   trunk/coreboot-v2/util/sconfig/NOTES
   trunk/coreboot-v2/util/sconfig/config.g
   trunk/coreboot-v2/util/sconfig/parsedesc.g
   trunk/coreboot-v2/util/sconfig/test.config
   trunk/coreboot-v2/util/sconfig/yapps2.py
   trunk/coreboot-v2/util/sconfig/yapps2.tex
   trunk/coreboot-v2/util/sconfig/yappsrt.py
   trunk/coreboot-v2/util/x86emu/Makefile.inc
   trunk/coreboot-v2/util/x86emu/pcbios/Makefile.inc
   trunk/coreboot-v2/util/x86emu/x86emu/Makefile.inc
   trunk/coreboot-v2/util/xcompile/
   trunk/coreboot-v2/util/xcompile/xcompile
Modified:
   trunk/coreboot-v2/documentation/Makefile
   trunk/coreboot-v2/src/console/console.c
   trunk/coreboot-v2/src/pc80/serial.c
   trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb
   trunk/coreboot-v2/util/abuild/abuild
Log:
Kconfig!
Works on Kontron, qemu, and serengeti. 

Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>

tested on abuild only. 

Acked-by: Ronald G. Minnich <rminnich at gmail.com>




Added: trunk/coreboot-v2/Makefile
===================================================================
--- trunk/coreboot-v2/Makefile	                        (rev 0)
+++ trunk/coreboot-v2/Makefile	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,299 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Advanced Micro Devices, Inc.
+## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following conditions
+## are met:
+## 1. Redistributions of source code must retain the above copyright
+##    notice, this list of conditions and the following disclaimer.
+## 2. Redistributions in binary form must reproduce the above copyright
+##    notice, this list of conditions and the following disclaimer in the
+##    documentation and/or other materials provided with the distribution.
+## 3. The name of the author may not be used to endorse or promote products
+##    derived from this software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+## ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+## SUCH DAMAGE.
+##
+
+$(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile > .xcompile)))
+include .xcompile
+
+export top := $(shell pwd)
+export src := $(top)/src
+export srck := $(top)/util/kconfig
+export obj := $(top)/build
+export objk := $(top)/build/util/kconfig
+export sconfig := $(top)/util/sconfig
+export yapps2_py := $(sconfig)/yapps2.py
+export config_g := $(sconfig)/config.g
+
+
+export KERNELVERSION      := 2.3
+export KCONFIG_AUTOHEADER := $(obj)/config.h
+export KCONFIG_AUTOCONFIG := $(obj)/auto.conf
+export COREBOOT_V2	:= 1
+
+CONFIG_SHELL := sh
+KBUILD_DEFCONFIG := configs/defconfig
+UNAME_RELEASE := $(shell uname -r)
+HAVE_DOTCONFIG := $(wildcard .config)
+MAKEFLAGS += -rR --no-print-directory
+
+# Make is silent per default, but 'make V=1' will show all compiler calls.
+ifneq ($(V),1)
+Q := @
+endif
+
+CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E
+HOSTCC = gcc
+HOSTCXX = g++
+HOSTCFLAGS := -I$(srck) -I$(objk) -g
+HOSTCXXFLAGS := -I$(srck) -I$(objk)
+
+DESTDIR = /opt
+
+DOXYGEN := doxygen
+DOXYGEN_OUTPUT_DIR := doxygen
+
+ifeq ($(strip $(HAVE_DOTCONFIG)),)
+
+all: config
+
+else
+
+include $(top)/.config
+
+ARCHDIR-$(CONFIG_ARCH_X86)    := i386
+ARCHDIR-$(CONFIG_ARCH_POWERPC) := ppc
+
+MAINBOARDDIR=$(shell echo $(CONFIG_MAINBOARD_DIR))
+export MAINBOARDDIR
+
+PLATFORM-y += src/arch/$(ARCHDIR-y) src/cpu src/mainboard/$(MAINBOARDDIR)
+TARGETS-y :=
+
+BUILD-y := src/lib src/boot src/console src/devices src/southbridge src/northbridge src/superio src/drivers util/x86emu
+BUILD-y += util/cbfstool
+BUILD-$(CONFIG_ARCH_X86) += src/pc80
+
+# The primary target needs to be here before we include the
+# other files
+
+all: coreboot
+
+
+#######################################################################
+# Build the tools
+
+CBFSTOOL:=$(obj)/util/cbfstool/cbfstool
+
+$(obj)/mainboard/$(MAINBOARDDIR)/config.py: $(yapps2_py) $(config_g) 
+	$(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
+	$(Q)python $(yapps2_py) $(config_g) $(obj)/mainboard/$(MAINBOARDDIR)/config.py
+
+
+# needed objects that every mainboard uses 
+# Creation of these is architecture and mainboard independent
+$(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/Config.lb  $(obj)/mainboard/$(MAINBOARDDIR)/config.py
+	$(Q)mkdir -p $(obj)/mainboard/$(MAINBOARDDIR)
+	(cd $(obj)/mainboard/$(MAINBOARDDIR) ; PYTHONPATH=$(top)/util/sconfig export PYTHONPATH; python config.py  $(MAINBOARDDIR) $(top) $(obj)/mainboard/$(MAINBOARDDIR))
+
+$(obj)/mainboard/$(MAINBOARDDIR)/static.o: $(obj)/mainboard/$(MAINBOARDDIR)/static.c
+#
+
+objs:=$(obj)/mainboard/$(MAINBOARDDIR)/static.o
+initobjs:=
+drivers:=
+smmobjs:=
+crt0s:=
+ldscripts:=
+types:=obj initobj driver smmobj
+src_types:=crt0 ldscript
+includemakefiles=$(foreach type,$(2), $(eval $(type)-y:=)) $(eval subdirs-y:=) $(eval include $(1)) $(if $(strip $(3)),$(foreach type,$(2),$(eval $(type)s+=$$(patsubst src/%,$(obj)/%,$$(addprefix $(dir $(1)),$$($(type)-y)))))) $(eval subdirs+=$$(subst $(PWD)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))
+evaluate_subdirs=$(eval cursubdirs:=$(subdirs)) $(eval subdirs:=) $(foreach dir,$(cursubdirs),$(eval $(call includemakefiles,$(dir)/Makefile.inc,$(types) $(src_types),$(1)))) $(if $(subdirs),$(eval $(call evaluate_subdirs, $(1))))
+
+# collect all object files eligible for building
+subdirs:=$(PLATFORM-y) $(BUILD-y)
+$(eval $(call evaluate_subdirs, modify))
+
+allobjs:=$(foreach var, $(addsuffix s,$(types)), $($(var)))
+alldirs:=$(sort $(abspath $(dir $(allobjs))))
+source_with_ext=$(patsubst $(obj)/%.o,src/%.$(1),$(allobjs))
+allsrc=$(wildcard $(call source_with_ext,c) $(call source_with_ext,S))
+
+POST_EVALUATION:=y
+
+# fetch rules (protected in POST_EVALUATION) that rely on the variables filled above
+subdirs:=$(PLATFORM-y) $(BUILD-y)
+$(eval $(call evaluate_subdirs))
+
+
+define objs_c_template
+$(obj)/$(1)%.o: src/$(1)%.c
+	$(Q)printf "    CC         $$(subst $$(shell pwd)/,,$$(@))\n"
+	$(Q)$(CC) -m32 $$(CFLAGS) -c -o $$@ $$<
+endef
+
+define objs_S_template
+$(obj)/$(1)%.o: src/$(1)%.S
+	$(Q)printf "    CC         $$(subst $$(shell pwd)/,,$$(@))\n"
+	$(Q)$(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$<
+endef
+
+define initobjs_c_template
+$(obj)/$(1)%.o: src/$(1)%.c
+	$(Q)printf "    CC         $$(subst $$(shell pwd)/,,$$(@))\n"
+	$(Q)$(CC) -m32 $$(CFLAGS) -c -o $$@ $$<
+endef
+
+define initobjs_S_template
+$(obj)/$(1)%.o: src/$(1)%.S
+	$(Q)printf "    CC         $$(subst $$(shell pwd)/,,$$(@))\n"
+	$(Q)$(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$<
+endef
+
+define drivers_c_template
+$(obj)/$(1)%.o: src/$(1)%.c
+	$(Q)printf "    CC         $$(subst $$(shell pwd)/,,$$(@))\n"
+	$(Q)$(CC) -m32 $$(CFLAGS) -c -o $$@ $$<
+endef
+
+define drivers_S_template
+$(obj)/$(1)%.o: src/$(1)%.S
+	$(Q)printf "    CC         $$(subst $$(shell pwd)/,,$$(@))\n"
+	$(Q)$(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$<
+endef
+
+define smmobjs_c_template
+$(obj)/$(1)%.o: src/$(1)%.c
+	$(Q)printf "    CC         $$(subst $$(shell pwd)/,,$$(@))\n"
+	$(Q)$(CC) -m32 $$(CFLAGS) -c -o $$@ $$<
+endef
+
+define smmobjs_S_template
+$(obj)/$(1)%.o: src/$(1)%.S
+	$(Q)printf "    CC         $$(subst $$(shell pwd)/,,$$(@))\n"
+	$(Q)$(CC) -m32 $$(CFLAGS) -c -o $$@ $$<
+endef
+
+usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d)))))
+usetemplate=$(foreach d,$(sort $(dir $($(1)))),$(eval $(call $(1)_$(2)_template,$(subst $(obj)/,,$(d)))))
+$(eval $(call usetemplate,objs,c))
+$(eval $(call usetemplate,objs,S))
+$(eval $(call usetemplate,initobjs,c))
+$(eval $(call usetemplate,initobjs,S))
+$(eval $(call usetemplate,drivers,c))
+$(eval $(call usetemplate,drivers,S))
+$(eval $(call usetemplate,smmobjs,c))
+$(eval $(call usetemplate,smmobjs,S))
+
+printall:
+	@echo objs:=$(objs)
+	@echo initobjs:=$(initobjs)
+	@echo drivers:=$(drivers)
+	@echo smmobjs:=$(smmobjs)
+	@echo alldirs:=$(alldirs)
+	@echo allsrc=$(allsrc)
+
+OBJS     := $(patsubst %,$(obj)/%,$(TARGETS-y))
+INCLUDES := -I$(top)/src -I$(top)/src/include -I$(obj) -I$(top)/src/arch/$(ARCHDIR-y)/include 
+INCLUDES += -I$(shell $(CC) -print-search-dirs | head -n 1 | cut -d' ' -f2)include
+INCLUDES += -include $(obj)/build.h
+
+try-run= $(shell set -e; \
+TMP=".$$$$.tmp"; \
+if ($(1)) > /dev/null 2>&1; \
+then echo "$(2)"; \
+else echo "$(3)"; \
+fi; rm -rf "$$TMP")
+
+cc-option= $(call try-run,\
+$(CC) $(1) -S -xc /dev/null -o "$$TMP", $(1), $(2))
+
+STACKPROTECT += $(call cc-option, -fno-stack-protector,)
+
+CFLAGS = $(STACKPROTECT) $(INCLUDES) $(MAINBOARD_OPTIONS) -Os -nostdinc
+CFLAGS += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
+CFLAGS +=-Wwrite-strings -Wredundant-decls -Wno-trigraphs 
+CFLAGS += -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow 
+CFLAGS += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
+
+CBFS_COMPRESS_FLAG:=
+ifeq "$(CONFIG_COMPRESSED_PAYLOAD_LZMA)" "1"
+CBFS_COMPRESS_FLAG:=l
+endif
+
+coreboot: prepare prepare2 $(obj)/coreboot.rom
+
+endif
+
+prepare:
+	$(Q)mkdir -p $(obj)
+	$(Q)mkdir -p $(obj)/util/kconfig/lxdialog
+	$(Q)test -n "$(alldirs)" && mkdir -p $(alldirs) || true
+
+prepare2:
+	$(Q)printf "    GEN        $(subst $(shell pwd)/,,$(obj)/build.h)\n"
+	$(Q)printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" > $(obj)/build.h
+	$(Q)printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.h
+	$(Q)printf "#define COREBOOT_V2 \"$(COREBOOT_V2)\"\n" >> $(obj)/build.h
+	$(Q)printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.h
+	$(Q)printf "\n" >> $(obj)/build.h
+	$(Q)printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.h
+	$(Q)printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.h
+	$(Q)printf "#define COREBOOT_LINKER \"$(shell LANG= $(LD) --version | head -n1)\"\n" >> $(obj)/build.h
+	$(Q)printf "#define COREBOOT_COMPILE_TIME \"`LANG= date +%T`\"\n" >> $(obj)/build.h
+	$(Q)printf "#define COREBOOT_COMPILE_BY \"$(shell PATH=$$PATH:/usr/ucb whoami)\"\n" >> $(obj)/build.h
+	$(Q)printf "#define COREBOOT_COMPILE_HOST \"$(shell hostname)\"\n" >> $(obj)/build.h
+	$(Q)printf "#define COREBOOT_COMPILE_DOMAIN \"$(shell test `uname -s` = "Linux" && dnsdomainname || domainname)\"\n" >> $(obj)/build.h
+	$(Q)printf "#include \"config.h\"\n" >> $(obj)/build.h
+
+doxy: doxygen
+doxygen:
+	$(Q)$(DOXYGEN) Doxyfile
+
+doxyclean: doxygen-clean
+doxygen-clean:
+	$(Q)rm -rf $(DOXYGEN_OUTPUT_DIR)
+
+clean: doxygen-clean
+	$(Q)rm -f $(allobjs) build/coreboot* .xcompile
+	$(Q)rm -f build/option_table.* build/crt0_includes.h build/ldscript
+	$(Q)rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot
+	$(Q)rm -f $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm
+	$(Q)rmdir -p $(alldirs) 2>/dev/null >/dev/null || true
+
+distclean: clean
+	$(Q)rm -rf build
+	$(Q)rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig*
+
+update:
+	$(Q)dongle.py -c /dev/term/1 build/coreboot.rom EOF
+
+# This include must come _before_ the pattern rules below!
+# Order _does_ matter for pattern rules.
+include util/kconfig/Makefile
+
+$(obj)/ldoptions: $(obj)/config.h
+#	cat $(obj)/config.h  | grep -v \" |grep -v AUTOCONF_INCLUDED | grep \#define | sed s/\#define\ // | sed s/\ /\ =\ / | sed 's/$$/;/' > $(obj)/ldoptions
+	$(Q)awk '/^#define ([^"])* ([^"])*$$/ {print $$2 " = " $$3 ";";}' $< > $@
+
+$(obj)/romcc: $(top)/util/romcc/romcc.c
+	$(Q)printf "  HOSTCC  romcc"
+	$(HOSTCC) -g -O2 -Wall -o $@ $<
+
+.PHONY: $(PHONY) prepare prepare2 clean distclean doxygen doxy coreboot
+

Added: trunk/coreboot-v2/documentation/Kconfig.tex
===================================================================
--- trunk/coreboot-v2/documentation/Kconfig.tex	                        (rev 0)
+++ trunk/coreboot-v2/documentation/Kconfig.tex	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,464 @@
+\documentclass[10pt,letterpaper]{article}
+\usepackage[latin1]{inputenc}
+\usepackage{amsmath}
+\usepackage{amsfonts}
+\usepackage{amssymb}
+\author{Ron Minnich}
+\title{Kconfig usage in coreboot v2}
+\begin{document}
+\section{Introduction}
+This document describes how to use Kconfig in v2. We describe our usage of Kconfig files, Makefile.inc files, when and where to use them, how to use them, and, interestingly, when and where not to use them. 
+\section{Kconfig variations}
+Most Kconfig files set variables, which can be set as part of the Kconfig dialog. Not all Kconfig variables are set by the user, however; some are too dangerous. These are merely enabled by the mainboard. 
+
+For variables set by the user, see src/console/Kconfig. 
+
+For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as ram base. These are highly mainboard dependent. 
+
+Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally. 
+
+\section{Makefile and Makefile.inc}
+There is only one Makefile, at the top level. All other makefiles are included as Makefile.inc. All the next-level Makefile.inc files are selected in the top level Makefile. Directories that are platform-independent are in BUILD-y; platform-dependent (e.g. Makefile.inc's that depend on architecture) are included in PLATFORM-y. 
+
+Make is not recursive. There is only one make process. 
+\subsection{subdir usage}
+Further includes of Makefile.inc, if needed, are done via subdir-y commands. As in Linux, the subdir can be conditional or unconditional. Conditional includes are done via subdir-\$(CONFIG\_VARIABLE) usage; unconditional are done via subdir-y. 
+
+We define the common rules for which variation to use below. 
+\subsection{object file specification}
+There are several different types of objects specified in the tree. They are: 
+\begin{description}
+\item[obj]objects for the ram part of the code
+\item[driver]drivers for the ram part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section. 
+\item[initobj]seperately-compiled code for the ROM section of coreboot
+\end{description}
+These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax. 
+
+\section{Example: AMD serengeti cheetah}
+\subsection{mainboard/Kconfig}
+Defines Vendor variables. Currently defined variables are: 
+Sources all Kconfig files in the vendor directories. 
+\input{ mainboardkconfig.tex}
+\subsection{mainboard/Makefile.inc}
+There is none at this time.
+\subsection{mainboard/<vendor>/Kconfig}
+We use the amd as a model. The only action currently taken is to source all Kconfig's in the 
+subdirectories. 
+\subsection{mainboard/<vendor>/Makefile.inc}
+We use amd as a model. There is currently no Makefile.inc at this level. 
+\subsection{mainboard/<vendor>/<board>/Kconfig}
+The mainboard Kconfig and Makefile.inc are designed to be the heart of the build. The defines 
+and rules in here determine everything about how a mainboard target is built. 
+We will use serengeti\_cheetah as a model. It defines these variables. 
+\input{ mainboardkconfig.tex}
+\subsection{mainboard/<vendor>/<board>/Makefile.inc}
+This is a fairly complex Makefile.inc. Because this is such a critical component, we are going to excerpt and take it piece by piece. 
+Note that this is the mainboard as of August, 2009, and it may change over time. 
+\subsubsection{objects}
+We define objects in the first part. The mainbard itself is a driver and included unconditionally. Other objects are conditional: 
+\begin{verbatim}
+driver-y +=  mainboard.o
+
+#needed by irq_tables and mptable and acpi_tables
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  fadt.o
+
+#./ssdt.o is in northbridge/amd/amdk8/Config.lb
+obj-$(CONFIG_ACPI_SSDTX_NUM) +=  ssdt2.o
+obj-$(CONFIG_ACPI_SSDTX_NUM) +=  ssdt3.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  ssdt4.o
+driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o
+
+# This is part of the conversion to init-obj and away from included code. 
+
+initobj-y += crt0.o
+\end{verbatim}
+\subsubsection{romcc legacy support}
+We hope to move away from romcc soon, but for now, if one is using romcc, the Makefile.inc must define 
+crt0 include files (assembly code for startup, usually); and several ldscripts. These are taken directly from the 
+old Config.lb. Note that these use the -y syntax and can use the ability to be included conditionally. 
+\begin{verbatim}
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+\end{verbatim}
+\subsubsection{defines}
+There are variables that should never be definable by users, as changing them will break the build or the image. These are set 
+in MAINBOARD\_OPTIONS. 
+\begin{verbatim}
+MAINBOARD_OPTIONS=\
+	-DCONFIG_AP_IN_SIPI_WAIT=0 \
+	-DCONFIG_USE_PRINTK_IN_CAR=1 \
+	-DCONFIG_HAVE_HIGH_TABLES=1
+\end{verbatim}
+\subsubsection{POST\_EVALUATION}
+POST\_EVALUATION rules should be placed after this section: 
+\begin{verbatim}
+ifdef POST_EVALUATION
+\end{verbatim}
+to ensure that the values of variables are correct. 
+Here are the post-evaluation rules for this mainboard: 
+\begin{verbatim}
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+	iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+	perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+	mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+	iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+	perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+	mv pci3.hex ssdt3.c
+           
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+	iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+	perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+	mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/rom.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/rom.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+\end{verbatim}
+The last rule is for romcc, and, again, we hope to eliminate romcc usage and this rule soon. The first set of rules concern ACPI tables. 
+\subsubsection{devicetree.cb}
+Most of the old Config.lb is gone, but one piece remains: the device tree specification. This tree is still required to build a mainboard
+properly, as it defines topology and chips that can be defined no other way. 
+Let's go through the tree. 
+\begin{verbatim}
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+\end{verbatim}
+This topology is always somewhat confusing to newcomers, and even to coreboot veterans. 
+
+We root the tree at the pci-e {\it root complex}. There is always the question of how and where to root the tree. Over the years we 
+have found that the one part that never goes away is the root complex. CPU sockets may be empty or full; but there is always a northbridge
+somewhere, since it runs memory. 
+
+
+What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the 
+CPU socket. So the tree is rooted at the northbridge, which has a link to an apic cluster, and then the CPU. The CPU contains 
+its own APIC, and will define any parameters needed. In this case, we have a northbridge of type 
+{\it northbridge/amd/amdk8/root\_complex}, with its won apic\_cluster device which we turn on, 
+which connects to a {\it cpu/amd/socket\_F}, 
+which has an apic, which is on. 
+
+Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here 
+is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many 
+BIOSes) that the BSP be CPU 0; any CPU will do. 
+\begin{verbatim}
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  northbridge 
+				#  devices on link 0, link 0 == LDT 0
+\end{verbatim}
+Here begins the pci domain, which usually starts with 0. Then there is the northbridge, which bridges to the PCI bus. On 
+Opterons, certain CPU control registers are managed in PCI config space in device 18.0 (BSP), 19.0 (AP), and up. 
+\begin{verbatim}
+				chip southbridge/amd/amd8132
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+\end{verbatim}
+This is the 8132, a bridge to a secondary PCI bus. 
+\begin{verbatim}
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+					end
+\end{verbatim}
+The 8111 is a bridge to other busses and to the legacy ISA devices such as superio. 
+\begin{verbatim}
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	        			device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+                	        			device pnp 2e.8 off end #  GPIO2
+                	        			device pnp 2e.9 off end #  GPIO3
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
+						end
+					end
+\end{verbatim}
+The pnp refers to the many Plug N Play devices on a superio. 2e refers to the base I/O address of the superio, and the number following the 
+2e (i.e. 2e.1) is the Logical Device Number, or LDN. Each LDN has a common configuration (base, irq, etc.) and these are set by the statements under the LDN. 
+\begin{verbatim}
+					device pci 1.1 on end
+					device pci 1.2 on end
+\end{verbatim}
+More devices. These statements set up placeholders in the device tree. 
+\begin{verbatim}
+					device pci 1.3 on
+                                                chip drivers/i2c/i2cmux # pca9556 smbus mux
+                                                        device i2c 18 on #0 pca9516 1
+                                                                chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                        end
+                                                        device i2c 18 on #1 pca9516 2
+                                                                chip drivers/generic/generic #dimm 1-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-2-0
+                                                                        device i2c 54 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-2-1
+                                                                        device i2c 55 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-3-0
+                                                                        device i2c 56 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-3-1
+                                                                        device i2c 57 on end
+                                                                end
+                                                        end
+						end
+					end # acpi
+\end{verbatim}
+These are the i2c devices. 
+\begin{verbatim}
+					device pci 1.5 off end
+					device pci 1.6 off end
+\end{verbatim}
+More placeholders. 
+\begin{verbatim}
+               	                register "ide0_enable" = "1"
+                	                register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0
+
+\end{verbatim}
+These "register" commands set controls in the southbridge. 
+\begin{verbatim}
+                       device pci 18.0 on end
+                        device pci 18.0 on end  
+\end{verbatim}
+These are the other two hypertransport links. 
+\begin{verbatim}
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+\end{verbatim}
+The 18.1 devices are, again, northbridge control for various k8 functions. 
+\begin{verbatim}
+		end
+  \end{verbatim}
+That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much here. 
+\begin{verbatim}
+              chip northbridge/amd/amdk8
+                        device pci 19.0 on #  northbridge
+                                chip southbridge/amd/amd8151
+                                        # the on/off keyword is mandatory
+                                        device pci 0.0 on end
+                                        device pci 1.0 on end
+                                end
+                        end #  device pci 19.0
+
+                        device pci 19.0 on end
+                        device pci 19.0 on end
+                        device pci 19.1 on end
+                        device pci 19.2 on end
+                        device pci 19.3 on end
+                end
+
+
+\end{verbatim}
+\begin{verbatim}
+	end #pci_domain
+#        chip drivers/generic/debug
+#        	device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 off end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 off end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#                device pnp 0.7 off end # tsc
+#       end
+
+end
+\end{verbatim}
+This is a trick used to debug by creating entries in the device tree. 
+
+\subsection{cpu socket}
+The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only 
+the socket, and the socket, in turn, references the various model CPUs which can be plugged into it. The socket is thus the focus 
+of all defines and Makefile controls for building the CPU components of a board. 
+
+\subsubsection{ /cpu/Kconfig}
+Defines variables. Current variables are: 
+\input{cpukconfig.tex}
+Sources all Kconfig files in the vendor directories. 
+\subsubsection{ /cpu/Makefile.inc}
+Unconditionally sources all Makefile.inc in the vendor directories. 
+
+\subsection{cpu/<vendor>/Kconfig}
+The only action currently taken is to source all Kconfig's in the 
+subdirectories. 
+\subsection{cpu/<vendor>/Makefile.inc}
+{\em Conditionally} source the socket directories. 
+Example: 
+\begin{verbatim}
+subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F
+\end{verbatim}
+.
+CONFIG\_CPU\_AMD\_SOCKET\_F is set in a mainboard file. 
+
+\subsection{cpu/<vendor>/<socket>/Kconfig}
+Set variables that relate to this {\em socket}, and {\em any models that plug into this socket}. Note that 
+the socket, as much as possible, should control the models, because the models may plug into many sockets. 
+Socket\_F currently sets: 
+\input{socketfkconfig.tex}
+
+It sources only those Kconfigs that relate to this particular socket, i.e. not all possible models are sourced. 
+
+\subsection{cpu/<vendor>/<model>/Kconfig}
+CPU Model Kconfigs only set variables, We do not expect that they will source any other Kconfig. The socket Kconfig should do that
+if needed. 
+\subsection{cpu/<vendor>/<model>/Makefile.inc}
+The Makefile.inc {\em unconditionally} specifies drivers and objects to be included in the build. There is no conditional 
+compilation at this point. IF a socket is included, it includes the models. If a model is included, it should include {em all} 
+objects, because it is not possible to determine at build time what options may be needed for a given model CPU. 
+This Makefile.inc includes no other Makefile.inc files; any inclusion should be done in the socket Makefile.inc.
+
+\subsection{northbridge}
+\subsubsection{northbridge/Kconfig}
+No variables. Source all vendor directory Kconfigs. 
+\subsubsection{northbridge/Kconfig}
+No variables. unconditionally include all vendor Makefile.inc
+\subsubsection{northbridge/<vendor>/Kconfig}
+No variables. Source all chip directory Kconfigs. 
+\subsubsection{northbridge/<vendor>/Makefile.inc}
+No variables. {\em Conditionally} include all chipset Makefile.inc. The variable 
+is the name of the part, e.g. 
+\begin{verbatim}
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8
+\end{verbatim}
+.
+\subsubsection{northbridge/<vendor>/<chip>/Kconfig}
+Typically a small number of variables. One defines the part name. Here is an example 
+of the variables defined for the K8. 
+\begin{verbatim}
+config NORTHBRIDGE_AMD_AMDK8
+	bool
+	default n
+
+config AGP_APERTURE_SIZE
+	hex
+	default 0x4000000
+
+config HAVE_HIGH_TABLES
+	int
+	default 1
+\end{verbatim}
+\subsubsection{northbridge/<vendor>/<chip>/Makefile.inc}
+Typically very small set of rules, and very simple. 
+Since this file is already conditionally included, 
+we don't need to test for the chipset CONFIG variable. We
+can therefore test other variables (which is part of the reason
+we set up conditional inclusion of this file, instead
+of unconditionally including it). Here is an example from AMD K8.
+Note that we can make a variable conditional on the ACPI tables. 
+\begin{verbatim}
+driver-y += northbridge.o
+driver-y += misc_control.o
+obj-y +=  get_sblk_pci1234.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  amdk8_acpi.o
+\end{verbatim}
+
+\subsubsection{northbridge/Kconfig}
+
+
+
+
+\subsubsection{vendor and part}
+\subsection{southbridge}
+\subsubsection{vendor and part}
+\subsection{superio}
+\subsection{i2cmux}
+\subsubsection{vendor and part}
+
+\end{document}

Modified: trunk/coreboot-v2/documentation/Makefile
===================================================================
--- trunk/coreboot-v2/documentation/Makefile	2009-08-12 05:49:48 UTC (rev 4533)
+++ trunk/coreboot-v2/documentation/Makefile	2009-08-12 15:00:51 UTC (rev 4534)
@@ -7,7 +7,7 @@
 
 FIGS=codeflow.pdf hypertransport.pdf
 
-all: LinuxBIOS-AMD64.pdf 
+all: LinuxBIOS-AMD64.pdf Kconfig.pdf
 
 SVG2PDF=$(shell which svg2pdf)
 INKSCAPE=$(shell which inkscape)
@@ -39,9 +39,34 @@
 LinuxBIOS-AMD64.pdf: $(FIGS) LinuxBIOS-AMD64.tex LinuxBIOS-AMD64.toc
 	$(PDFLATEX) LinuxBIOS-AMD64.tex
 
+Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex
+	$(PDFLATEX) $<
+
+# quick, somebody! make me a macro!
+mainboardkconfig.tex: ../src/mainboard/Kconfig
+	echo '\begin{verbatim}' > $@
+	grep '^config' $< | awk '{print $2}'  >>$@
+	echo '\end{verbatim}' >> $@
+
+skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig
+	echo '\begin{verbatim}' > $@
+	grep '^config' $< | awk '{print $2}'  >>$@
+	echo '\end{verbatim}' >> $@
+
+cpukconfig.tex: ../src/cpu/Kconfig
+	echo '\begin{verbatim}' > $@
+	grep '^config' $< | awk '{print $2}'  >>$@
+	echo '\end{verbatim}' >> $@
+
+socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig
+	echo '\begin{verbatim}' > $@
+	grep '^config' $< | awk '{print $2}'  >>$@
+	echo '\end{verbatim}' >> $@
+
+
 clean:
-	rm -f *.aux *.idx *.log *.toc *.out $(FIGS)
+	rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex
 
 distclean: clean
-	rm -f LinuxBIOS-AMD64.pdf
+	rm -f LinuxBIOS-AMD64.pdf mainboardkconfig.tex
 	

Added: trunk/coreboot-v2/src/Kconfig
===================================================================
--- trunk/coreboot-v2/src/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,275 @@
+##
+## This file is part of the coreboot repair project.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following conditions
+## are met:
+## 1. Redistributions of source code must retain the above copyright
+##    notice, this list of conditions and the following disclaimer.
+## 2. Redistributions in binary form must reproduce the above copyright
+##    notice, this list of conditions and the following disclaimer in the
+##    documentation and/or other materials provided with the distribution.
+## 3. The name of the author may not be used to endorse or promote products
+##    derived from this software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+## ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+## SUCH DAMAGE.
+##
+
+mainmenu "Coreboot Configuration"
+
+source src/mainboard/Kconfig
+source src/arch/i386/Kconfig
+source src/arch/ppc/Kconfig
+source src/devices/Kconfig
+source src/northbridge/Kconfig
+source src/southbridge/Kconfig
+source src/superio/Kconfig
+source src/cpu/Kconfig
+
+config CBFS
+	bool
+	default y
+
+config HAVE_HIGH_TABLES
+	bool
+	default y
+
+config PCI_BUS_SEGN_BITS
+	int
+	default 0
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+        hex
+        default 0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+        hex
+        default 0
+
+config CPU_ADDR_BITS
+	int
+	default 36
+
+config XIP_ROM_BASE
+	hex
+	default 0xfffe0000
+
+config XIP_ROM_SIZE
+	hex
+	default 0x20000
+
+config LB_CKS_RANGE_START
+	int
+	default 49
+
+config LB_CKS_RANGE_END
+	int
+	default 125
+
+config LB_CKS_LOC
+	int
+	default 126
+
+config LOGICAL_CPUS
+	int
+	default 1
+
+config PCI_ROM_RUN
+	int
+	default 0
+
+config HT_CHAIN_UNITID_BASE
+	int
+	default 1
+
+config HT_CHAIN_END_UNITID_BASE
+	int
+	default 32
+
+config HEAP_SIZE
+	hex
+	default 0x2000
+
+config COREBOOT_V2
+	bool
+	default y
+
+config COREBOOT_V4
+	bool
+	default y
+
+config DEBUG
+	bool
+	default n
+
+config USE_PRINTK_IN_CAR
+	bool
+	default n
+
+config USE_OPTION_TABLE
+	bool
+	default n
+
+config MAX_CPUS
+	int
+	default 1
+
+config MMCONF_SUPPORT_DEFAULT
+	bool
+	default n
+
+config MMCONF_SUPPORT
+	bool
+	default n
+
+config LB_MEM_TOPK
+	int
+	default 2048
+
+config MULTIBOOT
+	bool
+	default n
+
+config COMPRESSED_PAYLOAD_LZMA
+	bool
+	default y
+
+config COMPRESSED_PAYLOAD_NRV2B
+	bool
+	default n
+
+source src/console/Kconfig
+
+config HAVE_ACPI_RESUME
+	bool
+	default n
+
+config ACPI_SSDTX_NUM
+	int
+	default 0
+
+config HAVE_ACPI_TABLES
+	bool
+	default n
+
+config HAVE_FALLBACK_BOOT
+	bool
+	default y
+
+config USE_FALLBACK_IMAGE
+	bool
+	default y
+
+config HAVE_HARD_RESET
+	bool
+	default n
+
+config HAVE_INIT_TIMER
+	bool
+	default n
+
+config HAVE_MAINBOARD_RESOURCES
+	bool
+	default n
+
+config HAVE_MOVNTI
+	bool
+	default y
+
+config HAVE_MP_TABLE
+	bool
+	default n
+
+config HAVE_OPTION_TABLE
+	bool
+	default y
+
+config HAVE_PIRQ_TABLE
+	bool
+	default n
+
+config PIRQ_ROUTE
+	bool
+	default n
+
+config HAVE_SMI_HANDLER
+	bool
+	default n
+
+config PCI_IO_CFG_EXT
+	bool
+	default n
+
+config IOAPIC
+	bool
+	default n
+
+menu "Drivers"
+
+endmenu
+
+menu "Payload"
+
+config COMPRESSED_PAYLOAD_LZMA
+	bool "Use LZMA compression for payloads"
+	default yes
+
+choice
+	prompt "Payload type"
+	default PAYLOAD_NONE
+
+config PAYLOAD_ELF
+	bool "An ELF executable payload file"
+	help
+	  Select this option if you have a payload image (an ELF file)
+	  which coreboot should run as soon as the basic hardware
+	  initialization is completed.
+
+	  You will be able to specify the location and file name of the
+	  payload image later.
+
+config PAYLOAD_NONE
+	bool "No payload"
+	help
+	  Select this option if you want to create an "empty" coreboot
+	  ROM image for a certain mainboard, i.e. a coreboot ROM image
+	  which does not yet contain a payload.
+
+	  For such an image to be useful, you have to use the 'lar' tool
+	  to add a payload to the ROM image later.
+
+endchoice
+
+config NORMAL_PAYLOAD_FILE
+	string "Normal payload path and filename"
+	depends on PAYLOAD_ELF
+	default "payload.elf"
+	help
+	  The path and filename of the ELF executable file to use as normal payload.
+
+config FALLBACK_PAYLOAD_FILE
+	string "Fallback payload path and filename"
+	depends on PAYLOAD_ELF
+	default "payload.elf"
+	help
+	  The path and filename of the ELF executable file to use as fallback payload.
+
+endmenu
+
+config GDB_STUB
+	bool "Enable GDB debugging support"
+	default y
+	help
+	  If this is set, then you will be able to set breakpoints for gdb debugging. 
+	  See: src/arch/i386/lib/c_start.S
+

Added: trunk/coreboot-v2/src/arch/i386/Kconfig
===================================================================
--- trunk/coreboot-v2/src/arch/i386/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/arch/i386/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,59 @@
+config ARCH_X86
+	boolean
+	help
+	  This option is used to set the architecture of a mainboard.
+	  It is usually set in mainboard/*/Kconfig.
+
+config ARCH
+	string
+	default i386
+	depends on ARCH_X86
+	help
+	  This is the name of the respective subdirectory in arch/.
+
+config ROMBASE
+	hex 
+	default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048
+	default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024
+	default 0xfff80000 if COREBOOT_ROMSIZE_KB_512
+	default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256
+	default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128
+
+config PAYLOAD_SIZE
+	hex
+	default 0
+
+config ROM_PAYLOAD_START
+	hex
+	default 0xffe00000 if COREBOOT_ROMSIZE_KB_2048
+	default 0xfff00000 if COREBOOT_ROMSIZE_KB_1024
+	default 0xfff80000 if COREBOOT_ROMSIZE_KB_512
+	default 0xfffc0000 if COREBOOT_ROMSIZE_KB_256
+	default 0xfffe0000 if COREBOOT_ROMSIZE_KB_128
+
+config ROM_IMAGE_SIZE
+	hex
+	default 0x200000 if COREBOOT_ROMSIZE_KB_2048
+	default 0x100000 if COREBOOT_ROMSIZE_KB_1024
+	default 0x80000 if COREBOOT_ROMSIZE_KB_512
+	default 0x40000 if COREBOOT_ROMSIZE_KB_256
+	default 0x20000 if COREBOOT_ROMSIZE_KB_128
+
+config RAMBASE
+	hex
+	default 0x100000
+
+config STACK_SIZE
+	hex
+	default 0x8000
+
+
+menu "Misc Options"
+
+config MAX_REBOOT_CNT
+	int "Maximum Reboot Count"
+	default 3
+
+endmenu
+
+

Added: trunk/coreboot-v2/src/arch/i386/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/arch/i386/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/arch/i386/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,98 @@
+#######################################################################
+# Take care of subdirectories
+subdirs-y += boot
+subdirs-y += init
+subdirs-y += lib
+subdirs-y += smp
+
+obj-y += ../../option_table.o
+
+ifdef POST_EVALUATION
+#######################################################################
+# Build the final rom image
+
+$(obj)/coreboot.rom: $(obj)/coreboot.bootblock $(obj)/coreboot_ram $(CBFSTOOL)
+	$(Q)rm -f $@
+	$(Q)$(CBFSTOOL) $@ create $(shell expr 1024 \* $(CONFIG_COREBOOT_ROMSIZE_KB)) 131072 $(obj)/coreboot.bootblock
+	$(Q)$(CBFSTOOL) $@ add-stage  $(obj)/coreboot_ram normal/coreboot_ram $(CBFS_COMPRESS_FLAG)
+	$(Q)if [ -f fallback/coreboot_apc ]; \
+	then \
+		$(CBFSTOOL) $@ add-stage fallback/coreboot_apc fallback/coreboot_apc $(CBFS_COMPRESS_FLAG); \
+	fi
+	$(Q)$(CBFSTOOL) $@ add-stage  $(obj)/coreboot_ram fallback/coreboot_ram $(CBFS_COMPRESS_FLAG)
+ifeq ($(CONFIG_PAYLOAD_NONE),y)
+	$(Q)printf "    PAYLOAD    none (as specified by user)\n"
+else
+	printf "    PAYLOAD    $(CONFIG_FALLBACK_PAYLOAD_FILE) $(COMPRESSFLAG)\n"
+	$(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE)  fallback/payload $(CBFS_COMPRESS_FLAG)
+	printf "    PAYLOAD    $(CONFIG_NORMAL_PAYLOAD_FILE) $(COMPRESSFLAG)\n"
+	$(Q)$(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_NORMAL_PAYLOAD_FILE)  normal/payload $(CBFS_COMPRESS_FLAG)
+	$(CBFSTOOL) ./build/coreboot.rom print
+endif
+
+
+#######################################################################
+# Build the bootblock
+
+BOOTBLOCK_SIZE=65536
+
+$(obj)/coreboot.bootblock: $(obj)/coreboot.strip
+	$(Q)printf "    CREATE     $(subst $(obj)/,,$(@))\n"
+	$(Q)dd if=$< of=$(obj)/coreboot.bootblock.one obs=$(BOOTBLOCK_SIZE) conv=sync
+	$(Q)cat $(obj)/coreboot.bootblock.one $(obj)/coreboot.bootblock.one > $(obj)/coreboot.bootblock
+
+$(obj)/coreboot.strip: $(obj)/coreboot
+	$(Q)printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
+	$(Q)$(OBJCOPY) -O binary $< $@
+
+$(obj)/ldscript.ld: $(ldscripts) $(obj)/ldoptions
+	$(Q)printf 'INCLUDE "ldoptions"\n' > $@
+	$(Q)printf '$(foreach ldscript,$(ldscripts),INCLUDE "$(ldscript)"\n)' >> $@
+
+$(obj)/crt0_includes.h: $(crt0s)
+	$(Q)printf '$(foreach crt0,$(obj)/config.h $(crt0s),#include "$(crt0)"\n)' > $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/crt0.o: $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s
+	$(CC) -I$(obj) -Wa,-acdlns -c -o $@ $<  > $(dir $@)/crt0.disasm
+
+$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(src)/arch/i386/init/crt0.S.lb $(obj)/crt0_includes.h
+	$(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@
+
+$(obj)/coreboot: $(initobjs) $(obj)/ldscript.ld
+	$(Q)printf "    LINK       $(subst $(obj)/,,$(@))\n"
+	$(Q)$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/ldscript.ld $(initobjs)
+	$(Q)$(NM) -n $(obj)/coreboot | sort > $(obj)/coreboot.map
+
+#######################################################################
+# i386 specific tools
+
+$(obj)/option_table.h $(obj)/option_table.c: $(obj)/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout
+	$(Q)printf "    OPTION     $(subst $(obj)/,,$(@))\n"
+	$(Q)$(obj)/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $(obj)/option_table.h --option $(obj)/option_table.c
+
+$(obj)/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h
+	$(Q)printf "    HOSTCC     $(subst $(obj)/,,$(@))\n"
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) -include $(obj)/config.h $< -o $@
+
+#######################################################################
+# Build the coreboot_ram (stage 2)
+
+$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/config/coreboot_ram.ld #ldoptions
+	$(Q)printf "    CC         $(subst $(obj)/,,$(@))\n"
+	$(Q)$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/config/coreboot_ram.ld $(obj)/coreboot_ram.o
+	$(Q)$(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map
+
+$(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME)
+	$(Q)printf "    CC         $(subst $(obj)/,,$(@))\n"
+	$(Q)$(CC) -nostdlib -r -o $@ $(obj)/arch/i386/lib/c_start.o $(drivers) -Wl,-\( $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)
+
+$(obj)/coreboot.a: $(objs)
+	$(Q)printf "    AR         $(subst $(obj)/,,$(@))\n"
+	$(Q)rm -f $(obj)/coreboot.a
+	$(Q)$(AR) cr $(obj)/coreboot.a $(objs)
+
+
+#######################################################################
+# done
+
+endif

Added: trunk/coreboot-v2/src/arch/i386/boot/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/arch/i386/boot/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/arch/i386/boot/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,10 @@
+
+obj-y += boot.o
+obj-y += coreboot_table.o
+obj-$(CONFIG_MULTIBOOT) += multiboot.o
+obj-y += tables.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += pirq_routing.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpi.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.o
+obj-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S
+

Added: trunk/coreboot-v2/src/arch/i386/init/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/arch/i386/init/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/arch/i386/lib/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/arch/i386/lib/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,15 @@
+obj-y += c_start.o
+obj-y += cpu.o
+obj-y += pci_ops_conf1.o
+obj-y += pci_ops_conf2.o
+obj-y += pci_ops_mmconf.o
+obj-y += pci_ops_auto.o
+obj-y += exception.o
+
+initobj-y += printk_init.o
+initobj-y += cbfs_and_run.o
+
+ifdef POST_EVALUATION
+$(obj)/arch/i386/lib/console.o :: $(obj)/build.h
+endif
+

Added: trunk/coreboot-v2/src/arch/i386/smp/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/arch/i386/smp/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/arch/i386/smp/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,5 @@
+obj-$(CONFIG_HAVE_MP_TABLE) += mpspec.o
+# what about this: how awkward.
+#object ioapic.o CONFIG_IOAPIC
+
+

Added: trunk/coreboot-v2/src/arch/ppc/Kconfig
===================================================================
--- trunk/coreboot-v2/src/arch/ppc/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/arch/ppc/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,13 @@
+config ARCH_POWERPC
+	boolean
+	help
+	  This option is used to set the architecture of a mainboard.
+	  It is usually set in mainboard/*/Kconfig.
+
+config ARCH
+	string
+	default ppc
+	depends on ARCH_POWERPC
+	help
+	  This is the name of the respective subdirectory in arch/.
+

Added: trunk/coreboot-v2/src/boot/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/boot/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/boot/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+obj-y += hardwaremain.o
+obj-y += selfboot.o

Added: trunk/coreboot-v2/src/console/Kconfig
===================================================================
--- trunk/coreboot-v2/src/console/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/console/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,40 @@
+menu "Console Options"
+
+config SERIAL_CONSOLE
+	bool "See output on the serial port console"
+	default y
+
+config TTYS0_BASE
+	hex "I/O base for the serial port (default 0x3f8)"
+	depends on SERIAL_CONSOLE
+	default 0x3f8
+
+config SERIAL_SET_SPEED
+	bool "Override the serial console baud rate"
+	default y
+	depends on SERIAL_CONSOLE
+
+config TTYS0_BAUD
+	int "Serial console baud rate (default 115200)"
+	depends on SERIAL_SET_SPEED
+	default 115200
+
+config USBDEBUG_DIRECT
+	bool "Support a USB debug dongle. Not supported on all chipsets. FIX DEPENDENCY HERE"
+	default n
+
+config CONSOLE_VGA
+	bool
+	default n
+
+config MAXIMUM_CONSOLE_LOGLEVEL
+	int
+	default 9
+
+config DEFAULT_CONSOLE_LOGLEVEL
+	int
+	default 9
+
+endmenu
+
+

Added: trunk/coreboot-v2/src/console/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/console/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/console/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,12 @@
+obj-y +=  printk.o
+obj-y +=  console.o
+obj-y +=  vtxprintf.o
+obj-y +=  vsprintf.o
+initobj-y +=  vtxprintf.o
+initobj-y +=  vsprintf.o
+driver-$(CONFIG_SERIAL_CONSOLE) +=  uart8250_console.o
+driver-$(CONFIG_USBDEBUG_DIRECT) +=  usbdebug_direct_console.o
+driver-$(CONFIG_CONSOLE_VGA) +=  vga_console.o
+driver-$(CONFIG_CONSOLE_BTEXT) +=  btext_console.o
+driver-$(CONFIG_CONSOLE_BTEXT) +=  font-8x16.o
+driver-$(CONFIG_CONSOLE_LOGBUF) +=  logbuf_console.o

Modified: trunk/coreboot-v2/src/console/console.c
===================================================================
--- trunk/coreboot-v2/src/console/console.c	2009-08-12 05:49:48 UTC (rev 4533)
+++ trunk/coreboot-v2/src/console/console.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -8,8 +8,6 @@
 #include <pc80/mc146818rtc.h>
 
 
-static int initialized;
-
 /* initialize the console */
 void console_init(void)
 {
@@ -22,7 +20,6 @@
 			continue;
 		driver->init();
 	}
-	initialized = 1;
 }
 
 static void __console_tx_byte(unsigned char byte)
@@ -45,8 +42,6 @@
 
 void console_tx_byte(unsigned char byte)
 {
-	if (!initialized)
-		return;
 	if (byte == '\n')
 		__console_tx_byte('\r');
 	__console_tx_byte(byte);
@@ -55,8 +50,6 @@
 unsigned char console_rx_byte(void)
 {
 	struct console_driver *driver;
-	if (!initialized)
-		return 0;
 	for(driver = console_drivers; driver < econsole_drivers; driver++) {
 		if (driver->tst_byte)
 			break;
@@ -70,8 +63,6 @@
 int console_tst_byte(void)
 {
 	struct console_driver *driver;
-	if (!initialized)
-		return 0;
 	for(driver = console_drivers; driver < econsole_drivers; driver++)
 		if (driver->tst_byte)
 			return driver->tst_byte();

Added: trunk/coreboot-v2/src/cpu/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,18 @@
+#source src/cpu/amd/Kconfig
+source src/cpu/emulation/Kconfig
+source src/cpu/intel/Kconfig
+source src/cpu/via/Kconfig
+source src/cpu/x86/Kconfig
+source src/cpu/ppc/Kconfig
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffdf8000 if CPU_INTEL_CORE
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000 if CPU_INTEL_CORE
+
+config SMP
+	bool
+	default n

Added: trunk/coreboot-v2/src/cpu/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,8 @@
+#input amd
+subdirs-y += intel
+subdirs-y += via
+subdirs-y += emulation
+#input ppc
+#input simple_init
+#input via
+#input x86

Added: trunk/coreboot-v2/src/cpu/amd/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,8 @@
+source src/cpu/amd/socket_754/Kconfig
+source src/cpu/amd/socket_939/Kconfig
+source src/cpu/amd/socket_940/Kconfig
+source src/cpu/amd/socket_AM2/Kconfig
+source src/cpu/amd/socket_AM2r2/Kconfig
+source src/cpu/amd/socket_F/Kconfig
+source src/cpu/amd/socket_F_1207/Kconfig
+source src/cpu/amd/socket_S1G1/Kconfig

Added: trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/socket_F/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,3 @@
+config CPU_AMD_SOCKET_F
+	bool
+	default false

Added: trunk/coreboot-v2/src/cpu/emulation/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/emulation/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/emulation/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+source src/cpu/emulation/qemu-x86/Kconfig
+

Added: trunk/coreboot-v2/src/cpu/emulation/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/emulation/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/emulation/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+subdirs-y += qemu-x86

Added: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,4 @@
+config CPU_EMULATION_QEMU_X86
+        bool
+        default false
+

Added: trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/emulation/qemu-x86/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+obj-$(CONFIG_CPU_EMULATION_QEMU_X86) += northbridge.o

Added: trunk/coreboot-v2/src/cpu/intel/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,4 @@
+source src/cpu/intel/model_6ex/Kconfig
+source src/cpu/intel/model_6fx/Kconfig
+source src/cpu/intel/socket_mFCPGA478/Kconfig
+source src/cpu/intel/socket_PGA370/Kconfig
\ No newline at end of file

Added: trunk/coreboot-v2/src/cpu/intel/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,14 @@
+# Note: from here on down, we are socket-centric. Socket choice determines what other cpu files are included. 
+# Therefore:
+# ONLY include Makefile.inc from socket directories!
+
+subdirs-y += speedstep
+subdirs-y += socket_mFCPGA478
+subdirs-y += socket_PGA370
+
+#socket_mPGA478
+#socket_mPGA479M
+#socket_mPGA603
+#socket_mPGA604
+#socket_mPGA604_533Mhz
+#socket_mPGA604_800Mhz

Added: trunk/coreboot-v2/src/cpu/intel/hyperthreading/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/hyperthreading/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/hyperthreading/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+obj-y += intel_sibling.o

Added: trunk/coreboot-v2/src/cpu/intel/microcode/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/microcode/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/microcode/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+obj-y += microcode.o

Added: trunk/coreboot-v2/src/cpu/intel/model_69x/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_69x/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/model_69x/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+driver-y += model_69x_init.o

Added: trunk/coreboot-v2/src/cpu/intel/model_6dx/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6dx/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/model_6dx/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+driver-y += model_6dx_init.o

Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6ex/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/model_6ex/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,4 @@
+config CPU_INTEL_CORE
+	bool
+	default n
+	select SMP

Added: trunk/coreboot-v2/src/cpu/intel/model_6ex/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6ex/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/model_6ex/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+driver-y += model_6ex_init.o

Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6fx/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/model_6fx/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+# select HAVE_MOVNTI

Added: trunk/coreboot-v2/src/cpu/intel/model_6fx/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6fx/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/model_6fx/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+driver-y += model_6fx_init.o

Added: trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/model_6xx/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Ron Minnich <rminnich at gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+obj-y += model_6xx_init.o
+

Added: trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config CPU_INTEL_SOCKET_PGA370
+	bool
+	default false

Added: trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/socket_PGA370/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ifeq ($(CONFIG_CPU_INTEL_SOCKET_PGA370),y)
+	obj-y += socket_PGA370.o
+	subdirs-y += ../model_6xx
+	subdirs-y += ../../x86/tsc
+	subdirs-y += ../../x86/mtrr
+	subdirs-y += ../../x86/fpu
+	subdirs-y += ../../x86/mmx
+	subdirs-y += ../../x86/sse
+	subdirs-y += ../../x86/lapic
+	subdirs-y += ../../x86/cache
+	subdirs-y += ../../x86/smm
+	subdirs-y += ../microcode
+endif
+

Added: trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,3 @@
+config CPU_INTEL_SOCKET_MFCPGA478
+	bool
+	default false

Added: trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/socket_mFCPGA478/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,17 @@
+ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCPGA478),y)
+	obj-y += socket_mFCPGA478.o
+	subdirs-y += ../model_69x
+	subdirs-y += ../model_6dx
+	subdirs-y += ../model_6ex
+	subdirs-y += ../model_6fx
+	subdirs-y += ../../x86/tsc
+	subdirs-y += ../../x86/mtrr
+	subdirs-y += ../../x86/fpu
+	subdirs-y += ../../x86/mmx
+	subdirs-y += ../../x86/sse
+	subdirs-y += ../../x86/lapic
+	subdirs-y += ../../x86/cache
+	subdirs-y += ../../x86/smm
+	subdirs-y += ../microcode
+	subdirs-y += ../hyperthreading
+endif

Added: trunk/coreboot-v2/src/cpu/intel/speedstep/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/speedstep/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/intel/speedstep/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_HAVE_ACPI_TABLES), y)
+ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCPGA478), y)
+	obj-y += acpi.o
+endif
+endif

Added: trunk/coreboot-v2/src/cpu/ppc/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/ppc/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/cpu/ppc/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/ppc/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/ppc/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,6 @@
+#subdirs-y += ../simple_init
+#subdirs-y += mpc74xx
+#subdirs-y += ppc4xx
+#subdirs-y += ppc7xx
+#subdirs-y += ppc970
+

Added: trunk/coreboot-v2/src/cpu/simple_init/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/simple_init/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/simple_init/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+obj-y += simple_cpu_init.o

Added: trunk/coreboot-v2/src/cpu/via/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/via/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/via/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+source src/cpu/via/model_c7/Kconfig

Added: trunk/coreboot-v2/src/cpu/via/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/via/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/via/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#subdirs-y += model_c7
+subdirs-y += model_c7

Added: trunk/coreboot-v2/src/cpu/via/model_c7/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/via/model_c7/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/via/model_c7/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,3 @@
+config CPU_VIA_C7
+	bool
+	default n

Added: trunk/coreboot-v2/src/cpu/via/model_c7/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/via/model_c7/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/via/model_c7/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,13 @@
+ifeq ($(CONFIG_CPU_VIA_C7),y)
+	subdirs-y += ../../x86/tsc
+	subdirs-y += ../../x86/mtrr
+	subdirs-y += ../../x86/fpu
+	subdirs-y += ../../x86/mmx
+	subdirs-y += ../../x86/sse
+	subdirs-y += ../../x86/lapic
+	subdirs-y += ../../x86/cache
+	subdirs-y += ../../x86/smm
+	subdirs-y += ../../intel/microcode
+endif
+
+obj-y += model_c7_init.o

Added: trunk/coreboot-v2/src/cpu/x86/Kconfig
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/x86/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,11 @@
+config SERIAL_CPU_INIT
+	bool
+	default y
+
+config XIP_ROM_BASE
+	hex
+	default 0xfffe0000
+
+config XIP_ROM_BASE
+	hex
+	default 0x2000

Added: trunk/coreboot-v2/src/cpu/x86/cache/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/cache/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/x86/cache/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+obj-y += cache.o

Added: trunk/coreboot-v2/src/cpu/x86/fpu/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/fpu/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/x86/fpu/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/cpu/x86/lapic/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/lapic/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/x86/lapic/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,4 @@
+obj-y += lapic.o
+obj-y += lapic_cpu_init.o
+obj-y += secondary.o
+

Added: trunk/coreboot-v2/src/cpu/x86/mmx/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/mmx/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/x86/mmx/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/cpu/x86/mtrr/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/mtrr/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/x86/mtrr/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+obj-y += mtrr.o

Added: trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/x86/smm/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,45 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+##if CONFIG_HAVE_SMI_HANDLER
+##	object smmrelocate.S
+##
+##	smmobject smmhandler.S
+##	smmobject smihandler.o
+##
+##	makerule smm.o
+##		depends	"$(SMM-OBJECTS) $(TOP)/src/console/printk.o $(TOP)/src/console/vtxprintf.o $(LIBGCC_FILE_NAME)" 
+##		action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^"
+##	end
+##
+##	makerule smm
+##		depends	"smm.o $(TOP)/src/cpu/x86/smm/smm.ld ldoptions" 
+##		action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/cpu/x86/smm/smm.ld smm.o"
+##		action 	"$(CONFIG_CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
+##		action  "$(OBJCOPY) -O binary smm.elf smm"
+##	end
+##
+##	makerule smm_bin.c
+##		depends "smm"
+##		action "(echo 'unsigned char smm[] = {'; od -vtx1 smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c smm |awk '{print $$1;}' ; echo ';')  > smm_bin.c"
+##	end
+##
+##	object ./smm_bin.o
+##end

Added: trunk/coreboot-v2/src/cpu/x86/sse/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/sse/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/x86/sse/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/cpu/x86/tsc/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/tsc/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/cpu/x86/tsc/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,7 @@
+obj-y += delay_tsc.o
+
+# default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
+# if CONFIG_UDELAY_TSC 
+#	default CONFIG_HAVE_INIT_TIMER=1
+# 	object delay_tsc.o  
+# end

Added: trunk/coreboot-v2/src/devices/Kconfig
===================================================================
--- trunk/coreboot-v2/src/devices/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/devices/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 coresystems GmbH
+## (Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH)
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+menu "Devices"
+
+config VGA_ROM_RUN
+	bool
+	help
+	  Execute PCI/AGP option ROMs if available. This is required to
+	  enable PCI/AGP VGA plugin cards. 
+
+choice
+        prompt "Execute PCI Option ROMs"
+        default  PCI_OPTION_ROM_RUN_REALMODE
+        help
+          Execute PCI/AGP option ROMs if available. You can choose to
+          execute PCI option ROMs natively (32bit x86 system required),
+          in an emulator (x86emu), or ignore option ROM execution.
+
+	config PCI_OPTION_ROM_RUN_REALMODE
+		prompt "Run VGA ROMs"
+		bool
+		select VGA_ROM_RUN
+		help
+	  	Execute PCI/AGP option ROMs if available. This is required to
+	  	enable PCI/AGP VGA plugin cards. 
+
+	config NO_RUN
+		prompt "DO NOT Run VGA ROMs"
+		bool
+		help
+	  	Execute PCI/AGP option ROMs if available. This is required to
+	  	enable PCI/AGP VGA plugin cards. 
+
+endchoice
+endmenu

Added: trunk/coreboot-v2/src/devices/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/devices/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/devices/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,21 @@
+obj-y += device.o
+obj-y += root_device.o
+obj-y += device_util.o
+obj-y += pci_device.o
+obj-y += hypertransport.o
+obj-y += pcix_device.o
+obj-y += pciexp_device.o
+obj-y += agp_device.o
+obj-y += cardbus_device.o
+obj-y += pnp_device.o
+obj-y += pci_ops.o
+obj-y += smbus_ops.o
+
+ifeq ($(CONFIG_PCI_ROM_RUN),y)
+obj-$(CONFIG_PCI_ROM_RUN) += pci_rom.o
+subdirs-$(CONFIG_PCI_ROM_RUN) += ../../util/x86emu
+else
+obj-$(CONFIG_VGA_ROM_RUN) += pci_rom.o
+subdirs-$(CONFIG_VGA_ROM_RUN) += ../../util/x86emu
+endif
+

Added: trunk/coreboot-v2/src/drivers/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/drivers/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/drivers/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+subdirs-y += pci

Added: trunk/coreboot-v2/src/drivers/pci/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/drivers/pci/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/drivers/pci/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+subdirs-y += onboard

Added: trunk/coreboot-v2/src/drivers/pci/onboard/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/drivers/pci/onboard/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/drivers/pci/onboard/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+obj-y += onboard.o

Added: trunk/coreboot-v2/src/lib/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/lib/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/lib/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,29 @@
+obj-y +=  clog2.o
+obj-y +=  uart8250.o
+obj-y +=  memset.o
+obj-y +=  memcpy.o
+obj-y +=  memcmp.o
+obj-y +=  memmove.o
+obj-y +=  malloc.o
+obj-y +=  delay.o
+obj-y +=  fallback_boot.o
+obj-y +=  compute_ip_checksum.o
+obj-y +=  version.o
+obj-y +=  cbfs.o
+obj-y +=  lzma.o
+#obj-y +=  lzmadecode.o
+
+initobj-y  +=   uart8250.o
+initobj-y  +=   memset.o
+initobj-y  +=   memcpy.o
+initobj-y  +=   memcmp.o
+initobj-y  +=   cbfs.o
+initobj-y  +=   lzma.o
+#initobj-y  +=   lzmadecode.o
+
+obj-$(CONFIG_USBDEBUG_DIRECT)  +=  usbdebug_direct.o
+obj-$(CONFIG_COMPRESSED_PAYLOAD_LZMA)  +=  lzma.o
+
+ifdef POST_EVALUATION
+$(obj)/lib/version.o :: $(obj)/build.h
+endif

Added: trunk/coreboot-v2/src/mainboard/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,343 @@
+
+menu "Mainboard"
+
+choice
+	prompt "Mainboard vendor"
+	default VENDOR_EMULATION
+
+config VENDOR_ATREND
+	bool "A-Trend"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_ABIT
+	bool "ABIT"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_ADVANTECH
+	bool "Advantech"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_AGAMI
+	bool "Agami"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_AMD
+	bool "AMD"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_ARIMA
+	bool "Arima"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_ARTEC
+	bool "Artec Group"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_ASI
+	bool "ASI"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_ASUS
+	bool "ASUS"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_AXUS
+	bool "AXUS"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_AZZA
+	bool "Azza"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_BCOM
+	bool "BCOM"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_BIOSTAR
+	bool "Biostar"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_BROADCOM
+	bool "Broadcom"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_COMPAQ
+	bool "Compaq"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_DELL
+	bool "DELL"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_DIGITALLOGIC
+	bool "Digital Logic"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_EAGLELION
+	bool "Eagle Lion"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_EMBEDDEDPLANET
+	bool "Embedded Planet"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_EMULATION
+	bool "Emulation"
+	help
+	  Select this option for various system emulators, such as QEMU.
+
+config VENDOR_GIGABYTE
+	bool "Gigabyte"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_HP
+	bool "HP"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_IBM
+	bool "IBM"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_IEI
+	bool "IEI"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_INTEL
+	bool "Intel"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_IWILL
+	bool "Iwill"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_JETWAY
+	bool "Jetway"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_KONTRON
+	bool "Kontron"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_LIPPERT
+	bool "Lippert"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_MOTOROLA
+	bool "Motorola"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_MSI
+	bool "MSI"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_NEC
+	bool "NEC"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_NEWISYS
+	bool "Newisys"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_NVIDIA
+	bool "NVidia"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_OLPC
+	bool "OLPC"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_PCENGINES
+	bool "PC Engines"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_RCA
+	bool "RCA"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_SUNW
+	bool "SUN Microsystems"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_SUPERMICRO
+	bool "Supermicro"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_TECHNEXION
+	bool "Technexion"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_THOMSON
+	bool "Thomson"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_TOTALIMPACT
+	bool "Total Impact"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_TYAN
+	bool "Tyan"
+	help
+	  Select this option for systems from the vendor.
+
+config VENDOR_VIA
+	bool "VIA"
+	help
+	  Select this option for systems from the vendor.
+
+endchoice
+
+config MAINBOARD_VENDOR
+        string
+        default "EMULATION"
+        depends on VENDOR_EMULATION
+
+config MAINBOARD_VENDOR
+        string
+        default "KONTRON"
+        depends on VENDOR_KONTRON
+
+config MAINBOARD_VENDOR
+        string
+        default "VIA"
+        depends on VENDOR_VIA
+
+config MAINBOARD_VENDOR
+        string
+        default "AMD"
+        depends on VENDOR_AMD
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1019
+        depends on VENDOR_VIA
+
+source "src/mainboard/a-trend/Kconfig"
+source "src/mainboard/abit/Kconfig"
+source "src/mainboard/advantech/Kconfig"
+source "src/mainboard/amd/Kconfig"
+source "src/mainboard/arima/Kconfig"
+source "src/mainboard/artecgroup/Kconfig"
+source "src/mainboard/asi/Kconfig"
+source "src/mainboard/asus/Kconfig"
+source "src/mainboard/axus/Kconfig"
+source "src/mainboard/azza/Kconfig"
+source "src/mainboard/bcom/Kconfig"
+source "src/mainboard/biostar/Kconfig"
+source "src/mainboard/broadcom/Kconfig"
+source "src/mainboard/compaq/Kconfig"
+source "src/mainboard/dell/Kconfig"
+source "src/mainboard/digitallogic/Kconfig"
+source "src/mainboard/eaglelion/Kconfig"
+source "src/mainboard/embeddedplanet/Kconfig"
+source "src/mainboard/emulation/Kconfig"
+source "src/mainboard/gigabyte/Kconfig"
+source "src/mainboard/hp/Kconfig"
+source "src/mainboard/ibm/Kconfig"
+source "src/mainboard/iei/Kconfig"
+source "src/mainboard/intel/Kconfig"
+source "src/mainboard/iwill/Kconfig"
+source "src/mainboard/jetway/Kconfig"
+source "src/mainboard/kontron/Kconfig"
+source "src/mainboard/lippert/Kconfig"
+source "src/mainboard/motorola/Kconfig"
+source "src/mainboard/msi/Kconfig"
+source "src/mainboard/nec/Kconfig"
+source "src/mainboard/newisys/Kconfig"
+source "src/mainboard/nvidia/Kconfig"
+source "src/mainboard/olpc/Kconfig"
+source "src/mainboard/pcengines/Kconfig"
+source "src/mainboard/rca/Kconfig"
+source "src/mainboard/sunw/Kconfig"
+source "src/mainboard/supermicro/Kconfig"
+source "src/mainboard/technexion/Kconfig"
+source "src/mainboard/technologic/Kconfig"
+source "src/mainboard/televideo/Kconfig"
+source "src/mainboard/thomson/Kconfig"
+source "src/mainboard/totalimpact/Kconfig"
+source "src/mainboard/tyan/Kconfig"
+source "src/mainboard/via/Kconfig"
+
+choice
+	prompt "ROM chip size"
+	default COREBOOT_ROMSIZE_KB_256
+
+config COREBOOT_ROMSIZE_KB_128
+	bool "128 KB"
+	help
+	  Choose this option if you have a 128 KB ROM chip.
+
+config COREBOOT_ROMSIZE_KB_256
+	bool "256 KB"
+	help
+	  Choose this option if you have a 256 KB ROM chip.
+
+config COREBOOT_ROMSIZE_KB_512
+	bool "512 KB"
+	help
+	  Choose this option if you have a 512 KB ROM chip.
+
+config COREBOOT_ROMSIZE_KB_1024
+	bool "1024 KB (1 MB)"
+	help
+	  Choose this option if you have a 1024 KB (1 MB) ROM chip.
+
+config COREBOOT_ROMSIZE_KB_2048
+	bool "2048 KB (2 MB)"
+	help
+	  Choose this option if you have a 2048 KB (2 MB) ROM chip.
+
+endchoice
+
+config COREBOOT_ROMSIZE_KB
+	int
+	default 128 if COREBOOT_ROMSIZE_KB_128
+	default 256 if COREBOOT_ROMSIZE_KB_256
+	default 512 if COREBOOT_ROMSIZE_KB_512
+	default 1024 if COREBOOT_ROMSIZE_KB_1024
+	default 2048 if COREBOOT_ROMSIZE_KB_2048
+	help
+	  Map the config names to an integer.
+
+endmenu
+

Added: trunk/coreboot-v2/src/mainboard/a-trend/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/a-trend/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/a-trend/atc-6240/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,69 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/winbond/w83627hf	# Super I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+            io 0x60 = 0x00
+          end
+          device pnp 3f0.7 on		# Game port / MIDI / GPIO 1
+            io 0x60 = 0x201
+            io 0x62 = 0x330
+            irq 0x70 = 9
+          end
+          device pnp 3f0.8 off		# GPIO 2 / WDT
+          end
+          device pnp 3f0.9 off		# GPIO 3
+          end
+          device pnp 3f0.a off		# ACPI
+          end
+          device pnp 3f0.b off		# HWM (TODO)
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      device pci c.0 on end		# Onboard audio (ES1371)
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/abit/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/abit/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/abit/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/abit/be6-ii_v2_0/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE, UDMA/33 (part of 82371EB)
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      device pci 13.0 on end		# IDE, UDMA/66 (HPT366 controller)
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      register "ide0_drive0_udma33_enable" = "1"
+      register "ide0_drive1_udma33_enable" = "1"
+      register "ide1_drive0_udma33_enable" = "1"
+      register "ide1_drive1_udma33_enable" = "1"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/advantech/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/advantech/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/advantech/pcm-5820/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,56 @@
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 12.0 on		# ISA bridge
+        chip superio/winbond/w83977f	# SUper I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.4 on		# RTC / On-Now control
+            io 0x60 = 0x70
+            irq 0x70 = 8
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# IR
+            # TODO?
+          end
+          device pnp 3f0.7 on		# GPIO 1
+            # TODO?
+          end
+          device pnp 3f0.8 on		# GPIO 2
+            # TODO?
+          end
+        end
+      end
+      device pci 12.1 on end		# SMI
+      device pci 12.2 on end		# IDE
+      device pci 12.3 on end		# Audio (onboard)
+      device pci 12.4 on end		# VGA
+      device pci 13.0 on end		# USB
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/amd/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+source "src/mainboard/amd/serengeti_cheetah/Kconfig"
\ No newline at end of file

Added: trunk/coreboot-v2/src/mainboard/amd/db800/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/db800/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/db800/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,68 @@
+chip northbridge/amd/lx
+	device pci_domain 0 on
+		device pci 1.0 on end				# Northbridge
+		device pci 1.1 on end				# Graphics
+		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
+			register "lpc_serirq_enable" = "0x0000105a"
+			register "lpc_serirq_polarity" = "0x0000EFA5"
+			register "lpc_serirq_mode" = "1"
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0"	# 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "1"	# 0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "0"
+			register "com1_address" = "0x3F8"
+			register "com1_irq" = "4"
+			register "com2_enable" = "0"
+			register "com2_address" = "0x2F8"
+			register "com2_irq" = "3"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+			device pci d.0 on end			# Ethernet
+			device pci e.0 on end			# Slot1
+			device pci f.0 on			# ISA Bridge
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off	# Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.1 off	# Parallel port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.2 on	# Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off end	# Com2
+					device pnp 2e.5 on	# Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6 off end	# CIR
+					device pnp 2e.7 off end	# GAME_MIDI_GIPO1
+					device pnp 2e.8 off end	# GPIO2
+					device pnp 2e.9 off end	# GPIO3
+					device pnp 2e.a off end	# ACPI
+					device pnp 2e.b off end	# HW Monitor
+				end
+			end
+			device pci f.2 on end			# IDE Controller
+			device pci f.3 on end			# Audio
+			device pci f.4 on end			# OHCI
+			device pci f.5 on end			# EHCI
+		end
+	end
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+end
+

Added: trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,117 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_S1G1
+		device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  southbridge
+				chip southbridge/amd/rs690
+					device pci 0.0 on end # HT  	0x7910
+					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
+						chip drivers/pci/onboard
+							device pci 5.0 on end	# Internal Graphics 0x791F
+							register "rom_address" = "0xfff00000"
+						end
+					end
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
+					device pci 3.0 off end # PCIE P2P bridge	0x791b
+					device pci 4.0 on end # PCIE P2P bridge 0x7914
+					device pci 5.0 on end # PCIE P2P bridge 0x7915
+					device pci 6.0 on end # PCIE P2P bridge 0x7916
+					device pci 7.0 on end # PCIE P2P bridge 0x7917
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					register "vga_rom_address" = "0xfff00000"
+					register "gpp_configuration" = "4"
+					register "port_enable" = "0xfc"
+					register "gfx_dev2_dev3" = "1"
+					register "gfx_dual_slot" = "0"
+					register "gfx_lane_reversal" = "0"
+					register "gfx_tmds" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+				end
+				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
+					device pci 12.0 on end # SATA  0x4380
+					device pci 13.0 on end # USB   0x4387
+					device pci 13.1 on end # USB   0x4388
+					device pci 13.2 on end # USB   0x4389
+					device pci 13.3 on end # USB   0x438a
+					device pci 13.4 on end # USB   0x438b
+					device pci 13.5 on end # USB 2 0x4386
+	 				device pci 14.0 on # SM        0x4385
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE    0x438c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on # LPC	0x438d
+						chip superio/ite/it8712f
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.2 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.4 off end #  EC
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 2e.6 on #  Mouse
+								irq 0x70 = 12
+							end
+							device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
+							end
+							device pnp 2e.8 off #  MIDI
+								io 0x60 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.9 off #  GAME
+								io 0x60 = 0x220
+							end
+							device pnp 2e.a off end #  CIR
+						end	#superio/ite/it8712f
+					end		#LPC
+					device pci 14.4 on end # PCI 0x4384
+					device pci 14.5 on end # ACI 0x4382
+					device pci 14.6 on end # MCI 0x438e
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "hda_viddid" = "0x10ec0882"
+				end	#southbridge/amd/sb600
+			end #  device pci 18.0
+
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end		#northbridge/amd/amdk8
+	end #pci_domain
+end		#northbridge/amd/amdk8/root_complex
+

Added: trunk/coreboot-v2/src/mainboard/amd/norwich/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/norwich/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/norwich/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,41 @@
+chip northbridge/amd/lx
+	device pci_domain 0 on
+		device pci 1.0 on end	# Northbridge
+		device pci 1.1 on end	# Graphics
+		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+			register "lpc_serirq_enable" = "0x00001002"
+			register "lpc_serirq_polarity" = "0x0000EFFD"
+			register "lpc_serirq_mode" = "1"
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "0"	#0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "1"
+			register "com1_address" = "0x3F8"
+			register "com1_irq" = "4"
+			register "com2_enable" = "0"
+			register "com2_address" = "0x2F8"
+			register "com2_irq" = "3"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+			device pci b.0 on end	# Slot 3
+			device pci c.0 on end	# Slot 4
+			device pci d.0 on end	# Slot 1
+			device pci e.0 on end	# Slot 2
+			device pci f.0 on end	# ISA Bridge
+			device pci f.2 on end	# IDE Controller
+			device pci f.3 on end	# Audio
+			device pci f.4 on end	# OHCI
+			device pci f.5 on end	# EHCI
+		end
+	end
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+end
+

Added: trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,77 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_AM2
+		device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  southbridge, K8 HT Configuration
+				chip southbridge/amd/rs690
+					device pci 0.0 on end # HT  	0x7910
+				#	device pci 0.1 off end # CLK
+					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
+						chip drivers/pci/onboard
+							device pci 5.0 on end	# Internal Graphics 0x791F
+							register "rom_address" = "0xfff00000"
+						end
+					end
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
+					device pci 3.0 off end # PCIE P2P bridge	0x791b
+					device pci 4.0 on end # PCIE P2P bridge 0x7914
+					device pci 5.0 on end # PCIE P2P bridge 0x7915
+					device pci 6.0 on end # PCIE P2P bridge 0x7916
+					device pci 7.0 on end # PCIE P2P bridge 0x7917
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					register "vga_rom_address" = "0xfff00000"
+					register "gpp_configuration" = "4"
+					register "port_enable" = "0xfc"
+					register "gfx_dev2_dev3" = "1"
+					register "gfx_dual_slot" = "0"
+					register "gfx_lane_reversal" = "0"
+					register "gfx_tmds" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+				end
+				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
+					device pci 12.0 on end # SATA  0x4380
+					device pci 13.0 on end # USB   0x4387
+					device pci 13.1 on end # USB   0x4388
+					device pci 13.2 on end # USB   0x4389
+					device pci 13.3 on end # USB   0x438a
+					device pci 13.4 on end # USB   0x438b
+					device pci 13.5 on end # USB 2 0x4386
+	 				device pci 14.0 on # SM        0x4385
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 off end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 off end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 off end
+						end
+					end # SM
+				device pci 14.1 on end # IDE    0x438c
+				device pci 14.2 on end # HDA    0x4383
+				device pci 14.3 on end # LPC	0x438d
+				device pci 14.4 on end # PCI 0x4384
+				device pci 14.5 on end # ACI 0x4382
+				device pci 14.6 on end # MCI 0x438e
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "hda_viddid" = "0x10ec0882"
+				end	#southbridge/amd/sb600
+			end #  device pci 18.0
+
+			device pci 18.1 on end		# K8 Address Map
+			device pci 18.2 on end		# K8 DRAM Controller and HT Trace Mode
+			device pci 18.3 on end		# K8 Miscellaneous Control
+		end		#northbridge/amd/amdk8
+	end #pci_domain
+end		#northbridge/amd/amdk8/root_complex
+

Added: trunk/coreboot-v2/src/mainboard/amd/rumba/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/rumba/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/rumba/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,21 @@
+chip northbridge/amd/gx2
+	device apic_cluster 0 on
+		chip cpu/amd/model_gx2
+			device apic 0 on end
+		end
+	end
+  	device pci_domain 0 on 
+    		device pci 1.0 on end
+		device pci 1.1 on end
+      		chip southbridge/amd/cs5536
+			register "lpc_serirq_enable" = "0x80"  # enabled with default timing
+        		device pci d.0 on end	# Realtek 8139 LAN
+        		device pci f.0 on end	# ISA Bridge
+        		device pci f.2 on end	# IDE Controller
+        		device pci f.3 on end 	# Audio
+        		device pci f.4 on end	# OHCI
+			device pci f.4 on end	# UHCI
+      		end
+    	end
+end
+

Added: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,49 @@
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_AMD
+
+config BOARD_AMD_SERENGETI_CHEETAH
+	bool "SERENGETI_CHEETAH"
+	select ARCH_X86
+	select CPU_AMD_K8
+	select CPU_AMD_SOCKET_F
+	select NORTHBRIDGE_AMD_AMDK8
+	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	select SOUTHBRIDGE_AMD_AMD8111
+	select SUPERIO_WINBOND_W83627THF
+	select PIRQ_TABLE
+	select MMCONF_SUPPORT
+	select USE_PRINTK_IN_CAR
+	help
+	AMD Serengeti Series mainboards
+endchoice
+
+config MAINBOARD_DIR
+	string
+	default amd/serengeti_cheetah
+	depends on BOARD_AMD_SERENGETI_CHEETAH
+
+#config DCACHE_RAM_BASE
+#	hex
+#	default 0xffdf8000
+#	depends on BOARD_AMD_SERENGETI_CHEETAH
+#	
+#config DCACHE_RAM_SIZE
+#	hex
+#	default 0x8000
+#	depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config LB_CKS_LOC
+	int
+        default 123
+	depends on BOARD_AMD_SERENGETI_CHEETAH
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Serengeti-Cheetah"
+	depends on BOARD_AMD_SERENGETI_CHEETAH

Added: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,95 @@
+##
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+## 
+
+driver-y +=  mainboard.o
+
+#needed by irq_tables and mptable and acpi_tables
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  fadt.o
+
+#./ssdt.o is in northbridge/amd/amdk8/Config.lb
+obj-$(CONFIG_ACPI_SSDTX_NUM) +=  ssdt2.o
+obj-$(CONFIG_ACPI_SSDTX_NUM) +=  ssdt3.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  ssdt4.o
+
+# This is part of the conversion to init-obj and away from included code. 
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=\
+	-DCONFIG_AP_IN_SIPI_WAIT=1 \
+	-DCONFIG_USE_PRINTK_IN_CAR=1 \
+	-DCONFIG_HAVE_HIGH_TABLES=1 \
+	-DCONFIG_MMCONF_SUPPORT=1 \
+	-DCONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+	iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+	perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+	mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+	iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+	perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+	mv pci3.hex ssdt3.c
+           
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+	iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+	perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+	mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+

Added: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,159 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  northbridge 
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/amd/amd8132
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	        			device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+                	        			device pnp 2e.8 off end #  GPIO2
+                	        			device pnp 2e.9 off end #  GPIO3
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on
+                                                chip drivers/i2c/i2cmux # pca9556 smbus mux
+                                                        device i2c 18 on #0 pca9516 1
+                                                                chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                        end
+                                                        device i2c 18 on #1 pca9516 2
+                                                                chip drivers/generic/generic #dimm 1-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-2-0
+                                                                        device i2c 54 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-2-1
+                                                                        device i2c 55 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-3-0
+                                                                        device i2c 56 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-3-1
+                                                                        device i2c 57 on end
+                                                                end
+                                                        end
+						end
+					end # acpi
+					device pci 1.5 off end
+					device pci 1.6 off end
+                	                register "ide0_enable" = "1"
+                	                register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0
+
+                        device pci 18.0 on end
+                        device pci 18.0 on end  
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+                chip northbridge/amd/amdk8
+                        device pci 19.0 on #  northbridge
+                                chip southbridge/amd/amd8151
+                                        # the on/off keyword is mandatory
+                                        device pci 0.0 on end
+                                        device pci 1.0 on end
+                                end
+                        end #  device pci 19.0
+
+                        device pci 19.0 on end
+                        device pci 19.0 on end
+                        device pci 19.1 on end
+                        device pci 19.2 on end
+                        device pci 19.3 on end
+                end
+
+
+	end #pci_domain
+#        chip drivers/generic/debug
+#        	device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 off end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 off end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#                device pnp 0.7 off end # tsc
+#       end
+
+end
+
+

Added: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,152 @@
+chip northbridge/amd/amdfam10/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_F_1207  #L1 and DDR2
+			 device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdfam10
+			device pci 18.0 on #  northbridge
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/amd/amd8132
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.3 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+							device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.8 off end #  GPIO2
+							device pnp 2e.9 off end #  GPIO3
+							device pnp 2e.a off end #  ACPI
+							device pnp 2e.b on #  HW Monitor
+								io 0x60 = 0x290
+								irq 0x70 = 5
+							end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on
+						chip drivers/i2c/i2cmux2 # pca9556 smbus mux
+						chip drivers/i2c/i2cmux2 # pca9556 smbus mux
+							device i2c 18 on #0 pca9516 1
+								chip drivers/generic/generic #dimm 0-0-0
+									device i2c 50 on end
+								end
+								chip drivers/generic/generic #dimm 0-0-1
+									device i2c 51 on end
+								end
+								chip drivers/generic/generic #dimm 0-1-0
+									device i2c 52 on end
+								end
+								chip drivers/generic/generic #dimm 0-1-1
+									device i2c 53 on end
+								end
+							end
+							device i2c 18 on #1 pca9516 2
+								chip drivers/generic/generic #dimm 1-0-0
+									device i2c 50 on end
+								end
+								chip drivers/generic/generic #dimm 1-0-1
+									device i2c 51 on end
+								end
+								chip drivers/generic/generic #dimm 1-1-0
+									device i2c 52 on end
+								end
+								chip drivers/generic/generic #dimm 1-1-1
+									device i2c 53 on end
+								end
+							end
+						end
+						end
+					end # acpi
+					device pci 1.5 off end
+					device pci 1.6 off end
+					register "ide0_enable" = "1"
+					register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0
+
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+#			device pci 00.5 on end
+		end
+	end #pci_domain
+	#for node 32 to node 63
+#	device pci_domain 0 on
+#		chip northbridge/amd/amdfam10
+#			  device pci 00.0 on end#  northbridge
+#			  device pci 00.0 on end
+#			  device pci 00.0 on end
+#			  device pci 00.0 on end
+#			  device pci 00.1 on end
+#			  device pci 00.2 on end
+#			  device pci 00.3 on end
+#			  device pci 00.4 on end
+#			 device pci 00.5 on end
+#		end
+#	end #pci_domain
+
+#	  chip drivers/generic/debug
+#		 device pnp 0.0 off end # chip name
+#		  device pnp 0.1 on end # pci_regs_all
+#		  device pnp 0.2 off end # mem
+#		  device pnp 0.3 off end # cpuid
+#		  device pnp 0.4 off end # smbus_regs_all
+#		  device pnp 0.5 off end # dual core msr
+#		  device pnp 0.6 off end # cache size
+#		  device pnp 0.7 off end # tsc
+#		  device pnp 0.8 off end # hard reset
+#		  device pnp 0.9 off end # mcp55
+#		  device pnp 0.a on end # GH ext table
+#	 end
+
+end
+
+

Added: trunk/coreboot-v2/src/mainboard/arima/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/arima/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/arima/hdama/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,196 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  northbridge 
+				#  devices on link 0, link 0 == LDT 0 
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+					device pci 0.0 on	# PCIX bridge
+						## On board NIC A
+						#chip drivers/generic/generic
+						#	device pci 3.0 on	
+						#		irq 0 = 0x13
+						#	end
+						#end
+						## On board NIC B
+						#chip drivers/generic/generic
+						#	device pci 4.0 on
+						#		irq 0 = 0x13
+						#	end
+						#end
+						## PCI Slot 3
+						#chip drivers/generic/generic
+						#	device pci 1.0 on
+						#		irq 0 = 0x11
+						#		irq 1 = 0x12
+						#		irq 2 = 0x13
+						#		irq 3 = 0x10
+						#	end
+						#end 
+						## PCI Slot 4
+						#chip drivers/generic/generic
+						#	device pci 2.0 on
+						#		irq 0 = 0x12
+						#		irq 1 = 0x13
+						#		irq 2 = 0x10
+						#		irq 3 = 0x11
+						#	end
+						#end 
+					end
+					device pci 0.1 on end	# IOAPIC
+					device pci 1.0 on 	# PCIX bridge
+						## PCI Slot 1
+						#chip drivers/generic/generic
+						#	device pci 1.0 on
+						#		irq 0 = 0x11
+						#		irq 1 = 0x12
+						#		irq 2 = 0x13
+						#		irq 3 = 0x10
+						#	end
+						#end
+						## PCI Slot 2
+						#chip drivers/generic/generic
+						#	device pci 2.0 on
+						#		irq 0 = 0x12
+						#		irq 1 = 0x13
+						#		irq 2 = 0x10
+						#		irq 3 = 0x11
+						#	end
+						#end 
+					end
+					device pci 1.1 on end	# IOAPIC
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent of the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on  end	# USB0
+						device pci 0.1 on  end	# USB1
+						device pci 0.2 off end	# USB 2.0
+						device pci 1.0 off end	# LAN
+						chip drivers/pci/onboard
+							device pci 6.0 on end # ATI Rage XL
+							register "rom_address" = "0xfff80000"
+						end
+						## PCI Slot 5 (correct?)
+						#chip drivers/generic/generic
+						#	device pci 5.0 on
+						#		irq 0 = 0x11
+						#		irq 1 = 0x12
+						#		irq 2 = 0x13
+						#		irq 3 = 0x10
+						#	end
+						#end 
+						## PCI Slot 6 (correct?)
+						#chip drivers/generic/generic
+						#	device pci 4.0 on
+						#		irq 0 = 0x10
+						#		irq 1 = 0x11
+						#		irq 2 = 0x12
+						#		irq 3 = 0x13
+						#	end
+						#end 
+
+					end
+					# LPC bridge
+					device pci 1.0 on
+						chip superio/nsc/pc87360
+							device	pnp 2e.0 off  # Floppy 
+								 io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off  # Parallel Port
+								 io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 off # Com 2
+								 io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 on  # Com 1
+								 io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.4 off end # SWC
+							device pnp 2e.5 off end # Mouse
+							device pnp 2e.6 on  # Keyboard
+								 io 0x60 = 0x60
+								 io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 2e.7 off end # GPIO
+							device pnp 2e.8 off end # ACB
+							device pnp 2e.9 off end # FSCM
+							device pnp 2e.a off end # WDT  
+						end
+					end
+					device pci 1.1 on end	# IDE
+					device pci 1.2 on end	# SMBus 2.0
+					device pci 1.3 on 	# System Management
+						chip drivers/generic/generic
+							#phillips pca9545 smbus mux
+							device i2c 70 on 
+								# analog_devices adm1026	
+								chip drivers/generic/generic
+									device i2c 2c on end
+								end
+							end
+							device i2c 70 on end
+							device i2c 70 on end
+							device i2c 70 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end 
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end 
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end 
+						chip drivers/generic/generic #dimm 1-0-0
+							device i2c 54 on end 
+						end
+						chip drivers/generic/generic #dimm 1-0-1
+							device i2c 55 on end
+						end 
+						chip drivers/generic/generic #dimm 1-1-0
+							device i2c 56 on end
+						end 
+						chip drivers/generic/generic #dimm 1-1-1
+							device i2c 57 on end
+						end 
+					end
+					device pci 1.5 off end	# AC97 Audio
+					device pci 1.6 on  end	# AC97 Modem
+					register "ide0_enable" = "1"
+					register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0 
+			
+			device pci 18.0 on end # LDT1
+			device pci 18.0 on end # LDT2
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end  # chip northbridge/amd/amdk8
+		chip northbridge/amd/amdk8
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.1 on end
+			device pci 19.2 on end
+			device pci 19.3 on end
+		end
+	end 
+end
+

Added: trunk/coreboot-v2/src/mainboard/artecgroup/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/artecgroup/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/artecgroup/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,42 @@
+chip northbridge/amd/lx
+	device pci_domain 0 on
+		device pci 1.0 on end	# Northbridge
+		device pci 1.1 on end	# Graphics
+		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+			register "lpc_serirq_enable" = "0x00001002"
+			register "lpc_serirq_polarity" = "0x0000EFFD"
+			register "lpc_serirq_mode" = "1"
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "0"	#0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "0"
+			register "com1_address" = "0x2F8"
+			register "com1_irq" = "3"
+			register "com2_enable" = "1"
+			register "com2_address" = "0x3F8"
+			register "com2_irq" = "4"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+			device pci b.0 on end	# Slot 3
+			device pci c.0 on end	# Slot 4
+			device pci d.0 on end	# Slot 1
+			device pci e.0 on end	# Slot 2
+			device pci f.0 on end	# ISA Bridge
+			device pci f.2 on end	# IDE Controller
+			device pci f.3 on end	# Audio
+			device pci f.4 on end	# OHCI
+			device pci f.5 on end	# EHCI
+		end
+	end
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+
+end
+

Added: trunk/coreboot-v2/src/mainboard/asi/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blgp/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,55 @@
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 0f.0 on end		# Ethernet
+      device pci 12.0 on		# ISA bridge
+        chip superio/nsc/pc87351	# Super I/O
+          device pnp 2e.0 off		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.2 on		# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.e on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.4 on		# System wake-up control (SWC)
+            irq 0x60 = 0x500
+          end
+          device pnp 2e.5 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.6 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.7 on		# GPIO
+            irq 0x60 = 0x800
+          end
+          device pnp 2e.8 on		# Fan speed control
+            irq 0x60 = 0x900
+          end
+        end
+      end
+      device pci 12.1 off end		# SMI
+      device pci 12.2 on end		# IDE
+      device pci 12.3 on end		# Audio
+      device pci 12.4 on end		# VGA
+      device pci 13.0 on end		# USB
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "0"	# No connector on this board
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asi/mb_5blmp/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,56 @@
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 0f.0 off end		# Ethernet (Realtek RTL8139B)
+      device pci 12.0 on		# ISA bridge
+        chip superio/nsc/pc87351	# Super I/O
+          device pnp 2e.4 on		# PS/2 keyboard (+ mouse?)
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+            # irq 0x72 = 12
+          end
+          device pnp 2e.a on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.e on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.f off		# Floppy
+            io 0x60 = 0x3f2
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.10 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.12 on		# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+        end
+      end
+      device pci 12.1 off end		# SMI
+      device pci 12.2 on  end		# IDE
+      device pci 12.3 on  end		# Audio
+      device pci 12.4 on  end		# VGA (onboard)
+      # device pci 12.4 on		# VGA (onboard)
+      #   chip drivers/pci/onboard
+      #     device pci 12.4 on end
+      #     register "rom_address" = "0xfffc0000" # 256 KB image
+      #     # register "rom_address" = "0xfff80000" # 512 KB image
+      #     # register "rom_address" = "0xfff00000" # 1 MB image
+      #   end
+      # end
+      device pci 13.0 on end		# USB
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end
+

Added: trunk/coreboot-v2/src/mainboard/asus/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asus/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/asus/a8n_e/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,130 @@
+chip northbridge/amd/amdk8/root_complex		# Root complex
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/amd/socket_939			# Socket 939 CPU
+      device apic 0 on end			# APIC
+    end
+  end
+
+  device pci_domain 0 on			# PCI domain
+    chip northbridge/amd/amdk8			# mc0
+      device pci 18.0 on			# Northbridge
+        # Devices on link 0, link 0 == LDT 0
+        chip southbridge/nvidia/ck804		# Southbridge
+          device pci 0.0 on end			# HT
+          device pci 1.0 on			# LPC
+            chip superio/ite/it8712f		# Super I/O
+              device pnp 2e.0 on		# Floppy
+                io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 on		# Com1
+                io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.2 off		# Com2 (N/A on this board)
+                io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 2e.3 on		# Parallel port
+                io 0x60 = 0x378
+                irq 0x70 = 7
+                drq 0x74 = 3
+              end
+              device pnp 2e.4 on		# Environment controller
+                io 0x60 = 0x290
+                io 0x62 = 0x0000
+                irq 0x70 = 0x00
+              end
+              device pnp 2e.5 on		# PS/2 keyboard
+                io 0x60 = 0x60
+                io 0x62 = 0x64
+                irq 0x70 = 1
+                irq 0x71 = 2
+              end
+              device pnp 2e.6 on		# PS/2 mouse
+                irq 0x70 = 12
+                irq 0x71 = 2
+              end
+              device pnp 2e.7 on		# GPIO config
+                io 0x60 = 0x0800
+                # Set GPIO 1 & 2
+                io 0x25 = 0x0000
+                # Set GPIO 3 & 4
+                io 0x27 = 0x2540
+                # GPIO Polarity for Set 3
+                io 0xb2 = 0x2100
+                # GPIO Pin Internal Pull up for Set 3
+                io 0xba = 0x0100
+                # Simple I/O register config
+                io 0xc0 = 0x0000
+                io 0xc2 = 0x2540
+                io 0xc8 = 0x0000
+                io 0xca = 0x0500
+              end
+              device pnp 2e.8 on		# Midi port
+                io 0x60 = 0x300
+                irq 0x70 = 10
+              end
+              device pnp 2e.9 on		# Game port
+                io 0x60 = 0x201
+              end
+              device pnp 2e.a off		# IR (N/A on this board)
+                io 0x60 = 0x310
+                irq 0x70 = 11
+              end
+            end
+          end
+          device pci 1.1 on			# SM 0
+            # chip drivers/generic/generic #dimm 0-0-0
+            #   device i2c 50 on end
+            # end
+            # chip drivers/generic/generic #dimm 0-0-1
+            #   device i2c 51 on end
+            # end
+            # chip drivers/generic/generic #dimm 0-1-0
+            #   device i2c 52 on end
+            # end
+            # chip drivers/generic/generic #dimm 0-1-1
+            #   device i2c 53 on end
+            # end
+            # chip drivers/generic/generic #dimm 1-0-0
+            #   device i2c 54 on end
+            # end
+            # chip drivers/generic/generic #dimm 1-0-1
+            #   device i2c 55 on end
+            # end
+            # chip drivers/generic/generic #dimm 1-1-0
+            #   device i2c 56 on end
+            # end
+            # chip drivers/generic/generic #dimm 1-1-1
+            #   device i2c 57 on end
+            # end
+          end
+          device pci 2.0 on end			# USB 1.1
+          device pci 2.1 on end			# USB 2
+          device pci 4.0 on end			# Onboard audio (ACI)
+          device pci 4.1 off end		# Onboard modem (MCI), N/A
+          device pci 6.0 on end			# IDE
+          device pci 7.0 on end			# SATA 1
+          device pci 8.0 on end			# SATA 0
+          device pci 9.0 on end			# PCI
+          device pci a.0 on end			# NIC
+          device pci b.0 on end			# PCI E 3
+          device pci c.0 on end			# PCI E 2
+          device pci d.0 on end			# PCI E 1
+          device pci e.0 on end			# PCI E 0
+          register "ide0_enable" = "1"
+          register "ide1_enable" = "1"
+          register "sata0_enable" = "1"
+          register "sata1_enable" = "1"
+          # register "mac_eeprom_smbus" = "3"
+          # register "mac_eeprom_addr" = "0x51"
+        end
+      end
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,96 @@
+chip northbridge/amd/amdk8/root_complex		# Root complex
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/amd/socket_939			# CPU
+      device apic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on			# PCI domain
+    chip northbridge/amd/amdk8			# mc0
+      device pci 18.0 on			# Northbridge
+        # Devices on link 0, link 0 == LDT 0
+        chip southbridge/via/vt8237r		# Southbridge
+          register "ide0_enable" = "1"		# Enable IDE channel 0
+          register "ide1_enable" = "1"		# Enable IDE channel 1
+          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
+          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
+          register "fn_ctrl_lo" = "0"		# Enable SB functions
+          register "fn_ctrl_hi" = "0xad"	# Enable SB functions
+          device pci 0.0 on end			# HT
+          device pci f.1 on end			# IDE
+          device pci 11.0 on			# LPC
+            chip drivers/generic/generic	# DIMM 0-0-0
+              device i2c 50 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-0-1
+              device i2c 51 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-0
+              device i2c 52 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-1
+              device i2c 53 on end
+            end
+            chip superio/winbond/w83627ehg	# Super I/O
+              device pnp 2e.0 on		# Floppy
+                io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 on		# Parallel port
+                io 0x60 = 0x378
+                irq 0x70 = 7
+                drq 0x74 = 3
+              end
+              device pnp 2e.2 on		# Com1
+                io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.3 off		# Com2 (N/A on this board)
+                io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 2e.5 off		# PS/2 keyboard (off)
+              end
+              device pnp 2e.106 off		# Serial flash
+                io 0x60 = 0x100
+              end
+              device pnp 2e.007 off		# GPIO 1
+              end
+              device pnp 2e.107 on		# Game port
+                io 0x60 = 0x201
+              end
+              device pnp 2e.207 on		# MIDI
+                io 0x62 = 0x330
+                irq 0x70 = 0xa
+              end
+              device pnp 2e.307 off		# GPIO 6
+              end
+              device pnp 2e.8 off		# WDTO_PLED
+              end
+              device pnp 2e.009 on		# GPIO 2 on LDN 9 is in sio_setup
+              end
+              device pnp 2e.109 off		# GPIO 3
+              end
+              device pnp 2e.209 off		# GPIO 4
+              end
+              device pnp 2e.309 on		# GPIO5
+              end
+              device pnp 2e.a off		# ACPI
+              end
+              device pnp 2e.b on		# Hardware monitor
+                io 0x60 = 0x290
+                irq 0x70 = 0
+              end
+            end
+          end
+          device pci 12.0 off end		# VIA LAN (off, other chip used)
+        end
+        chip southbridge/via/k8t890		# "Southbridge" K8T890
+        end
+      end
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,76 @@
+chip northbridge/amd/amdk8/root_complex		# Root complex
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/amd/socket_AM2			# CPU
+      device apic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on			# PCI domain
+    chip northbridge/amd/amdk8			# mc0
+      device pci 18.0 on			# Northbridge
+        # Devices on link 0, link 0 == LDT 0
+        chip southbridge/via/vt8237r		# Southbridge
+          register "ide0_enable" = "1"		# Enable IDE channel 0
+          register "ide1_enable" = "1"		# Enable IDE channel 1
+          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
+          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
+          register "fn_ctrl_lo" = "0xc0"	# Enable SB functions
+          register "fn_ctrl_hi" = "0x1d"	# Enable SB functions
+          device pci 0.0 on end			# HT
+          device pci f.1 on end			# IDE
+          device pci 11.0 on			# LPC
+            chip drivers/generic/generic	# DIMM 0-0-0
+              device i2c 50 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-0-1
+              device i2c 51 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-0
+              device i2c 52 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-1
+              device i2c 53 on end
+            end
+            chip superio/ite/it8712f		# Super I/O
+              device pnp 2e.0 on		# Floppy
+                io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 on		# Com1
+                io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.2 off		# Com2
+                io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 2e.3 on		# Parallel port
+                io 0x60 = 0x378
+                irq 0x70 = 7
+              end
+              device pnp 2e.4 on		# Environment controller
+                io 0x60 = 0x290
+                io 0x62 = 0x230
+                irq 0x70 = 0x00
+              end
+              device pnp 2e.5 off end		# PS/2 keyboard
+              device pnp 2e.6 off end		# PS/2 mouse
+              device pnp 2e.7 off end		# GPIO config
+              device pnp 2e.8 off end		# Midi port
+              device pnp 2e.9 off end		# Game port
+              device pnp 2e.a off end		# IR
+	     end
+	   end
+          device pci 12.0 on end		# VIA LAN
+          device pci 13.0 on end		# br
+          device pci 13.1 on end		# br2 need to have it here to discover it
+        end
+        chip southbridge/via/k8t890		# "Southbridge" K8M890
+        end
+      end
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/asus/mew-am/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-am/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-am/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,60 @@
+chip northbridge/intel/i82810		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/socket_PGA370	# CPU
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Graphics Memory Controller Hub (GMCH)
+    device pci 1.0 on end		# Chipset Graphics Controller (CGC)
+    chip southbridge/intel/i82801xx	# Southbridge
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
+      device pci 1e.0 on end		# PCI bridge
+      device pci 1f.0 on		# ISA bridge
+        chip superio/smsc/smscsuperio	# Super I/O
+          device pnp 2e.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.3 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 4
+          end
+          device pnp 2e.4 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.5 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.7 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 2e.9 on		# Game port
+            io 0x60 = 0x201
+          end
+          device pnp 2e.a on		# Power-management events (PME)
+            io 0x60 = 0x600
+          end
+          device pnp 2e.b on		# MIDI port (MPU-401)
+            io 0x60 = 0x330
+            irq 0x70 = 5
+          end
+        end
+      end
+      device pci 1f.1 on end		# IDE
+      device pci 1f.2 on end		# USB
+      device pci 1f.3 on end		# SMbus
+      device pci 1f.5 off end		# AC'97 audio (N/A, uses CS4280 chip)
+      device pci 1f.6 off end		# AC'97 modem (N/A)
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/asus/mew-vm/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/mew-vm/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asus/mew-vm/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,58 @@
+chip northbridge/intel/i82810
+	device pci_domain 0 on 
+		device pci 0.0 on end # Host bridge
+		device pci 1.0 on # Onboard Video
+			#chip drivers/pci/onboard
+			#	device pci 1.0 on end
+			#	register "rom_address" = "0xfff80000"
+		        #end
+		end
+		chip southbridge/intel/i82801xx # Southbridge
+      			register "ide0_enable" = "1"
+      			register "ide1_enable" = "1"
+
+			device pci 1e.0 on # PCI Bridge
+				#chip drivers/pci/onboard
+				#	device pci 1.0 on end
+				#	register "rom_address" = "0xfff80000"
+			        #end
+			end
+			device pci 1f.0 on  # ISA/LPC? Bridge
+				chip superio/smsc/lpc47b272
+					device pnp 2e.0 off # Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.3 off # Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.4 on # Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.5 off # Com2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.7 on # Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1 # Keyboard interrupt
+						irq 0x72 = 12 # Mouse interrupt
+					end
+					device pnp 2e.a off end # ACPI
+				end
+			end
+			device pci 1f.1 on end # IDE
+			device pci 1f.2 on end # USB
+			device pci 1f.3 on end # SMBus
+			device pci 1f.5 off end # AC'97, no header on MEW-VM
+			device pci 1f.6 off end # AC'97 Modem (MC'97)
+		end
+	end
+	chip cpu/intel/socket_PGA370
+	end
+end
+

Added: trunk/coreboot-v2/src/mainboard/asus/p2b/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 4.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.9 on		# GPIO 3
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 4.1 on	end		# IDE
+      device pci 4.2 on	end		# USB
+      device pci 4.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/asus/p2b-d/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-d/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-d/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,62 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 1 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 4.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.9 on		# GPIO 3
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 4.1 on	end		# IDE
+      device pci 4.2 on	end		# USB
+      device pci 4.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "1"
+      register "ide0_drive1_udma33_enable" = "1"
+      register "ide1_drive0_udma33_enable" = "1"
+      register "ide1_drive1_udma33_enable" = "1"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/asus/p2b-ds/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-ds/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-ds/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,63 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 1 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 4.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.9 on		# GPIO 3
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 4.1 on	end		# IDE
+      device pci 4.2 on	end		# USB
+      device pci 4.3 on end		# ACPI
+      device pci 6.0 on end		# Onboard SCSI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "1"
+      register "ide0_drive1_udma33_enable" = "1"
+      register "ide1_drive0_udma33_enable" = "1"
+      register "ide1_drive1_udma33_enable" = "1"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/asus/p2b-f/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p2b-f/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asus/p2b-f/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 4.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 4.1 on	end		# IDE
+      device pci 4.2 on	end		# USB
+      device pci 4.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/asus/p3b-f/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/p3b-f/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/asus/p3b-f/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 4.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 4.1 on	end		# IDE
+      device pci 4.2 on	end		# USB
+      device pci 4.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/axus/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/axus/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/axus/tc320/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/axus/tc320/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/axus/tc320/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,55 @@
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 12.0 on		# ISA bridge
+        chip superio/nsc/pc97317	# Super I/O
+          device pnp 2e.0 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.1 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.2 on		# RTC, advanced power control (APC)
+            io 0x60 = 0x70
+            irq 0x70 = 8
+          end
+          device pnp 2e.3 off		# Floppy (N/A on this board)
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.4 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.5 off		# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.6 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.7 on		# GPIO
+            io 0x60 = 0xe0
+          end
+          device pnp 2e.8 on		# Power management
+            io 0x60 = 0xe800
+          end
+        end
+      end
+      device pci 12.1 off end		# SMI
+      device pci 12.2 off end		# IDE
+      device pci 12.3 on end		# Audio
+      device pci 12.4 on end		# VGA (onboard)
+      device pci 13.0 on end		# USB
+      # register "ide0_enable" = "1"
+      # register "ide1_enable" = "1"
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/azza/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/azza/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/azza/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/azza/pt-6ibd/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,59 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.6 on		# Consumer IR
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/bcom/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/bcom/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/bcom/winnet100/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnet100/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnet100/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,56 @@
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 0f.0 on end		# Ethernet (onboard)
+      device pci 12.0 on		# ISA bridge
+        chip superio/nsc/pc97317	# Super I/O
+          device pnp 2e.0 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.1 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.2 on		# RTC, Advanced power control (APC)
+            io 0x60 = 0x70
+            irq 0x70 = 8
+          end
+          device pnp 2e.3 off		# Floppy (N/A on this board)
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.4 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.5 on		# COM2 (used for smartcard reader)
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.6 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.7 on		# GPIO
+            io 0x60 = 0xe0
+          end
+          device pnp 2e.8 on		# Power management
+            io 0x60 = 0xe8
+          end
+        end
+      end
+      device pci 12.1 off end		# SMI
+      device pci 12.2 on end		# IDE
+      device pci 12.3 on end		# Audio
+      device pci 12.4 on end		# VGA (onboard)
+      device pci 13.0 on end		# USB
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "0"	# Not available/needed on this board
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/bcom/winnetp680/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/bcom/winnetp680/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/bcom/winnetp680/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,64 @@
+chip northbridge/via/cn700			# Northbridge
+  device pci_domain 0 on			# PCI domain
+    device pci 0.0 on end			# AGP Bridge
+    device pci 0.1 on end			# Error Reporting
+    device pci 0.2 on end			# Host Bus Control
+    device pci 0.3 on end			# Memory Controller
+    device pci 0.4 on end			# Power Management
+    device pci 0.7 on end			# V-Link Controller
+    device pci 1.0 on end			# PCI Bridge
+    chip southbridge/via/vt8237r		# Southbridge
+      # Enable both IDE channels.
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      # Both cables are 40pin.
+      register "ide0_80pin_cable" = "0"
+      register "ide1_80pin_cable" = "0"
+      register "fn_ctrl_lo" = "0x80"
+      register "fn_ctrl_hi" = "0x1d"
+      device pci f.0 on end			# IDE
+      device pci 10.0 on end			# UHCI
+      device pci 10.1 on end			# UHCI
+      device pci 10.2 on end			# UHCI
+      device pci 10.3 on end			# UHCI
+      device pci 10.4 on end			# EHCI
+      device pci 11.0 on			# Southbridge LPC
+        chip superio/winbond/w83697hf		# Super I/O
+          device pnp 2e.0 off			# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on			# Parallel Port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 2e.2 on			# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.3 on			# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.6 off end		# Consumer IR
+          device pnp 2e.7 off end		# Game port, GPIO 1
+          device pnp 2e.8 off end		# MIDI port, GPIO 5
+          device pnp 2e.9 off end		# GPIO 2-4
+          device pnp 2e.a off end		# ACPI
+          device pnp 2e.b on			# HWM
+            io 0x60 = 0x290
+          end
+        end
+      end
+      device pci 11.5 on end			# AC'97 audio
+      device pci 12.0 on end			# Ethernet
+    end
+  end
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/via/model_c7			# VIA C7
+      device apic 0 on end			# APIC
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/biostar/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/biostar/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/biostar/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/biostar/m6tba/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/biostar/m6tba/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/biostar/m6tba/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,53 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/smsc/smscsuperio	# Super I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.3 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.4 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.5 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.7 on		# PS/2 keyboard / mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.8 on		# Aux I/O
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/broadcom/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/broadcom/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/broadcom/blast/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,148 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_940
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  northbridge 
+                              #  devices on link 0
+                                chip southbridge/broadcom/bcm5780 # HT2000
+                                        device pci 0.0 on end   # PXB 1 0x0130
+                                        device pci 1.0 on       # PXB 2 0x0130
+                                                device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
+                                                device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
+                                        end
+                                        device pci 2.0 on end # PCI E 1  #0x0132
+                                        device pci 3.0 on end # PCI E 2
+                                        device pci 4.0 on end # PCI E 3
+                                        device pci 5.0 on end # PCI E 4
+                                end
+                                chip southbridge/broadcom/bcm5785 # HT1000
+                                        device pci 0.0 on  # HT PXB  0x0036
+                                                device pci d.0 on end # PPBX 0x0104
+                                                device pci e.0 on end # SATA 0x024a
+                                        end
+                                        device pci 1.0 on # Legacy  pci main  0x0205
+                                                chip drivers/i2c/i2cmux2 # pca9554 smbus mux
+                                                        device i2c 71 on end #0 pca9554 0
+							device i2c 71 on end #0 pca9554 1
+							device i2c 71 on end #0 pca9554 2
+							device i2c 71 on end #0 pca9554 3
+							device i2c 71 on end #0 pca9554 4
+							device i2c 71 on end #0 pca9554 5
+                                                        device i2c 71 on #0 pca9554 6
+                                                                chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                        end
+                                                        device i2c 71 on #1 pca9554 7
+                                                                chip drivers/generic/generic #dimm 1-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 1-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                        end
+                                                end
+
+					end
+                                        device pci 1.1 on end # IDE        0x0214
+                                        device pci 1.2 on     # LPC        0x0234
+                                                chip superio/nsc/pc87417
+                                                        device  pnp 2e.0 off  # Floppy
+                                                                 io 0x60 = 0x3f0
+                                                                irq 0x70 = 6
+                                                                drq 0x74 = 2
+                                                        end
+                                                        device pnp 2e.1 off  # Parallel Port
+                                                                 io 0x60 = 0x378
+                                                                irq 0x70 = 7
+                                                        end
+                                                        device pnp 2e.2 off # Com 2
+                                                                 io 0x60 = 0x2f8
+                                                                irq 0x70 = 3
+                                                        end
+                                                        device pnp 2e.3 on  # Com 1
+                                                                 io 0x60 = 0x3f8
+                                                                irq 0x70 = 4
+                                                        end
+                                                        device pnp 2e.4 off end # SWC
+                                                        device pnp 2e.5 off end # Mouse
+                                                        device pnp 2e.6 on  # Keyboard
+                                                                 io 0x60 = 0x60
+                                                                 io 0x62 = 0x64
+                                                                irq 0x70 = 1
+                                                        end
+                                                        device pnp 2e.7 off end # GPIO
+                                                        device pnp 2e.f off end # XBUS
+                                                        device pnp 2e.10 on #RTC
+								 io 0x60 = 0x70
+								 io 0x62 = 0x72
+							end 
+                                                end
+                                        end
+                                        device pci 1.3 on end # WDTimer    0x0238
+                                        device pci 1.4 on end # XIOAPIC0   0x0235
+                                        device pci 1.5 on end # XIOAPIC1
+                                        device pci 1.6 on end # XIOAPIC2
+                                        device pci 2.0 on end # USB        0x0223
+                                        device pci 2.1 on end # USB
+                                        device pci 2.2 on end # USB
+                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,),
+                                        chip drivers/pci/onboard
+                                              device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
+                                                                    # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
+                                              register "rom_address" = "0xfff80000"
+                                        end
+                                end
+                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
+#                                        chip drivers/pci/onboard
+#                                              device pci 0.0 on end # fake, will be disabled
+#                                        end
+#                                        chip drivers/pci/onboard
+#                                              device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
+#                                              register "rom_address" = "0xfff80000"
+#                                        end
+
+
+			end #  device pci 18.0
+
+                        device pci 18.0 on end
+                        device pci 18.0 on end  
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+
+
+	end #pci_domain
+#        chip drivers/generic/debug
+#                device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 off end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 off end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#                device pnp 0.7 off end # tsc
+#       end
+
+end
+

Added: trunk/coreboot-v2/src/mainboard/compaq/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/compaq/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/compaq/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/compaq/deskpro_en_sff_p600/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,63 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    device pci a.0 on end		# NIC (onboard)
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 14.0 on		# ISA bridge
+        # chip superio/nsc/pc97307	# Super I/O
+        chip superio/nsc/pc97317	# Super I/O (FIXME: Should be PC97307!)
+          device pnp 15c.0 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 15c.1 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 15c.2 on		# RTC, APC
+            io 0x60 = 0x70
+            irq 0x70 = 8
+          end
+          device pnp 15c.3 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 15c.4 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 15c.5 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 15c.6 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 15c.7 on		# GPIO 1
+          end
+          device pnp 15c.8 on		# Power management
+          end
+        end
+      end
+      device pci 14.1 on end		# IDE
+      device pci 14.2 on end		# USB
+      device pci 14.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/dell/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/dell/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/dell/s1850/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/dell/s1850/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/dell/s1850/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,71 @@
+chip northbridge/intel/e7520 # mch
+	device pci_domain 0 on 
+		chip southbridge/intel/i82801er # i82801er
+			# USB ports
+			device pci 1d.0 on end
+			device pci 1d.1 on end
+			device pci 1d.2 on end 
+			device pci 1d.3 on end
+			device pci 1d.7 on end
+		
+			# -> Bridge
+			device pci 1e.0 on end
+		
+			# -> ISA
+			device pci 1f.0 on 
+				chip superio/nsc/pc8374
+					device pnp 2e.0 off end
+					device pnp 2e.1 off end
+					device pnp 2e.2 off end
+					device pnp 2e.3 on 
+						 io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.4 off end
+					device pnp 2e.5 off end
+					device pnp 2e.6 off end
+					device pnp 2e.7 off end
+					device pnp 2e.8 off end
+				end
+			end
+			# -> IDE
+			device pci 1f.1 on end
+			# -> SATA 
+			device pci 1f.2 on end
+			device pci 1f.3 on end
+
+			register "pirq_a_d" = "0x8a07030b"
+			register "pirq_e_h" = "0x85808080"
+		end
+		device pci 00.0 on end 
+		device pci 00.1 on end
+		device pci 01.0 on end 
+		device pci 02.0 on 
+			chip southbridge/intel/pxhd # pxhd1
+				# Bus bridges and ioapics usually bus 1
+				device pci 0.0 on 
+				# On board gig e1000
+					chip drivers/generic/generic 
+        		        	        device pci 03.0 on end
+        		        	        device pci 03.1 on end
+        		        	end
+				end
+				device pci 0.1 on end
+				device pci 0.2 on end
+				device pci 0.3 on end
+			end
+		end
+		device pci 04.0 on end
+		device pci 06.0 on end
+	end
+	device apic_cluster 0 on
+		chip cpu/intel/socket_mPGA604 # cpu 0
+			device apic 0 on end
+		end
+		chip cpu/intel/socket_mPGA604 # cpu 1
+			device apic 6 on end
+		end
+	end
+	register "intrline" = "0x00070100"
+end
+

Added: trunk/coreboot-v2/src/mainboard/digitallogic/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,61 @@
+chip northbridge/intel/i855pm
+	device pci_domain 0 on 
+		device pci 0.0 on end
+		device pci 1.0 on end
+		chip southbridge/intel/i82801dbm
+#			pci 11.0 on end
+#			pci 11.1 on end
+#			pci 11.2 on end
+#			pci 11.3 on end
+#			pci 11.4 on end
+#			pci 11.5 on end
+#			pci 11.6 on end
+#			pci 12.0 on end
+			register "enable_usb" = "0"
+			register "enable_native_ide" = "0"
+			register "enable_usb" = "0"
+			register "enable_native_ide" = "0"
+			chip superio/winbond/w83627hf # link 1
+                	        device pnp 2e.0 on      #  Floppy
+                	                 io 0x60 = 0x3f0
+                	                irq 0x70 = 6
+                	                drq 0x74 = 2
+				end
+                	        device pnp 2e.1 off     #  Parallel Port
+                	                 io 0x60 = 0x378
+                	                irq 0x70 = 7
+				end
+                	        device pnp 2e.2 on      #  Com1
+                	                 io 0x60 = 0x3f8
+                	                irq 0x70 = 4
+				end
+                	        device pnp 2e.3 off     #  Com2
+                	                io 0x60 = 0x2f8
+                	                irq 0x70 = 3
+				end
+                	        device pnp 2e.5 on      #  Keyboard
+                	                 io 0x60 = 0x60
+                	                 io 0x62 = 0x64
+                	                irq 0x70 = 1
+					irq 0x72 = 12
+				end
+                	        device pnp 2e.6 off end #  CIR
+                	        device pnp 2e.7 off end #  GAME_MIDI_GIPO1
+                	        device pnp 2e.8 off end #  GPIO2
+                	        device pnp 2e.9 off end #  GPIO3
+                	        device pnp 2e.a off end #  ACPI
+                	        device pnp 2e.b on      #  HW Monitor
+ 					 io 0x60 = 0x290
+				end
+				register "com1" = "{1}"
+			#	register "com1" = "{1, 0, 0x3f8, 4}"
+			#	register "lpt" = "{1}"
+                	end
+		end
+	end
+	device apic_cluster 0 on 
+		chip cpu/intel/socket_mPGA479M
+			device apic 0 on end
+		end
+	end
+end

Added: trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm586seg/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,16 @@
+chip cpu/amd/sc520
+	device pci_domain 0 on 
+		device pci 0.0 on end
+	
+		chip drivers/pci/onboard
+			device pci 12.0 on end # enet
+		end
+		chip drivers/pci/onboard
+			device pci 14.0 on end # 69000
+			register "rom_address" = "0x2000000"
+		end
+#		register "com1" = "{1}"
+#		register "com1" = "{1, 0, 0x3f8, 4}"
+	end
+
+end

Added: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,86 @@
+chip northbridge/amd/lx
+  	device pci_domain 0 on 
+    		device pci 1.0 on end
+		device pci 1.1 on end
+      		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+			# How to get these? Boot linux and do this:
+			# rdmsr 0x51400025
+			register "lpc_serirq_enable" = "0x0000105a"
+			# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
+			register "lpc_serirq_polarity" = "0x0000EFA5"
+			# mode is high 10 bits (determined from code)
+			register "lpc_serirq_mode" = "1"
+			# Don't yet know how to find this.
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "0"	#0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "0"
+			register "com1_address" = "0x3F8"
+			register "com1_irq" = "4"
+			register "com2_enable" = "0"
+			register "com2_address" = "0x2F8"
+			register "com2_irq" = "3"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+        			device pci f.0 on	# ISA Bridge
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off #  Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.1 off #  Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.2 on #  Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on #  Com2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.5 on #  Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6 off #  CIR
+						io 0x60 = 0x100
+					end
+					device pnp 2e.7 off #  GAME_MIDI_GIPO1
+						io 0x60 = 0x220
+						io 0x62 = 0x300
+						irq 0x70 = 9
+					end						
+					device pnp 2e.8 off end #  GPIO2
+					device pnp 2e.9 off end #  GPIO3
+					device pnp 2e.a off end #  ACPI
+					device pnp 2e.b on #  HW Monitor
+						io 0x60 = 0x290
+						irq 0x70 = 5
+					end
+				end
+			end
+			device pci f.1 on end	# Flash controller
+			device pci f.2 on end	# IDE controller
+        			device pci f.3 on end 	# Audio
+        			device pci f.4 on end	# OHCI
+			device pci f.5 on end	# EHCI
+      		end
+	end
+
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+
+end
+

Added: trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/5bcm/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,54 @@
+chip northbridge/amd/gx1
+  device pci_domain 0 on 
+    device pci 0.0 on end
+      chip southbridge/amd/cs5530
+        device pci 12.0 on
+          chip superio/nsc/pc97317
+            device pnp 2e.0 on		# Keyboard
+               io 0x60 = 0x60
+               io 0x62 = 0x64
+              irq 0x70 = 1
+            end
+            device pnp 2e.1 on		# Mouse
+              irq 0x70 = 12
+            end
+            device pnp 2e.2 on		# RTC
+               io 0x60 = 0x70
+              irq 0x70 = 8
+            end
+            device pnp 2e.3 off		# FDC
+            end
+            device pnp 2e.4 on		# Parallel Port
+               io 0x60 = 0x378
+              irq 0x70 = 7
+            end
+            device pnp 2e.5 on		# COM2
+               io 0x60 = 0x2f8
+              irq 0x70 = 3
+            end
+            device pnp 2e.6 on		# COM1
+               io 0x60 = 0x3f8
+              irq 0x70 = 4
+            end
+            device pnp 2e.7 on		# GPIO
+               io 0x60 = 0xe0
+            end
+            device pnp 2e.8 on		# Power Management
+               io 0x60 = 0xe800
+            end
+            register "com1" = "{115200}"
+            register "com2" = "{38400}"
+          end
+        device pci 12.1 off end		# SMI
+        device pci 12.2 on  end		# IDE
+        device pci 12.3 off end 	# Audio
+        device pci 12.4 off end		# VGA
+      end
+    end
+  end
+
+  chip cpu/amd/model_gx1
+  end
+
+end
+

Added: trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/eaglelion/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/embeddedplanet/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/embeddedplanet/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/embeddedplanet/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/embeddedplanet/ep405pc/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,17 @@
+chip cpu/ppc/ppc4xx 
+	device pci_domain 0 on
+		device pci 0.0 on end
+		chip southbridge/winbond/w83c553 
+			device pci 9.0 on end # ISA bridge
+			device pci 9.1 on end # IDE contoller
+		end
+		device pci e.0 on end
+	end
+end
+	
+##
+## Build the objects we have code for in this directory.
+##
+
+addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
+makedefine CFLAGS += -msoft-float

Added: trunk/coreboot-v2/src/mainboard/emulation/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/emulation/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,25 @@
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_EMULATION
+
+config BOARD_EMULATION_QEMU_X86
+	bool "QEMU x86"
+	select ARCH_X86
+	select CPU_I586
+	select SOUTHBRIDGE_INTEL_I82371EB
+	select CPU_EMULATION_QEMU_X86
+	select CONSOLE_SERIAL8250
+	help
+	  x86 QEMU variant.
+
+endchoice
+
+config MAINBOARD_DIR
+	string
+	default emulation/qemu-x86
+	depends on BOARD_EMULATION_QEMU_X86
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "QEMU-86"
+	depends on BOARD_EMULATION_QEMU_X86

Added: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,21 @@
+initobj-y += crt0.o
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += auto.inc
+
+obj-y += mainboard.o
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(obj)/romcc -mcpu=i386 -O $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+
+endif

Added: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,15 @@
+chip cpu/emulation/qemu-x86
+	device pci_domain 0 on 
+		device pci 0.0 on end
+
+		chip southbridge/intel/i82371eb # southbridge
+			device pci 01.0 on end
+			device pci 01.1 on end
+			register "ide0_enable" = "1"
+			register "ide1_enable" = "1"
+		end
+
+#		register "com1" = "{1}"
+#		register "com1" = "{1, 0, 0x3f8, 4}"
+	end
+end

Added: trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga-6bxc/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,57 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/ite/it8671f	# Super I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.2 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.3 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 3f0.4 on		# APC
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 3f0.6 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 3f0.7 on		# GPIO
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,106 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_AM2
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on
+				#  devices on link 0, link 0 == LDT 0
+			        chip southbridge/sis/sis966
+					device pci 0.0 on end   # Northbridge
+					device pci 1.0 on		# AGP bridge
+					  chip drivers/pci/onboard	# Integrated VGA
+						device pci 0.0 on end
+						register "rom_address" = "0xfff80000"
+					  end
+					end
+                			device pci 2.0 on # LPC
+						chip superio/ite/it8716f
+							device pnp 2e.0 off #  Floppy (N/A)
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.2 off #  Com2 (N/A)
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.3 off #  Parallel port (N/A)
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.4 on #  EC
+                	                 			io 0x60 = 0x290
+                	                 			io 0x62 = 0x230
+                	                			irq 0x70 = 9
+							end
+							device pnp 2e.5 off #  PS/2 keyboard (N/A)
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+							end
+							device pnp 2e.6 off #  Mouse (N/A)
+                	                			irq 0x70 = 12
+							end
+                	        			device pnp 2e.8 off #  MIDI (N/A)
+								io 0x60 = 0x300
+								irq 0x70 = 10
+							end
+                	        			device pnp 2e.9 off #  GAME (N/A)
+								io 0x60 = 0x220
+							end
+                	        			device pnp 2e.a off end #  CIR (N/A)
+						end
+					end
+
+                                        device pci 2.5 off end # IDE (SiS5513)
+                                        device pci 2.6 off end # Modem (SiS7013)
+                                        device pci 2.7 off end # Audio (SiS7012)
+                                        device pci 3.0 on end # USB (SiS7001,USB1.1)
+                                        device pci 3.1 on end # USB (SiS7001,USB1.1)
+                                        device pci 3.3 on end # USB (SiS7002,USB2.0)
+                                        device pci 4.0 on end # NIC (SiS191)
+                                        device pci 5.0 on end # SATA (SiS1183,Native Mode)
+                                        device pci 6.0 on end # PCI-e x1
+                                        device pci 7.0 on end # PCI-e x1
+                                        device pci a.0 off end
+                                        device pci b.0 off end
+                                        device pci c.0 off end
+                                        device pci d.0 off end
+                                        device pci e.0 off end
+                                        device pci f.0 off end # HD Audio (SiS7502)
+
+                                        register "ide0_enable" = "1"
+                                        register "ide1_enable" = "1"
+                                        register "sata0_enable" = "1"
+                                        register "sata1_enable" = "1"
+				end
+			end #  device pci 18.0
+			device pci 18.0 on end # Link 1
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+
+	end # PCI domain
+
+#       chip drivers/generic/debug
+#               device pnp 0.0 off end # chip name
+#               device pnp 0.1 on end # pci_regs_all
+#               device pnp 0.2 off end # mem
+#               device pnp 0.3 off end # cpuid
+#               device pnp 0.4 off end # smbus_regs_all
+#               device pnp 0.5 off end # dual core msr
+#               device pnp 0.6 off end # cache size
+#               device pnp 0.7 off end # tsc
+#               device pnp 0.8 off end # io
+#               device pnp 0.9 off end # io
+#       end
+end #root_complex

Added: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,202 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_AM2
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on 
+				#  devices on link 0, link 0 == LDT 0 
+			        chip southbridge/nvidia/mcp55 
+					device pci 0.0 on end   # HT
+                			device pci 1.0 on # LPC
+						chip superio/ite/it8716f
+							# Floppy and any LDN
+							device pnp 2e.0 off
+                	               			# Watchdog from CLKIN, CLKIN = 24 MHz
+                	                 			irq 0x23 = 0x11 
+							# Serial Flash (SPI only)
+								#0x24 = 0x1a
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.2 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.3 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.4 on #  EC
+                	                 			io 0x60 = 0x290
+                	                 			io 0x62 = 0x230
+                	                			irq 0x70 = 9
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+							end
+                	        			device pnp 2e.6 on #  Mouse
+                	                			irq 0x70 = 12
+							end
+	              	        			device pnp 2e.7 on #  GPIO, SPI flash
+								# pin 84 is not GP10
+								irq 0x25 = 0x0
+				# pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
+								irq 0x26 = 0x43
+								# pin 13 is GP35
+								irq 0x27 = 0x20 
+								# pin 70 is not GP46
+								#irq 0x28 = 0x0
+				# pin 6,3,128,127,126 is GP63,64,65,66,67
+								irq 0x29 = 0x81
+				# Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
+								#irq 0x2c = 0x1f
+				# Simple I/O base
+								io 0x62 = 0x800
+				# Serial Flash I/O (SPI only)
+								io 0x64 = 0x820
+				# watch dog force timeout (parallel flash only)
+								#irq 0x71 = 0x1
+								# No WDT interrupt
+								irq 0x72 = 0x0 
+					# GPIO pin set 1 disable internal pullup
+								irq 0xb8 = 0x0
+					# GPIO pin set 5 enable internal pullup
+								irq 0xbc = 0x01
+					# SIO pin set 1 alternate function
+								#irq 0xc0 = 0x0
+					# SIO pin set 2 mixed function
+								irq 0xc1 = 0x43
+					# SIO pin set 3 mixed function
+								irq 0xc2 = 0x20
+					# SIO pin set 4 alternate function
+								#irq 0xc3 = 0x0
+					# SIO pin set 1 input mode
+								#irq 0xc8 = 0x0
+					# SIO pin set 2 input mode
+								irq 0xc9 = 0x0
+					# SIO pin set 4 input mode
+								#irq 0xcb = 0x0
+					# Generate SMI# on EC IRQ
+								#irq 0xf0 = 0x10
+					# SMI# level trigger
+								#irq 0xf1 = 0x40
+					# HWMON alert beep pin location
+								irq 0xf6 = 0x28
+							end
+                	        			device pnp 2e.8 off #  MIDI
+								io 0x60 = 0x300
+								irq 0x70 = 10
+							end
+                	        			device pnp 2e.9 off #  GAME
+								io 0x60 = 0x220
+							end
+                	        			device pnp 2e.a off end #  CIR
+						end
+					end
+			                device pci 1.1 on # SM 0
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end  
+                                                end              
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end             
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end              
+                                                chip drivers/generic/generic #dimm 1-0-0
+                                                        device i2c 54 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-0-1
+                                                        device i2c 55 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-0
+                                                        device i2c 56 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-1
+                                                        device i2c 57 on end
+                                                end 
+					end # SM
+#WTF?!? We already have device pci 1.1 in the section above
+                                        device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#                                                chip drivers/generic/generic #PCIXA Slot1
+#                                                        device i2c 50 on end
+#                                                end
+#                                                chip drivers/generic/generic #PCIXB Slot1
+#                                                        device i2c 51 on end
+#                                                end     
+#                                                chip drivers/generic/generic #PCIXB Slot2
+#                                                        device i2c 52 on end
+#                                                end             
+#                                                chip drivers/generic/generic #PCI Slot1
+#                                                        device i2c 53 on end
+#                                                end              
+#                                                chip drivers/generic/generic #Master MCP55 PCI-E
+#                                                        device i2c 54 on end
+#                                                end     
+#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
+#                                                        device i2c 55 on end
+#                                                end             
+                                                chip drivers/generic/generic #MAC EEPROM
+                                                        device i2c 51 on end
+                                                end 
+
+                                        end # SM 
+	                		device pci 2.0 on end # USB 1.1
+        	        		device pci 2.1 on end # USB 2
+                			device pci 4.0 on end # IDE
+	                		device pci 5.0 on end # SATA 0
+	                		device pci 5.1 on end # SATA 1
+	                		device pci 5.2 on end # SATA 2
+                			device pci 6.0 on end # PCI
+        	        		device pci 6.1 on end # AZA
+	                		device pci 8.0 on end # NIC
+	                		device pci 9.0 off end # NIC
+        	       			device pci a.0 on end # PCI E 5
+        	       			device pci b.0 on end # PCI E 4
+                			device pci c.0 on end # PCI E 3
+                			device pci d.0 on end # PCI E 2
+                			device pci e.0 on end # PCI E 1
+        	       			device pci f.0 on end # PCI E 0
+	                                register "ide0_enable" = "1"
+                	                register "sata0_enable" = "1"
+                        	        register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0 
+			device pci 18.0 on end # Link 1
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+		
+	end # PCI domain
+	
+#       chip drivers/generic/debug 
+#               device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 on end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 on end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#               device pnp 0.7 off end # tsc
+#                device pnp 0.8 off  end # io
+#                device pnp 0.9 off end # io
+#       end  
+end #root_complex

Added: trunk/coreboot-v2/src/mainboard/hp/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/hp/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/hp/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,96 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_F
+			device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8  # northbridge
+			device pci 18.0 on  # devices on link 0
+				chip southbridge/broadcom/bcm21000 # HT2100
+					device pci 0.0 on
+					end   # bridge to slot PCI-E 4x ??
+					device pci 1.0 on
+					end
+					device pci 2.0 on
+					end  # unused
+					device pci 3.0 on  	# bridge to slot PCI-E 16x ??
+					end
+					device pci 4.0 on
+					end  # unused
+					device pci 5.0 on
+						device pci 4.0 on end # BCM5715 NIC
+						device pci 4.1 on end # BCM5715 NIC
+					end
+				end
+				chip southbridge/broadcom/bcm5785 # HT1000
+					device pci 0.0 on  # HT PXB  0x0036
+						device pci d.0 on end # PCI/PCI-X bridge 0x0104
+						device pci e.0 on end # SATA 0x024a
+					end
+					device pci 1.0 on end # Legacy  pci main  0x0205
+					device pci 1.1 on end # IDE	0x0214
+					device pci 1.2 on     # LPC	0x0234
+						chip superio/nsc/pc87417
+							device  pnp 4e.0 off  # Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 4e.1 off  # Parallel Port
+									io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 4e.2 off # Com 2
+									io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 4e.3 off  # Com 1
+									io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 4e.4 off end # SWC
+							device pnp 4e.5 off end # Mouse
+							device pnp 4e.6 off  # Keyboard
+									io 0x60 = 0x60
+									io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 4e.7 off end # GPIO
+							device pnp 4e.f off end # XBUS
+							device pnp 4e.10 on #RTC
+								io 0x60 = 0x70
+								io 0x62 = 0x72
+							end
+						end # end superio
+					end # end pci 1.2
+					device pci 1.3 off end # WDTimer    0x0238
+					device pci 1.4 on end # XIOAPIC0   0x0235
+					device pci 1.5 on end # XIOAPIC1
+					device pci 1.6 on end # XIOAPIC2
+					device pci 2.0 on end # USB	0x0223
+					device pci 2.1 on end # USB
+					device pci 2.2 on end # USB
+					device pci 3.0 on end # VGA
+					
+					#bx_a013+ start
+					#chip drivers/pci/onboard    #SATA2
+					#	device pci 5.0 on end
+					#	device pci 5.1 on end
+					#	device pci 5.2 on end
+					#	device pci 5.3 on end
+					#end
+					#bx_a013+ end
+				end
+			end
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+      end # amdk8
+
+   end #pci_domain
+end
+
+

Added: trunk/coreboot-v2/src/mainboard/ibm/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/ibm/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/ibm/e325/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,81 @@
+chip northbridge/amd/amdk8/root_complex
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on end # LDT 0
+			device pci 18.0 on     # LDT 1
+				chip southbridge/amd/amd8131
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 on end
+						device pci 1.0 off end
+					end
+					device pci 1.0 on
+						chip superio/nsc/pc87366
+							device	pnp 2e.0 off  # Floppy 
+								 io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off  # Parallel Port
+								 io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 off # Com 2
+								 io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 on  # Com 1
+								 io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.4 off end # SWC
+							device pnp 2e.5 off end # Mouse
+							device pnp 2e.6 on  # Keyboard
+								 io 0x60 = 0x60
+								 io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 2e.7 off end # GPIO
+							device pnp 2e.8 off end # ACB
+							device pnp 2e.9 off end # FSCM
+							device pnp 2e.a off end # WDT  
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on end
+					device pci 1.5 off end
+					device pci 1.6 off end
+				end
+			end #  device pci 18.0 
+			device pci 18.0 on end # LDT2
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+		chip northbridge/amd/amdk8
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.1 on end
+			device pci 19.2 on end
+			device pci 19.3 on end
+		end
+	end 
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+		chip cpu/amd/socket_940
+			device apic 1 on end
+		end
+	end
+end
+

Added: trunk/coreboot-v2/src/mainboard/ibm/e326/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,77 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+	end
+
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on end # LDT 0
+			device pci 18.0 on     # LDT 1
+				chip southbridge/amd/amd8131
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 on end
+						device pci 1.0 off end
+                                                chip drivers/pci/onboard
+                                                        device pci 5.0 on end # ATI Rage XL
+                                                        register "rom_address" = "0xfff80000"
+                                                end
+					end
+					device pci 1.0 on
+						chip superio/nsc/pc87366
+							device	pnp 2e.0 off  # Floppy 
+								 io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off  # Parallel Port
+								 io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 off # Com 2
+								 io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 on  # Com 1
+								 io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.4 off end # SWC
+							device pnp 2e.5 off end # Mouse
+							device pnp 2e.6 on  # Keyboard
+								 io 0x60 = 0x60
+								 io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 2e.7 off end # GPIO
+							device pnp 2e.8 off end # ACB
+							device pnp 2e.9 off end # FSCM
+							device pnp 2e.a off end # WDT  
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on end
+					device pci 1.5 off end
+					device pci 1.6 off end
+					register "ide0_enable" = "1"
+					register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0 
+			device pci 18.0 on end # LDT2
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+	end 
+end
+

Added: trunk/coreboot-v2/src/mainboard/iei/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/iei/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/iei/juki-511p/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/juki-511p/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/iei/juki-511p/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,59 @@
+chip northbridge/amd/gx1
+  device pci_domain 0 on
+    device pci 0.0 on end
+      chip southbridge/amd/cs5530
+
+        device pci 12.0 on
+          chip superio/winbond/w83977f
+            device pnp 3f0.0 on		# FDC
+              irq 0x70 = 6
+            end
+            device pnp 3f0.1 on		# Parallel port
+              io 0x60 = 0x378
+              irq 0x70 = 7
+            end
+            device pnp 3f0.2 on		# COM1
+              io 0x60 = 0x3f8
+              irq 0x70 = 4
+            end
+            register "com1" = "{115200}"
+            device pnp 3f0.3 on		# COM2
+              io 0x60 = 0x2f8
+              irq 0x70 = 3
+            end
+            register "com2" = "{115200}"
+            device pnp 3f0.4 on		# RTC
+              io 0x60 = 0x070
+              irq 0x70 = 8
+            end
+            device pnp 3f0.5 on		# Keyboard
+              io 0x60 = 0x60
+              io 0x62 = 0x64
+              irq 0x70 = 1		# Int  1 for PS/2 keyboard
+              irq 0x72 = 12		# Int 12 for PS/2 mouse
+            end
+            device pnp 3f0.6 off	# IR
+            end
+            device pnp 3f0.7 off	# GPIO1
+            end
+            device pnp 3f0.8 off	# GPIO
+            end
+          end
+        device pci 12.1 on end		# SMI
+        device pci 12.2 on end		# IDE
+        device pci 12.3 on end		# Audio
+        device pci 12.4 on end		# VGA onboard
+
+      end
+
+      device pci 0e.0 on end		# ETH0
+      device pci 13.0 on end		# USB
+
+    end
+  end
+
+  chip cpu/amd/model_gx1
+  end
+
+end
+

Added: trunk/coreboot-v2/src/mainboard/iei/nova4899r/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/nova4899r/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/iei/nova4899r/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,66 @@
+chip northbridge/amd/gx1
+  device pci_domain 0 on
+    device pci 0.0 on end
+      chip southbridge/amd/cs5530
+        device pci 0a.0 on  end		# ETH0
+        device pci 0b.0 off end		# ETH1
+        device pci 0c.0 on  end		# ETH2
+        device pci 0f.0 on  end		# PCI slot
+        device pci 12.0 on
+          chip superio/winbond/w83977tf
+            device pnp 2e.0 on		# FDC
+              irq 0x70 = 6
+            end
+            device pnp 2e.1 on		# Parallel Port
+               io 0x60 = 0x378
+              irq 0x70 = 7
+            end
+            device pnp 2e.2 on		# COM1
+               io 0x60 = 0x3f8
+              irq 0x70 = 4
+            end
+            register "com1" = "{115200}"
+            device pnp 2e.3 on		# COM2
+               io 0x60 = 0x2f8
+              irq 0x70 = 3
+            end
+            register "com2" = "{115200}"
+            device pnp 2e.4 off		# Reserved
+            end
+            device pnp 2e.5 on		# Keyboard
+               io 0x60 = 0x60
+               io 0x62 = 0x64
+              irq 0x70 = 0x01		# Int  1 for PS/2 keyboard
+              irq 0x72 = 0x0c		# Int 12 for PS/2 mouse
+            end
+            device pnp 2e.6 on		# IR
+               io 0x60 = 0x2e8
+              irq 0x70 = 3
+            end
+            device pnp 2e.7 on		# GAME/MIDI/GPIO1
+               io 0x60 = 0x290
+            end
+            device pnp 2e.8 on		# GPIO2
+               io 0x60 = 0x110
+            end
+            device pnp 2e.9 on		# GPIO3
+               io 0x60 = 0x120
+            end
+            device pnp 2e.A on		# Power Management
+               io 0x60 = 0xe800
+            end
+          end
+        device pci 12.1 on  end		# SMI
+        device pci 12.2 on  end		# IDE
+        device pci 12.3 on  end		# Audio
+        device pci 12.4 on  end		# VGA onboard
+      end
+      device pci 13.0 on end		# USB
+    end
+  end
+
+  chip cpu/amd/model_gx1
+  end
+
+end
+

Added: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,76 @@
+chip northbridge/amd/lx
+	device pci_domain 0 on
+		device pci 1.0 on end				# Northbridge
+		device pci 1.1 on end				# Graphics
+		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
+			register "lpc_serirq_enable" = "0x0000105a"
+			register "lpc_serirq_polarity" = "0x0000EFA5"
+			register "lpc_serirq_mode" = "1"
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0"	# 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "1"	# 0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "0"
+			register "com1_address" = "0x3F8"
+			register "com1_irq" = "4"
+			register "com2_enable" = "0"
+			register "com2_address" = "0x2F8"
+			register "com2_irq" = "3"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+			device pci 9.0 on end			# Slot1
+			device pci a.0 on end			# Slot2
+			device pci b.0 on end			# Slot3
+			device pci c.0 on end			# Slot4
+			device pci e.0 on end			# Ethernet 0
+			device pci 10.0 on end			# Ethernet 1
+			device pci 11.0 on end			# SATA
+			device pci f.0 on			# ISA Bridge
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off	# Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.1 off	# Parallel port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.2 on	# Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on	# Com2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.5 on	# Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6 off end	# CIR
+					device pnp 2e.7 off end	# GAME_MIDI_GIPO1
+					device pnp 2e.8 off end	# GPIO2
+					device pnp 2e.9 off end	# GPIO3
+					device pnp 2e.a off end	# ACPI
+					device pnp 2e.b off end	# HW Monitor
+				end
+			end
+			device pci f.2 on end			# IDE Controller
+			device pci f.3 on end			# Audio
+			device pci f.4 on end			# OHCI
+			device pci f.5 on end			# EHCI
+		end
+	end
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+end
+

Added: trunk/coreboot-v2/src/mainboard/intel/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/intel/jarrell/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/jarrell/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/jarrell/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,79 @@
+chip northbridge/intel/e7520
+	device pci_domain 0 on 
+		device pci 00.0 on end
+		device pci 00.1 on end
+		device pci 01.0 on end
+		device pci 02.0 on 
+			chip southbridge/intel/pxhd # pxhd1
+				device pci 00.0 on end
+				device pci 00.1 on end
+				device pci 00.2 on
+					chip drivers/generic/generic
+						device pci 04.0 on end
+						device pci 04.1 on end
+					end
+				end
+				device pci 00.3 on end
+			end
+		end
+		device pci 06.0 on end
+		chip southbridge/intel/i82801er # i82801er
+			device pci 1d.0 on end
+			device pci 1d.1 on end
+			device pci 1d.2 on end
+			device pci 1d.3 off end
+			device pci 1d.7 on end
+			device pci 1e.0 on
+				chip drivers/ati/ragexl
+					device pci 0c.0 on end
+				end
+			end
+			device pci 1f.0 on 
+				chip superio/nsc/pc87427
+					device pnp 2e.0 off end
+					device pnp 2e.2 on
+#						 io 0x60 = 0x2f8
+#						irq 0x70 = 3
+						 io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on
+#						 io 0x60 = 0x3f8
+#						irq 0x70 = 4
+						 io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.4 off end
+					device pnp 2e.5 off end
+					device pnp 2e.6 on
+						 io 0x60 = 0x60
+						 io 0x62 = 0x64
+						irq 0x70 = 1
+					end
+					device pnp 2e.7 off end
+					device pnp 2e.9 off end
+					device pnp 2e.a off end
+					device pnp 2e.f on end
+					device pnp 2e.10 off end
+					device pnp 2e.14 off end
+				end
+			end
+			device pci 1f.1 on end
+			device pci 1f.2 off end
+			device pci 1f.3 on end 
+			device pci 1f.5 off end
+			device pci 1f.6 off end
+			register "gpio[40]" = "ICH5R_GPIO_USE_AS_GPIO"
+			register "gpio[48]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_OUTPUT | ICH5R_GPIO_LVL_LOW"
+			register "gpio[41]" = "ICH5R_GPIO_USE_AS_GPIO | ICH5R_GPIO_SEL_INPUT"
+		end
+	end
+	device apic_cluster 0 on
+		chip cpu/intel/socket_mPGA604 # cpu 0
+			device apic 0 on end
+		end
+		chip cpu/intel/socket_mPGA604 # cpu 1
+			device apic 6 on end
+		end
+	end
+end

Added: trunk/coreboot-v2/src/mainboard/intel/mtarvon/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/mtarvon/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/mtarvon/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,44 @@
+chip northbridge/intel/i3100
+        device pci_domain 0 on
+                device pci 00.0 on end # IMCH
+                device pci 00.1 on end # IMCH error status
+                device pci 01.0 on end # IMCH EDMA engine
+                device pci 02.0 on end # PCIe port A/A0
+                device pci 03.0 on end # PCIe port A1
+                chip southbridge/intel/i3100
+                        # PIRQ line -> legacy IRQ mappings
+                        register "pirq_a_d" = "0x0b070a05"
+                        register "pirq_e_h" = "0x0a808080"
+
+                        device pci 1c.0 on end # PCIe port B0
+                        device pci 1c.1 on end # PCIe port B1
+                        device pci 1c.2 on end # PCIe port B2
+                        device pci 1c.3 on end # PCIe port B3
+                        device pci 1d.0 on end # USB (UHCI) 1
+                        device pci 1d.1 on end # USB (UHCI) 2
+                        device pci 1d.7 on end # USB (EHCI)
+                        device pci 1e.0 on end # PCI bridge
+                        device pci 1e.2 on end # audio
+                        device pci 1e.3 on end # modem
+                        device pci 1f.0 on     # LPC bridge
+                                chip superio/intel/i3100
+                                        device pnp 4e.4 on # Com1
+                                                 io 0x60 = 0x3f8
+                                                irq 0x70 = 4
+                                        end
+                                        device pnp 4e.5 on # Com2
+                                                 io 0x60 = 0x2f8
+                                                irq 0x70 = 3
+                                        end
+                                end
+                        end
+                        device pci 1f.2 on end # SATA
+                        device pci 1f.3 on end # SMBus
+                end
+        end
+        device apic_cluster 0 on
+                chip cpu/intel/socket_mPGA479M
+                        device apic 0 on end
+                end
+        end
+end

Added: trunk/coreboot-v2/src/mainboard/intel/truxton/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/truxton/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/truxton/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,41 @@
+chip northbridge/intel/i3100
+        device pci_domain 0 on
+                device pci 00.0 on end # IMCH
+                device pci 00.1 on end # IMCH error status
+                device pci 01.0 on end # IMCH EDMA engine
+                device pci 02.0 on end # PCIe port A/A0
+                device pci 03.0 on end # PCIe port A1
+                device pci 04.0 on end # ?
+                device pci 08.0 off end # must be off to boot
+                device pci 0d.0 off end # must be off to boot
+                device pci 0d.1 off end # must be off to boot
+                chip southbridge/intel/i3100
+                        # PIRQ line -> legacy IRQ mappings
+                        register "pirq_a_d" = "0x0b070a05"
+                        register "pirq_e_h" = "0x0a808080"
+
+                        device pci 1d.0 on end  # USB (UHCI)
+                        device pci 1d.7 on end  # USB (EHCI)
+                        device pci 1f.0 on      # LPC bridge
+                                chip superio/intel/i3100
+                                        device pnp 4e.4 on # Com1
+                                                 io 0x60 = 0x3f8
+                                                irq 0x70 = 4
+                                        end
+                                        device pnp 4e.5 on # Com2
+                                                 io 0x60 = 0x2f8
+                                                irq 0x70 = 3
+                                        end
+                                end
+                        end
+                        device pci 1f.2 on end  # SATA
+                        device pci 1f.3 on end  # SMBus
+                        device pci 1f.4 on end  # ?
+                end
+        end
+        device apic_cluster 0 on
+                chip cpu/intel/ep80579
+                        device apic 0 on end
+                end
+        end
+end

Added: trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/intel/xe7501devkit/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,75 @@
+chip northbridge/intel/e7501
+	device pci_domain 0 on
+		device pci 0.0 on end # Chipset host controller
+		device pci 0.1 on end # Host RASUM controller
+		device pci 2.0 on # Hub interface B
+			chip southbridge/intel/i82870 # P64H2
+				device pci 1c.0 on end # IOAPIC - bus B
+				device pci 1d.0 on end # Hub to PCI-B bridge
+				device pci 1e.0 on end # IOAPIC - bus A
+				device pci 1f.0 on end # Hub to PCI-A bridge
+			end
+		end
+		device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
+		device pci 4.0 on # Hub interface D
+			chip southbridge/intel/i82870 # P64H2
+				device pci 1c.0 on end # IOAPIC - bus B
+				device pci 1d.0 on end # Hub to PCI-B bridge
+				device pci 1e.0 on end # IOAPIC - bus A
+				device pci 1f.0 on end # Hub to PCI-A bridge
+			end
+		end
+		device pci 6.0 on end # E7501 Power management registers? (undocumented)
+		chip southbridge/intel/i82801ca
+			device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
+			device pci 1d.1 off end # USB (not populated)
+			device pci 1d.2 off end # USB (not populated)
+			device pci 1e.0 on # Hub to PCI bridge
+				chip drivers/pci/onboard # VGA ROM
+					device pci 0.0 on end
+				register "rom_address" = "_vgarom_start"
+				end
+			end
+			device pci 1f.0 on # LPC bridge
+				chip superio/smsc/lpc47b272
+					device pnp 2e.0 off # Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.3 off # Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.4 on # Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.5 off # Com2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.7 on # Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1 # Keyboard interrupt
+						irq 0x72 = 12 # Mouse interrupt
+					end
+					device pnp 2e.a off end # ACPI
+				end
+			end
+			device pci 1f.1 on end # IDE
+			device pci 1f.3 on end # SMBus
+			device pci 1f.5 off end # AC97 Audio
+			device pci 1f.6 off end # AC97 Modem
+		end # SB
+	end # PCI_DOMAIN
+	device apic_cluster 0 on
+		chip cpu/intel/socket_mPGA604
+			device apic 0 on end
+		end
+		chip cpu/intel/socket_mPGA604
+			device apic 6 on end
+		end
+	end
+end

Added: trunk/coreboot-v2/src/mainboard/iwill/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/iwill/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,133 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_940
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.0 on #  northbridge 
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+                                                #chip drivers/pci/onboard
+                                                #        device pci 6.0 on end
+						#	register "rom_address" = "0xfff80000"
+                                                #end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	        			device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+							device pnp 2e.8 on #  GPIO2
+								io 0x07 = 0x08ff
+								io 0x30 = 0x01ff
+								io 0x2b = 0xd0ff
+								io 0xf0 = 0xef16
+							end
+                	        			device pnp 2e.9 off end #  GPIO3
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-0
+							device i2c 54 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-1
+							device i2c 55 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-0
+							device i2c 56 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-1
+							device i2c 57 on end
+						end
+					end # acpi
+					device pci 1.5 off end
+					device pci 1.6 off end
+                	                register "ide0_enable" = "1"
+                	                register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0
+
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+
+	end #pci_domain
+#        chip drivers/generic/debug
+#        	device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 off end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 off end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#                device pnp 0.7 off end # tsc
+#       end
+
+end
+
+

Added: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,89 @@
+chip northbridge/amd/amdk8/root_complex
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on # LDT 0
+				chip southbridge/amd/amd8131
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 on end
+						device pci 1.0 off end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp  2e.0 on      # Floppy
+								 io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp  2e.1 off     # Parallel Port
+								 io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp  2e.2 on      # Com1
+								 io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp  2e.3 off     # Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp  2e.5 on      # Keyboard
+								 io 0x60 = 0x60
+								 io 0x62 = 0x64
+							       irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp  2e.6 off end # CIR
+							device pnp  2e.7 off end # GAME_MIDI_GIPO1
+							device pnp  2e.8 off end # GPIO2
+							device pnp  2e.9 off end # GPIO3
+							device pnp  2e.a off end # ACPI
+							device pnp  2e.b on      # HW Monitor
+								 io 0x60 = 0x290
+							end
+							register "com1" = "{1}"
+						#	register "com1" = "{1, 0, 0x3f8, 4}"
+						#	register "lpt" = "{1}"
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on end
+					device pci 1.5 off end
+					device pci 1.6 off end
+				end
+			end # LDT0
+			device pci 18.0 on end # LDT1
+			device pci 18.0 on end # LDT2
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+		chip northbridge/amd/amdk8
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.1 on end
+			device pci 19.2 on end
+			device pci 19.3 on end
+		end
+	end
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+		chip cpu/amd/socket_940
+			device apic 1 on end
+		end
+	end
+end
+

Added: trunk/coreboot-v2/src/mainboard/iwill/dk8x/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,68 @@
+chip northbridge/amd/amdk8/root_complex
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  northbridge 
+				#  devices on link 0, link 0 == LDT 0 
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 on end
+						device pci 1.0 off end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627thf
+							device pnp 2e.0 on end
+							device pnp 2e.1 on end
+							device pnp 2e.2 on end
+							device pnp 2e.3 on end
+							device pnp 2e.4 on end
+							device pnp 2e.5 on end
+							device pnp 2e.6 on end
+							device pnp 2e.7 on end 
+							device pnp 2e.8 on end 
+							device pnp 2e.9 on end 
+							device pnp 2e.a on end 
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on end 
+					device pci 1.5 off end
+					device pci 1.6 off end
+				end
+			end # LDT0
+			device pci 18.0 on end # LDT1
+			device pci 18.0 on end # LDT2
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+		chip northbridge/amd/amdk8
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.1 on end
+			device pci 19.2 on end
+			device pci 19.3 on end
+		end
+	end 
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+		chip cpu/amd/socket_940
+			device apic 1 on end
+		end
+	end
+end
+

Added: trunk/coreboot-v2/src/mainboard/jetway/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/jetway/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/jetway/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/jetway/j7f24/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/jetway/j7f24/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/jetway/j7f24/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,62 @@
+chip northbridge/via/cn700			# Northbridge
+  device pci_domain 0 on			# PCI domain
+    device pci 0.0 on end			# AGP Bridge
+    device pci 0.1 on end			# Error Reporting
+    device pci 0.2 on end			# Host Bus Control
+    device pci 0.3 on end			# Memory Controller
+    device pci 0.4 on end			# Power Management
+    device pci 0.7 on end			# V-Link Controller
+    device pci 1.0 on end			# PCI Bridge
+    chip southbridge/via/vt8237r		# Southbridge
+      # Enable both IDE channels.
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      # Both cables are 40pin.
+      register "ide0_80pin_cable" = "0"
+      register "ide1_80pin_cable" = "0"
+      register "fn_ctrl_lo" = "0x80"
+      register "fn_ctrl_hi" = "0x1d"
+      device pci a.0 on end			# Firewire
+      device pci f.0 on end			# SATA
+      device pci f.1 on end			# IDE
+      device pci 10.0 on end			# OHCI
+      device pci 10.1 on end			# OHCI
+      device pci 10.2 on end			# OHCI
+      device pci 10.3 on end			# OHCI
+      device pci 10.4 on end			# EHCI
+      device pci 11.0 on			# Southbridge LPC
+        chip superio/fintek/f71805f		# Super I/O
+          device pnp 2e.0 off			# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on			# Parallel Port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 2e.2 on			# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.3 on			# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.b on			# HWM
+            io 0x60 = 0xec00
+          end
+        end
+      end
+      device pci 11.5 on end			# AC'97 audio
+      # device pci 11.6 off end			# AC'97 Modem
+      device pci 12.0 on end			# Ethernet
+    end
+  end
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/via/model_c7			# VIA C7
+      device apic 0 on end			# APIC
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,77 @@
+##
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+## 
+
+driver-y +=  mainboard.o
+driver-y +=  rtl8168.o
+
+#obj-y += ../../../southbridge/intel/i82801gx/i82801gx_reset.c
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  fadt.o
+
+smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o
+
+# This is part of the conversion to init-obj and away from included code. 
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/intel/model_6ex/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+MAINBOARD_OPTIONS=\
+	-DCONFIG_AP_IN_SIPI_WAIT=1 \
+	-DCONFIG_USE_PRINTK_IN_CAR=1 \
+	-DCONFIG_HAVE_HIGH_TABLES=1 \
+	-DCONFIG_MMCONF_SUPPORT=1 \
+	-DCONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+

Added: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,132 @@
+chip northbridge/intel/i945
+
+        device apic_cluster 0 on
+                chip cpu/intel/socket_mFCPGA478
+                        device apic 0 on end
+                end
+        end
+
+        device pci_domain 0 on 
+                device pci 00.0 on end # host bridge
+		device pci 01.0 off end # i945 PCIe root port
+		chip drivers/pci/onboard
+			device pci 02.0 on end # vga controller
+			# register "rom_address" = "0xfffc0000"	# 256 KB image
+			# register "rom_address" = "0xfff80000"	# 512 KB image
+			register "rom_address" = "0xfff00000" # 1 MB image
+		end
+		device pci 02.1 on end # display controller
+
+                chip southbridge/intel/i82801gx
+			register "pirqa_routing" = "0x05"
+			register "pirqb_routing" = "0x07"
+			register "pirqc_routing" = "0x05"
+			register "pirqd_routing" = "0x07"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x06"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "gpi13_routing" = "1"
+
+                        register "ide_legacy_combined" = "0x1"
+                        register "ide_enable_primary" = "0x1"
+                        register "ide_enable_secondary" = "0x1"
+                        register "sata_ahci" = "0x0"
+
+                	device pci 1b.0 on end # High Definition Audio
+                	device pci 1c.0 on end # PCIe
+                	device pci 1c.1 on end # PCIe
+                	device pci 1c.2 on end # PCIe
+			#device pci 1c.3 off end # PCIe port 4
+			#device pci 1c.4 off end # PCIe port 5
+			#device pci 1c.5 off end # PCIe port 6
+                	device pci 1d.0 on end # USB UHCI
+                	device pci 1d.1 on end # USB UHCI
+                	device pci 1d.2 on end # USB UHCI
+                	device pci 1d.3 on end # USB UHCI
+                	device pci 1d.7 on end # USB2 EHCI
+                	device pci 1e.0 on end # PCI bridge
+			#device pci 1e.2 off end # AC'97 Audio 
+			#device pci 1e.3 off end # AC'97 Modem
+                        device pci 1f.0 on # LPC bridge
+                                chip superio/winbond/w83627thg
+					device pnp 2e.0 off		# Floppy
+					end
+					device pnp 2e.1 off		# Parport
+					end
+                                        device pnp 2e.2 on
+                                                 io 0x60 = 0x3f8
+                                                irq 0x70 = 4
+                                        end
+                                        device pnp 2e.3 on
+                                                 io 0x60 = 0x2f8
+                                                irq 0x70 = 3
+						irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
+                                        end
+					device pnp 2e.5 on		# Keyboard+Mouse
+						 io 0x60 = 0x60
+						 io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+						irq 0xf0 = 0x82		# HW accel A20.
+					end
+					device pnp 2e.7 on		# GPIO1, GAME, MIDI
+						 io 0x62 = 0x330
+						irq 0x70 = 9
+					end
+					device pnp 2e.8 on		# GPIO2
+						# all default
+					end
+					device pnp 2e.9 on		# GPIO3/4
+						irq 0x30 = 0x03		# does this work?
+						irq 0xf0 = 0xfb		# set inputs/outputs
+						irq 0xf1 = 0x66
+					end
+					device pnp 2e.a off		# ACPI
+					end
+					device pnp 2e.b on		# HWM
+						 io 0x60 = 0xa00
+						irq 0x70 = 0
+					end
+
+                                end
+                                chip superio/winbond/w83627thg
+                                        device pnp 4e.0 off		# Floppy
+					end
+					device pnp 4e.1 off		# Parport
+					end
+                                        device pnp 4e.2 on		# COM3
+                                                 io 0x60 = 0x3e8
+                                                irq 0x70 = 11
+                                        end
+                                        device pnp 4e.3 on		# COM4
+                                                 io 0x60 = 0x2e8
+                                                irq 0x70 = 10
+                                        end
+					device pnp 4e.5 off		# Keyboard
+					end
+					device pnp 4e.7 off		# GPIO1, GAME, MIDI
+					end
+					device pnp 4e.8 off		# GPIO2
+					end
+					device pnp 4e.9 off		# GPIO3/4
+					end
+					device pnp 4e.a off		# ACPI
+					end
+					device pnp 4e.b off		# HWM
+					end
+                                end
+
+                        end
+			#device pci 1f.1 off end # IDE
+                        device pci 1f.2 on end  # SATA
+                        device pci 1f.3 on end  # SMBus
+			#device pci 1f.4 off end # Realtek ID Codec
+                end
+        end
+end

Added: trunk/coreboot-v2/src/mainboard/kontron/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/kontron/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,48 @@
+choice
+        prompt "Mainboard model"
+        depends on VENDOR_KONTRON
+
+config BOARD_KONTRON_986LCD_M
+        bool "986LCD-M"
+        select ARCH_X86
+        select CPU_INTEL_CORE
+	select CPU_INTEL_SOCKET_MFCPGA478
+        select NORTHBRIDGE_INTEL_I945
+        select SOUTHBRIDGE_INTEL_I82801GX
+        select SUPERIO_WINBOND_W83627THG
+        select PIRQ_TABLE
+	select MMCONF_SUPPORT
+	select USE_PRINTK_IN_CAR
+        help
+          Kontron 986LCD-M Series mainboards
+endchoice
+
+config MAINBOARD_DIR
+	string
+	default kontron/986lcd-m
+	depends on BOARD_KONTRON_986LCD_M
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffdf8000
+	depends on BOARD_KONTRON_986LCD_M
+	
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+	depends on BOARD_KONTRON_986LCD_M
+
+config LB_CKS_RANGE_END
+	int
+	default 122
+	depends on BOARD_KONTRON_986LCD_M
+
+config LB_CKS_LOC
+	int
+        default 123
+	depends on BOARD_KONTRON_986LCD_M
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "986LCD-M"
+	depends on BOARD_KONTRON_986LCD_M

Added: trunk/coreboot-v2/src/mainboard/lippert/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/lippert/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/lippert/frontrunner/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/frontrunner/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/lippert/frontrunner/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,18 @@
+chip northbridge/amd/gx2
+  device pci_domain 0 on 
+    device pci 0.0 on end
+      chip southbridge/amd/cs5535
+        device pci 12.0 on
+        device pci 12.1 off end		# SMI
+        device pci 12.2 on  end		# IDE
+        device pci 12.3 off end 	# Audio
+        device pci 12.4 off end		# VGA
+      end
+    end
+  end
+
+  chip cpu/amd/model_gx2
+  end
+
+end
+

Added: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,89 @@
+chip northbridge/amd/lx
+  device pci_domain 0 on
+    device pci 1.0 on end		# Northbridge
+    device pci 1.1 on end		# Graphics
+    device pci 1.2 on end		# AES
+    chip southbridge/amd/cs5536		# Southbridge
+      # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
+      # SIRQ Mode = Active(Quiet) mode. Save power...
+      # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
+      # UARTs, etc IRQs. OK
+      register "lpc_serirq_enable"        = "0x000012DA"  # 00010010 11011010
+      register "lpc_serirq_polarity"      = "0x0000ED25"  # inverse of above
+      register "lpc_serirq_mode"          = "1"
+      register "enable_gpio_int_route"    = "0x0D0C0700"
+      register "enable_ide_nand_flash"    = "0"  # 0:ide mode, 1:flash
+      register "enable_USBP4_device"      = "0"  # 0: host, 1:device
+      register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+      register "com1_enable"              = "0"
+      register "com1_address"             = "0x3E8"
+      register "com1_irq"                 = "6"
+      register "com2_enable"              = "0"
+      register "com2_address"             = "0x2E8"
+      register "com2_irq"                 = "6"
+      register "unwanted_vpci[0]"         = "0"  # End of list has a zero
+      device pci 8.0 on end		# Slot4
+      device pci 9.0 on end		# Slot3
+      device pci a.0 on end		# Slot2
+      device pci b.0 on end		# Slot1
+      device pci c.0 on end		# IT8888
+      device pci e.0 on end		# Ethernet
+      device pci f.0 on			# ISA bridge
+        chip superio/ite/it8712f
+          device pnp 2e.0 off		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on		# Com1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.2 on		# Com2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.3 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.4 on		# EC
+            io 0x60 = 0x290
+            io 0x62 = 0x230
+            irq 0x70 = 9
+          end
+          device pnp 2e.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.6 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.7 on		# GPIO
+            io 0x62 = 0x1220
+            # io 0x64 = 0x1200
+          end
+          device pnp 2e.8 off		# MIDI
+            io 0x60 = 0x300
+            irq 0x70 = 9
+          end
+          device pnp 2e.9 off		# Game port
+            io 0x60 = 0x220
+          end
+          device pnp 2e.a off end	# CIR
+        end
+      end
+      device pci f.2 on end		# IDE controller
+      device pci f.3 on end		# Audio
+      device pci f.4 on end		# OHCI
+      device pci f.5 on end		# EHCI
+    end
+  end
+  # APIC cluster is late CPU init.
+  device apic_cluster 0 on
+    chip cpu/amd/model_lx
+      device apic 0 on end
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,90 @@
+chip northbridge/amd/lx
+  device pci_domain 0 on
+    device pci 1.0 on end				# Northbridge
+    device pci 1.1 on end				# Graphics
+    device pci 1.2 on end				# AES
+    chip southbridge/amd/cs5536
+      # IRQ 12 and 1 unmasked, keyboard and mouse IRQs. OK
+      # SIRQ Mode = Active(Quiet) mode. Save power....
+      # Invert mask = IRQ 12 and 1 are active high. Keyboard and mouse,
+      # UARTs, etc IRQs. OK
+      register "lpc_serirq_enable"        = "0x000012DA" # 00010010 11011010
+      register "lpc_serirq_polarity"      = "0x0000ED25" # inverse of above
+      register "lpc_serirq_mode"          = "1"
+      register "enable_gpio_int_route"    = "0x0D0C0700"
+      register "enable_ide_nand_flash"    = "0" # 0:ide mode, 1:flash
+      register "enable_USBP4_device"      = "0" # 0:host, 1:device
+      register "enable_USBP4_overcurrent" = "0" # 0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+      register "com1_enable"              = "0"
+      register "com1_address"             = "0x3E8"
+      register "com1_irq"                 = "6"
+      register "com2_enable"              = "0"
+      register "com2_address"             = "0x2E8"
+      register "com2_irq"                 = "6"
+      register "unwanted_vpci[0]"         = "0x80007B00" # Audio: 1<<31 + Device 0x0F<<11 + Function 3<<8
+      register "unwanted_vpci[1]"         = "0" # End of list has a zero
+      device pci 8.0 on end		# Slot4
+      device pci 9.0 on end		# Slot3
+      device pci a.0 on end		# Slot2
+      device pci b.0 on end		# Slot1
+      device pci c.0 on end		# IT8888
+      device pci e.0 on end		# Ethernet
+      device pci f.0 on			# ISA Bridge
+        chip superio/ite/it8712f
+          device pnp 2e.0 off		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on		# Com1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.2 on		# Com2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.3 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.4 on		# EC
+            io 0x60 = 0x290
+            io 0x62 = 0x230
+            irq 0x70 = 9
+          end
+          device pnp 2e.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.6 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.7 on		# GPIO
+            io 0x62 = 0x1220
+            io 0x64 = 0x1200
+          end
+          device pnp 2e.8 off		# MIDI
+            io 0x60 = 0x300
+            irq 0x70 = 9
+          end
+          device pnp 2e.9 off		# Game port
+            io 0x60 = 0x220
+          end
+          device pnp 2e.a off end	# CIR
+        end
+      end
+      device pci f.2 on end		# IDE
+      device pci f.3 off end		# Audio
+      device pci f.4 on end		# OHCI
+      device pci f.5 on end		# EHCI
+    end
+  end
+  # APIC cluster is late CPU init.
+  device apic_cluster 0 on
+    chip cpu/amd/model_lx
+      device apic 0 on end
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/mitac/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/mitac/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/mitac/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/motorola/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/motorola/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/motorola/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/motorola/sandpoint/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/motorola/sandpoint/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/motorola/sandpoint/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,30 @@
+##
+## Config file for the Motorola Sandpoint III development system.
+## Note that this has only been tested with the Altimus 7410 PMC.
+##
+
+##
+## Early board initialization, called from ppc_main()
+##
+initobject init.o
+initobject clock.o
+
+##
+## Stage 2 timer support
+##
+object clock.o
+
+##
+## Set our CONFIG_ARCH
+##
+arch ppc end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+dir nvram
+dir flash
+
+addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
+makedefine CFLAGS += -g

Added: trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/motorola/sandpointx3_altimus_mpc7410/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,26 @@
+chip northbridge/motorola/mpc107
+	device pci_domain 0 on
+		device pci 0.0 on end
+		device pci b.0 on
+			chip southbridge/winbond/w83c553
+				chip superio/nsc/pc97307
+					device pnp 15c.0 on end # Kyeboard
+					device pnp 15c.1 on end # Mouse
+					device pnp 15c.2 on end # Real-time Clock
+					device pnp 15c.3 on end # Floppy
+					device pnp 15c.4 on end # Parallel port
+					device pnp 15c.5 on end # com2
+					device pnp 15c.6 on end # com1
+					device pnp 15c.7 on end # gpio
+					device pnp 15c.8 on end # Power management
+				end
+			end
+		end # pci to isa bridge
+		device pci b.1 on end # pci ide controller
+	end
+	device cpu_bus 0 on
+		chip cpu/ppc/mpc74xx
+			device cpu 0 on end
+		end
+	end
+end

Added: trunk/coreboot-v2/src/mainboard/msi/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/msi/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,41 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+choice
+	prompt "Mainboard model"
+	depends on VENDOR_MSI
+
+config BOARD_MSI_MS6178
+	bool "MS-6178"
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_PGA370
+	select NORTHBRIDGE_INTEL_I82810
+	select SOUTHBRIDGE_INTEL_I82801XX
+	select SUPERIO_WINBOND_W83627HF
+	select PIRQ_TABLE
+	help
+	  MSI MS-6178 mainboard.
+endchoice
+
+config MAINBOARD_DIR
+	string
+	default msi/ms6178
+	depends on BOARD_MSI_MS6178
+

Added: trunk/coreboot-v2/src/mainboard/msi/ms6119/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6119/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6119/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,60 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.9 on		# GPIO 3
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/msi/ms6147/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6147/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6147/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,60 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/winbond/w83977tf	# Super I/O
+          device pnp 3f0.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 3f0.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 3f0.2 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 3f0.3 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 3f0.5 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# PS/2 keyboard interrupt
+            irq 0x72 = 12		# PS/2 mouse interrupt
+          end
+          device pnp 3f0.7 on		# GPIO 1
+          end
+          device pnp 3f0.8 on		# GPIO 2
+          end
+          device pnp 3f0.9 off		# GPIO 3
+          end
+          device pnp 3f0.a on		# ACPI
+          end
+        end
+      end
+      device pci 7.1 on end		# IDE
+      device pci 7.2 on end		# USB
+      device pci 7.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "1"
+      register "ide0_drive1_udma33_enable" = "1"
+      register "ide1_drive0_udma33_enable" = "1"
+      register "ide1_drive1_udma33_enable" = "1"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/msi/ms6178/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6178/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6178/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+driver-y += mainboard.o
+
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+
+initobj-y += ../../../arch/i386/init/entry.o
+initobj-y += ../../../cpu/intel/model_6ex/car.o # FIXME. romcc.
+# initobj-y += ../../../arch/i386/init/rombootstrap.o
+# initobj-y += ../../../cpu/intel/model_6ex/disable_car.o
+initobj-y += ../../../pc80/mc146818rtc_early.o
+initobj-y += ../../../arch/i386/lib/console.o
+initobj-y += ../../../arch/i386/lib/console_printk.o
+# initobj-y += ../../../ram/ramtest.o # FIXME
+initobj-y += ../../../southbridge/intel/i82801xx/i82801xx_early_smbus.o
+initobj-y += ../../../southbridge/intel/i82801xx/i82801xx_reset.o
+initobj-y += ../../../superio/winbond/w83627hf/w83627hf_early_serial.o
+initobj-y += ../../../northbridge/intel/i82810/raminit.o
+
+ifdef POST_EVALUATION
+
+# FIXME: Drop DCACHE_RAM_BASE/DCACHE_RAM_SIZE, only here to make it build.
+MAINBOARD_OPTIONS=\
+	-DCONFIG_USE_PRINTK_IN_CAR=1 \
+	-DCONFIG_HAVE_HIGH_TABLES=1 \
+	-DCONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0 \
+	-DCONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0 \
+	-DCONFIG_MAINBOARD_VENDOR=\"MSI\" \
+	-DCONFIG_MAINBOARD_PART_NUMBER=\"MS-6178\" \
+	-DCONFIG_DCACHE_RAM_BASE=0xffdf8000 \
+	-DCONFIG_DCACHE_RAM_SIZE=0x8000
+
+endif
+

Added: trunk/coreboot-v2/src/mainboard/msi/ms6178/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms6178/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/msi/ms6178/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,69 @@
+chip northbridge/intel/i82810			# Northbridge
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/intel/socket_PGA370		# CPU
+      device apic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on
+    device pci 0.0 on end			# Host bridge
+    device pci 1.0 off				# Onboard video
+      # chip drivers/pci/onboard
+      #   device pci 1.0 on end
+      #   register "rom_address" = "0xfff80000"
+      # end
+    end
+    chip southbridge/intel/i82801xx		# Southbridge
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
+      device pci 1e.0 on end			# PCI bridge
+      device pci 1f.0 on			# ISA/LPC bridge
+        chip superio/winbond/w83627hf		# Super I/O
+          device pnp 2e.0 on			# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on			# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 2e.2 on			# Com1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.3 on			# Com2 (only header on board)
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.5 on			# PS/2 keyboard/mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1			# Keyboard interrupt
+            irq 0x72 = 12			# Mouse interrupt
+          end
+          device pnp 2e.6 on end		# Consumer IR (TODO)
+          device pnp 2e.7 on			# Game port / MIDI / GPIO 1
+            io 0x60 = 0x201
+            io 0x62 = 0x330
+            irq 0x70 = 9
+          end
+          device pnp 2e.8 on end		# GPIO 2
+          device pnp 2e.9 on end		# GPIO 3
+          device pnp 2e.a on end		# ACPI
+          device pnp 2e.b on			# Hardware monitor
+            io 0x60 = 0x290
+            irq 0x70 = 5
+          end
+        end
+      end
+      device pci 1f.1 on end			# IDE
+      device pci 1f.2 on end			# USB
+      device pci 1f.3 on end			# SMBus
+      device pci 1f.5 on end			# AC'97 audio
+      device pci 1f.6 on end			# AC'97 modem
+    end
+  end
+end
+

Added: trunk/coreboot-v2/src/mainboard/msi/ms7135/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7135/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7135/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,76 @@
+chip northbridge/amd/amdk8/root_complex		# Root complex
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/amd/socket_754			# Socket 754 CPU
+      device apic 0 on end			# APIC
+    end
+  end
+
+  device pci_domain 0 on			# PCI domain
+    chip northbridge/amd/amdk8			# mc0
+      device pci 18.0 on			# Northbridge
+        # Devices on link 0, link 0 == LDT 0
+        chip southbridge/nvidia/ck804		# Southbridge
+          device pci 0.0 on end			# HT
+          device pci 1.0 on			# LPC
+            chip superio/winbond/w83627thf	# Super I/O
+              device pnp 4e.0 on		# Floppy
+                io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 4e.1 on		# Parallel port
+                io 0x60 = 0x378
+                irq 0x70 = 7
+              end
+              device pnp 4e.2 on		# Com1
+                io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 4e.3 on		# Com2
+                io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 4e.5 on		# PS/2 keyboard
+                io 0x60 = 0x60
+                io 0x62 = 0x64
+                irq 0x70 = 1
+                irq 0x72 = 12
+              end
+              device pnp 4e.7 off end		# Game, MIDI, GPIO 1, GPIO 5
+              device pnp 4e.8 off end		# GPIO 2
+              device pnp 4e.9 off end		# GPIO 3, GPIO 4
+              device pnp 4e.a off end		# ACPI
+              device pnp 4e.b on		# Hardware monitor
+                io 0x60 = 0x290
+                irq 0x70 = 0
+              end
+            end
+          end
+          device pci 1.1 on end			# SMbus
+          device pci 2.0 on end			# USB 1.1
+          device pci 2.1 on end			# USB 2
+          device pci 4.0 on end			# Onboard audio (ACI)
+          device pci 4.1 off end		# Onboard modem (MCI) -- not wired out
+          device pci 6.0 on end			# IDE
+          device pci 7.0 on end			# SATA 1
+          device pci 8.0 on end			# SATA 0
+          device pci 9.0 on end			# PCI
+          device pci a.0 on end			# NIC
+          device pci b.0 off end		# PCI E 3 -- not wired out
+          device pci c.0 off end		# PCI E 2 -- not wired out
+          device pci d.0 on end			# PCI E 1
+          device pci e.0 on end			# PCI E 0
+          register "ide0_enable" = "1"
+          register "ide1_enable" = "1"
+          register "sata0_enable" = "1"
+          register "sata1_enable" = "1"
+          # register "mac_eeprom_smbus" = "3"
+          # register "mac_eeprom_addr" = "0x51"
+        end
+      end
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/msi/ms7260/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7260/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7260/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,157 @@
+chip northbridge/amd/amdk8/root_complex		# Root complex
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/amd/socket_AM2			# CPU
+      device apic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on			# PCI domain
+    chip northbridge/amd/amdk8			# Northbridge / mc0
+      device pci 18.0 on
+        # Devices on link 0, link 0 == LDT 0
+        chip southbridge/nvidia/mcp55		# Southbridge
+          device pci 0.0 on end			# HT
+          device pci 1.0 on			# LPC
+            chip superio/winbond/w83627ehg	# Super I/O
+              device pnp 4e.0 on		# Floppy
+                io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 4e.1 on		# Parallel port
+                io 0x60 = 0x378
+                irq 0x70 = 7
+              end
+              device pnp 4e.2 on		# Com1
+                io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 4e.3 on		# Com2 / IrDA
+                io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 4e.5 on		# PS/2 keyboard
+                io 0x60 = 0x60
+                io 0x62 = 0x64
+                irq 0x70 = 1			# PS/2 keyboard IRQ
+                irq 0x72 = 12			# PS/2 mouse IRQ
+              end
+              device pnp 4e.6 off		# Serial flash interface
+                # io 0x62 = 0x100
+              end
+              device pnp 4e.7 off		# GPIO1/6, game port, MIDI port
+                # io 0x60 = 0x220		# Datasheet: 0x201
+                # io 0x62 = 0x300		# Datasheet: 0x330
+                # irq 0x70 = 9
+              end
+              device pnp 4e.8 off		# WDTO#, PLED
+              end
+              device pnp 4e.9 off		# GPIO2/3/4/5, SUSLED
+              end
+              device pnp 4e.a off		# ACPI
+              end
+              device pnp 4e.b on		# HWM (for lm-sensors)
+                io 0x60 = 0xa10
+              end
+            end
+          end
+          device pci 1.1 on			# SM 0
+            chip drivers/generic/generic	# DIMM 0-0-0
+              device i2c 50 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-0-1
+              device i2c 51 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-0
+              device i2c 52 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-1
+              device i2c 53 on end
+            end
+            # TODO: Needed?
+            # chip drivers/generic/generic	# DIMM 1-0-0
+            #   device i2c 54 on end
+            # end
+            # chip drivers/generic/generic	# DIMM 1-0-1
+            #   device i2c 55 on end
+            # end
+            # chip drivers/generic/generic	# DIMM 1-1-0
+            #   device i2c 56 on end
+            # end
+            # chip drivers/generic/generic	# DIMM 1-1-1
+            #   device i2c 57 on end
+            # end
+          end
+          # TODO: Check if the stuff below is correct / needed.
+          device pci 1.1 on			# SM 1
+            # PCI device SMBus address will depend on addon PCI device,
+            # do we need to scan_smbus_bus?
+
+            # chip drivers/generic/generic	# PCIXA Slot1
+            #   device i2c 50 on end
+            # end
+            # chip drivers/generic/generic	# PCIXB Slot1
+            #   device i2c 51 on end
+            # end
+            # chip drivers/generic/generic	# PCIXB Slot2
+            #   device i2c 52 on end
+            # end
+            # chip drivers/generic/generic	# PCI Slot1
+            #   device i2c 53 on end
+            # end
+            # chip drivers/generic/generic	# Master MCP55 PCI-E
+            #   device i2c 54 on end
+            # end
+            # chip drivers/generic/generic	# Slave MCP55 PCI-E
+            #   device i2c 55 on end
+            # end
+            chip drivers/generic/generic	# MAC EEPROM
+              device i2c 51 on end
+            end
+          end
+          device pci 2.0 on end			# USB 1.1
+          device pci 2.1 on end			# USB 2
+          device pci 4.0 on end			# IDE
+          device pci 5.0 on end			# SATA 0
+          device pci 5.1 on end			# SATA 1
+          device pci 5.2 off end		# SATA 2 (N/A on this board)
+          device pci 6.0 on end			# PCI
+          device pci 6.1 on end			# AZA (HD Audio)
+          device pci 8.0 on end			# NIC
+          device pci 9.0 off end		# NIC (N/A on this board)
+          device pci a.0 off end		# PCI E 5 (N/A on this board?)
+          device pci b.0 on end			# PCI E 4
+          device pci c.0 on end			# PCI E 3
+          device pci d.0 on end			# PCI E 2
+          device pci e.0 on end			# PCI E 1
+          device pci f.0 on end			# PCI E 0
+          register "ide0_enable" = "1"
+          register "sata0_enable" = "1"
+          register "sata1_enable" = "1"
+          # TODO: Check the two lines below.
+          register "mac_eeprom_smbus" = "3"	# 1: SMBus under 2e.8, 2: SM0 3: SM1
+          register "mac_eeprom_addr" = "0x51"
+        end
+      end
+      device pci 18.0 on end			# Link 1
+      device pci 18.0 on end
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+    end
+  end
+
+# TODO
+#  chip drivers/generic/debug
+#    device pnp 0.0 off end			# chip name
+#    device pnp 0.1 on end			# pci_regs_all
+#    device pnp 0.2 on end			# mem
+#    device pnp 0.3 off end			# cpuid
+#    device pnp 0.4 on end			# smbus_regs_all
+#    device pnp 0.5 off end			# dual core msr
+#    device pnp 0.6 off end			# cache size
+#    device pnp 0.7 off end			# tsc
+#    device pnp 0.8 off end			# io
+#    device pnp 0.9 off end			# io
+#  end
+
+end

Added: trunk/coreboot-v2/src/mainboard/msi/ms9185/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9185/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9185/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,120 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+       device pci_domain 0 on
+               chip northbridge/amd/amdk8
+                       device pci 18.0 on end
+                       device pci 18.0 on end
+                       device pci 18.0 on #  northbridge
+                              #  devices on link 0
+                                chip southbridge/broadcom/bcm5780 # HT2000
+                                        device pci 0.0 on end   # PXB 1 0x0130
+                                        device pci 1.0 on       # PXB 2 0x0130
+                                                device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
+                                                device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
+                                        end
+                                        device pci 2.0 on end # PCI E 1  #0x0132
+                                       device pci 3.0 on end # PCI E 2
+                                       device pci 4.0 on end # PCI E 3
+                                       device pci 5.0 on end # PCI E 4
+                                end
+                                chip southbridge/broadcom/bcm5785 # HT1000
+                                        device pci 0.0 on  # HT PXB  0x0036
+                                                device pci d.0 on end # PPBX 0x0104
+                                                device pci e.0 on end # SATA 0x024a
+                                                device pci e.1 on end # SATA 0x024a bx_a001
+                                                device pci e.2 on end # SATA 0x024a bx_a001
+                                                device pci e.3 on end # SATA 0x024a bx_a001
+                                        end
+                                        device pci 1.0 on # Legacy  pci main  0x0205
+                                       end
+                                        device pci 1.1 on end # IDE        0x0214
+                                        device pci 1.2 on     # LPC        0x0234
+                                                chip superio/nsc/pc87417
+                                                        device  pnp 2e.0 off  # Floppy
+                                                                 io 0x60 = 0x3f0
+                                                                irq 0x70 = 6
+                                                                drq 0x74 = 2
+                                                        end
+                                                        device pnp 2e.1 off  # Parallel Port
+                                                                 io 0x60 = 0x378
+                                                                irq 0x70 = 7
+                                                        end
+                                                        device pnp 2e.2 off # Com 2
+                                                                 io 0x60 = 0x2f8
+                                                                irq 0x70 = 3
+                                                        end
+                                                        device pnp 2e.3 on  # Com 1
+                                                                 io 0x60 = 0x3f8
+                                                                irq 0x70 = 4
+                                                        end
+                                                        device pnp 2e.4 off end # SWC
+                                                        device pnp 2e.5 off end # Mouse
+                                                        device pnp 2e.6 on  # Keyboard
+                                                                 io 0x60 = 0x60
+                                                                 io 0x62 = 0x64
+                                                                irq 0x70 = 1
+                                                        end
+                                                        device pnp 2e.7 off end # GPIO
+                                                        device pnp 2e.f off end # XBUS
+                                                        device pnp 2e.10 on #RTC
+                                                                io 0x60 = 0x70
+                                                                io 0x62 = 0x72
+                                                       end
+                                                end
+                                        end
+                                        device pci 1.3 on end # WDTimer    0x0238
+                                        device pci 1.4 on end # XIOAPIC0   0x0235
+                                        device pci 1.5 on end # XIOAPIC1
+                                        device pci 1.6 on end # XIOAPIC2
+                                        device pci 2.0 on end # USB        0x0223
+                                        device pci 2.1 on end # USB
+                                        device pci 2.2 on end # USB
+                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,),
+                                        chip drivers/pci/onboard
+                                              device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
+                                                                    # if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
+                                              register "rom_address" = "0xfff80000"
+                                        end
+                                       #bx_a013+ start
+                                       #chip drivers/pci/onboard    #SATA2
+                                       #       device pci 5.0 on end
+                                       #       device pci 5.1 on end
+                                       #       device pci 5.2 on end
+                                       #       device pci 5.3 on end
+                                       #end
+                                       #bx_a013+ end
+
+                                end
+                                        #when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
+#                                        chip drivers/pci/onboard
+#                                              device pci 0.0 on end # fake, will be disabled
+#                                        end
+#                                        chip drivers/pci/onboard
+#                                              device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
+#                                              register "rom_address" = "0xfff80000"
+#                                        end
+
+                       end #  device pci 18.0
+                       device pci 18.1 on end
+                       device pci 18.2 on end
+                       device pci 18.3 on end
+               end # amdk8
+       end #pci_domain
+#        chip drivers/generic/debug
+#              device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 off end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 off end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#                device pnp 0.7 off end # tsc
+#       end
+
+end
+
+

Added: trunk/coreboot-v2/src/mainboard/msi/ms9282/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,188 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+
+       device pci_domain 0 on
+               chip northbridge/amd/amdk8 #mc0
+                       device pci 18.0 on #  northbridge
+                               #  devices on link 0, link 0 == LDT 0
+                               chip southbridge/nvidia/mcp55
+                                       device pci 0.0 on end   # HT
+                                       device pci 1.0 on # LPC
+                                               chip superio/winbond/w83627ehg
+                                                       device pnp 2e.0 on #  Floppy
+                                                               io 0x60 = 0x3f0
+                                                               irq 0x70 = 6
+                                                               drq 0x74 = 2
+                                                       end
+                                                       device pnp 2e.1 off #  Parallel Port
+                                                               io 0x60 = 0x378
+                                                               irq 0x70 = 7
+                                                       end
+                                                       device pnp 2e.2 on #  Com1
+                                                               io 0x60 = 0x3f8
+                                                               irq 0x70 = 4
+                                                       end
+                                                       device pnp 2e.3 off #  Com2
+                                                               io 0x60 = 0x2f8
+                                                               irq 0x70 = 3
+                                                       end
+                                                       device pnp 2e.5 on #  Keyboard
+                                                               io 0x60 = 0x60
+                                                               io 0x62 = 0x64
+                                                               irq 0x70 = 1
+                                                               irq 0x72 = 12
+                                                       end
+                                                       device pnp 2e.6 off #  SERIAL_FALSH
+                                                               io 0x60 = 0x100
+                                                       end
+                                                       device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                                                               io 0x60 = 0x220
+                                                               io 0x62 = 0x300
+                                                               irq 0x70 = 9
+                                                       end
+                                                       device pnp 2e.8 off end #  WDTO_PLED
+                                                       device pnp 2e.9 off end #  GPIO2_GPIO3_GPIO4_GPIO5
+                                                       device pnp 2e.a off end #  ACPI
+                                                       device pnp 2e.b on #  HW Monitor
+                                                               io 0x60 = 0x290
+                                                               irq 0x70 = 5
+                                                       end
+                                               end
+                                       end
+                                        device pci 1.1 on # SM 0
+                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
+                                                       device i2c 70 on  #0 pca9554 1
+                                                               chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                               chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 54 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 55 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 56 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 57 on end
+                                                                end
+                                                       end
+                                                       device i2c 70 on  #0 pca9554 2
+                                                               chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 50 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 51 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 52 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 53 on end
+                                                                end
+                                                               chip drivers/generic/generic #dimm 0-0-0
+                                                                        device i2c 54 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-0-1
+                                                                        device i2c 55 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-0
+                                                                        device i2c 56 on end
+                                                                end
+                                                                chip drivers/generic/generic #dimm 0-1-1
+                                                                        device i2c 57 on end
+                                                                end
+                                                       end
+                                               end
+                                       end
+                                       device pci 1.1 on # SM 1
+                                               chip drivers/i2c/i2cmux2 # pca9554 smbus mux
+                                                       device i2c 72 on     #pca9554 channle1
+                                                               chip drivers/i2c/adm1027   #HWM ADT7476 1
+                                                                       device i2c 2e on end
+                                                               end
+                                                       end
+                                                       device i2c 72 on     #pca9545 channel 2
+                                                               chip drivers/i2c/adm1027   #HWM ADT7463
+                                                                       device i2c 2e on end
+                                                               end
+                                                       end
+                                                       device i2c 72 on end  #pca9545 channel 3
+                                                       device i2c 72 on      #pca9545 channel 4
+                                                               chip drivers/i2c/adm1027   #HWM ADT7476 2
+                                                                       device i2c 2e on end
+                                                               end
+                                                       end
+                                               end
+                                       end
+
+                                       device pci 2.0 on end # USB 1.1
+                                       device pci 2.1 on end # USB 2
+                                       device pci 4.0 on  end # IDE
+                                               device pci 5.0 on  end # SATA 0
+                                       device pci 5.1 on  end # SATA 1
+                                       device pci 5.2 on  end # SATA 2
+                                       device pci 6.0 on  #P2P
+                                               chip drivers/pci/onboard
+                                                       device pci 4.0 on end
+                                                       register "rom_address" = "0xfff80000"
+                                               end
+                                       end # P2P
+                                       device pci 7.0 on end # reserve
+                                       device pci 8.0 on end # MAC0
+                                       device pci 9.0 on end # MAC1
+                                       device pci a.0 on
+                                               device pci 0.0 on
+                                                       chip drivers/pci/onboard
+                                                               device pci 4.0 on end  #pci_E lan1
+                                                               device pci 4.1 on end  #pci_E lan2
+                                                       end
+                                               end
+                                       end # 0x376
+                                               device pci b.0 on  end # PCI E 0x374
+                                       device pci c.0 on  end
+                                       device pci d.0 on   #SAS
+                                               chip drivers/pci/onboard
+                                                       device pci 0.0 on end
+                                               end
+                                       end # PCI E 1 0x378
+                                       device pci e.0 on end # PCI E 0 0x375
+                                       device pci f.0 on end   #PCI E 0x377  pci_E slot
+                                       register "ide0_enable" = "1"
+                                       register "ide1_enable" = "1"
+                                       register "sata0_enable" = "1"
+                                       register "sata1_enable" = "1"
+                               end
+                       end #  device pci 18.0
+                       device pci 18.0 on end # Link 1
+                       device pci 18.0 on end
+                       device pci 18.1 on end
+                       device pci 18.2 on end
+                       device pci 18.3 on end
+               end #mc0
+
+       end # pci_domain
+
+#        chip drivers/generic/debug
+#                device pnp 0.0 off end
+#                device pnp 0.1 off end
+#                device pnp 0.2 off end
+#                device pnp 0.3 off end
+#                device pnp 0.4 off end
+#              device pnp 0.5 on end
+#        end
+end # root_complex

Added: trunk/coreboot-v2/src/mainboard/nec/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/nec/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/nec/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/nec/powermate2000/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/nec/powermate2000/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/nec/powermate2000/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,59 @@
+chip northbridge/intel/i82810			# Northbridge
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/intel/socket_PGA370		# CPU
+      device apic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on
+    device pci 0.0 on end			# Host bridge
+    device pci 1.0 off				# Onboard video
+      # chip drivers/pci/onboard
+      #   device pci 1.0 on end
+      #   register "rom_address" = "0xfff80000"
+      # end
+    end
+    chip southbridge/intel/i82801xx		# Southbridge
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
+      device pci 1e.0 on end			# PCI bridge
+      device pci 1f.0 on			# ISA/LPC bridge
+        chip superio/smsc/smscsuperio		# Super I/O (SMSC LPC47B27x)
+          device pnp 2e.0 on			# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.3 on			# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 2e.4 on			# Com1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.5 off end		# Com2 (N/A)
+          device pnp 2e.7 on			# PS/2 keyboard
+            irq 0x70 = 1
+            irq 0x72 = 0
+          end
+          device pnp 2e.9 off end		# Game port (N/A)
+          device pnp 2e.a on			# Power-management events (PME)
+            io 0x60 = 0x800
+          end
+          device pnp 2e.b on			# MIDI port
+            io 0x60 = 0x330
+            irq 0x70 = 5
+          end
+        end
+      end
+      device pci 1f.1 on end			# IDE
+      device pci 1f.2 on end			# USB
+      device pci 1f.3 on end			# SMBus
+      device pci 1f.5 on end			# AC'97 audio
+      device pci 1f.6 off end			# AC'97 modem (N/A)
+    end
+  end
+end
+

Added: trunk/coreboot-v2/src/mainboard/newisys/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/newisys/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/newisys/khepri/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/khepri/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/newisys/khepri/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,92 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+		chip cpu/amd/socket_940
+			device apic 1 on end
+		end
+	end
+
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on end # LDT 0 
+			device pci 18.0 on     # LDT 1
+				chip southbridge/amd/amd8131
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 on end
+						device pci 1.0 on end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 on #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 on #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	        			device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+                	        			device pnp 2e.8 off end #  GPIO2
+                	        			device pnp 2e.9 off end #  GPIO3
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on end 
+					device pci 1.5 on end
+					device pci 1.6 on end
+				end
+			end # LDT1
+			device pci 18.0 on end # LDT2
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+		chip northbridge/amd/amdk8
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.1 on end
+			device pci 19.2 on end
+			device pci 19.3 on end
+		end
+	end 
+end
+

Added: trunk/coreboot-v2/src/mainboard/nvidia/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/nvidia/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/nvidia/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,178 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_F
+			device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/nvidia/mcp55
+					device pci 0.0 on end   # HT
+					device pci 1.0 on # LPC
+						chip superio/winbond/w83627ehg
+							device pnp 2e.0 off #  Floppy
+					 			io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off #  Parallel Port
+					 			io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 on #  Com1
+					 			io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.3 off #  Com2
+					 			io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.5 on #  Keyboard
+					 			io 0x60 = 0x60
+					 			io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp 2e.6 off  # SFI
+					 			io 0x62 = 0x100
+							end
+							device pnp 2e.7 off #  GPIO_GAME_MIDI
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.8 off end #  WDTO_PLED
+							device pnp 2e.9 off end #  GPIO_SUSLED
+							device pnp 2e.a off end #  ACPI
+							device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+							end
+						end
+					end
+					device pci 1.1 on # SM 0
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-0
+							device i2c 54 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-1
+							device i2c 55 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-0
+							device i2c 56 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-1
+							device i2c 57 on end
+						end
+					end # SM
+					device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#						chip drivers/generic/generic #PCIXA Slot1
+#							device i2c 50 on end
+#						end
+#						chip drivers/generic/generic #PCIXB Slot1
+#							device i2c 51 on end
+#						end
+#						chip drivers/generic/generic #PCIXB Slot2
+#							device i2c 52 on end
+#						end
+#						chip drivers/generic/generic #PCI Slot1
+#							device i2c 53 on end
+#						end
+#						chip drivers/generic/generic #Master MCP55 PCI-E
+#							device i2c 54 on end
+#						end
+#						chip drivers/generic/generic #Slave MCP55 PCI-E
+#							device i2c 55 on end
+#						end
+						chip drivers/generic/generic #MAC EEPROM
+							device i2c 51 on end
+						end
+
+					end # SM
+					device pci 2.0 on end # USB 1.1
+					device pci 2.1 on end # USB 2
+					device pci 4.0 on end # IDE
+					device pci 5.0 on end # SATA 0
+					device pci 5.1 on end # SATA 1
+					device pci 5.2 on end # SATA 2
+					device pci 6.0 on end # PCI
+					device pci 6.1 on end # AZA
+					device pci 8.0 on end # NIC
+					device pci 9.0 on end # NIC
+		       			device pci a.0 on end # PCI E 5
+		       			device pci b.0 off end # PCI E 4
+					device pci c.0 off end # PCI E 3
+					device pci d.0 on end # PCI E 2
+					device pci e.0 off end # PCI E 1
+		       			device pci f.0 on end # PCI E 0
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0
+			device pci 18.0 on end # Link 1
+			device pci 18.0 on
+				#  devices on link 2, link 2 == LDT 2
+				chip southbridge/nvidia/mcp55
+					device pci 0.0 on end   # HT
+					device pci 1.0 on end  # LPC
+					device pci 1.1 on end # SM 0
+					device pci 2.0 off end # USB 1.1
+					device pci 2.1 off end # USB 2
+					device pci 4.0 off end # IDE
+					device pci 5.0 on end # SATA 0
+					device pci 5.1 on end # SATA 1
+					device pci 5.2 on end # SATA 2
+					device pci 6.0 off end # PCI
+					device pci 6.1 off end # AZA
+					device pci 8.0 on end # NIC
+					device pci 9.0 on end # NIC
+		       			device pci a.0 on end # PCI E 5
+		       			device pci b.0 off end # PCI E 4
+					device pci c.0 off end # PCI E 3
+					device pci d.0 on end # PCI E 2
+					device pci e.0 on end # PCI E 1
+		       			device pci f.0 on end # PCI E 0
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end # device pci 18.0
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+
+	end # PCI domain
+
+#       chip drivers/generic/debug
+#		device pnp 0.0 off end # chip name
+#		device pnp 0.1 on end # pci_regs_all
+#		device pnp 0.2 on end # mem
+#		device pnp 0.3 off end # cpuid
+#		device pnp 0.4 on end # smbus_regs_all
+#		device pnp 0.5 off end # dual core msr
+#		device pnp 0.6 off end # cache size
+#		device pnp 0.7 off end # tsc
+#		device pnp 0.8 off  end # io
+#		device pnp 0.9 off end # io
+#       end
+end #root_complex

Added: trunk/coreboot-v2/src/mainboard/olpc/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/olpc/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/olpc/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/olpc/btest/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/olpc/btest/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/olpc/btest/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,45 @@
+chip northbridge/amd/gx2
+	register "irqmap" = "0xaa5b"
+	register "setupflash" = "0"
+	device apic_cluster 0 on
+		chip cpu/amd/model_gx2
+			device apic 0 on end
+		end
+	end
+  	device pci_domain 0 on 
+    		device pci 1.0 on end
+		device pci 1.1 on end
+      		chip southbridge/amd/cs5536
+		# 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002
+		# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+		# 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080.
+		# Frame Pulse Width = 4clocks
+		# IRQ Data Frames = 17Frames
+		# SIRQ Mode = continous , It would be better if the EC could operate in
+		# Active(Quiet) mode. Save power....
+		# SIRQ Enable = Enabled
+		# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK 
+			#register "lpc_irq" = "0x00001002"
+			#register "lpc_serirq_enable" = "0xEFFD0080"
+			#register "enable_gpio0_inta" = "1"
+			#register "enable_ide_nand_flash" = "1"
+			#register "enable_uarta" = "1"
+			#register "enable_USBP4_host" = "1"
+			#register "audio_irq" = "5"
+			#register "usbf4_irq" = "10"
+			#register "usbf5_irq" = "10"
+			#register "usbf6_irq" = "0"
+			#register "usbf7_irq" = "0"
+        		device pci d.0 on end	# Realtek 8139 LAN
+        		device pci f.0 on end	# ISA Bridge
+        		device pci f.2 on end	# IDE Controller
+        		device pci f.3 on end 	# Audio
+        		device pci f.4 on end	# OHCI
+			device pci f.5 on end	# EHCI
+			register "unwanted_vpci[0]" = "0x80007E00"	# USB/UDC
+			register "unwanted_vpci[1]" = "0x80007F00"	# USB/OTG
+			register "unwanted_vpci[2]" = "0"	# End of list has a zero
+      		end
+    	end
+end
+

Added: trunk/coreboot-v2/src/mainboard/olpc/rev_a/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/olpc/rev_a/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/olpc/rev_a/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,45 @@
+chip northbridge/amd/gx2
+	register "irqmap" = "0xaa5b"
+	register "setupflash" = "0"
+	device apic_cluster 0 on
+		chip cpu/amd/model_gx2
+			device apic 0 on end
+		end
+	end
+  	device pci_domain 0 on 
+    		device pci 1.0 on end
+		device pci 1.1 on end
+      		chip southbridge/amd/cs5536
+		# 0x51400025 (IRQ Mapper LPC Mask)= 0x00001002
+		# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+		# 0x5140004E (LPC Serial IRQ Control) = 0xEFFD0080.
+		# Frame Pulse Width = 4clocks
+		# IRQ Data Frames = 17Frames
+		# SIRQ Mode = continous , It would be better if the EC could operate in
+		# Active(Quiet) mode. Save power....
+		# SIRQ Enable = Enabled
+		# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK 
+			#register "lpc_irq" = "0x00001002"
+			#register "lpc_serirq_enable" = "0xEFFD0080"
+			#register "enable_gpio0_inta" = "1"
+			#register "enable_ide_nand_flash" = "1"
+			#register "enable_uarta" = "1"
+			#register "enable_USBP4_host" = "1"
+			#register "audio_irq" = "5"
+			#register "usbf4_irq" = "10"
+			#register "usbf5_irq" = "10"
+			#register "usbf6_irq" = "0"
+			#register "usbf7_irq" = "0"
+        		device pci d.0 on end	# Realtek 8139 LAN
+        		device pci f.0 on end	# ISA Bridge
+        		device pci f.2 on end	# IDE Controller
+        		device pci f.3 on end 	# Audio
+        		device pci f.4 on end	# OHCI
+			device pci f.5 on end	# EHCI
+			register "unwanted_vpci[0]" = "0x80007E00"	# USB/UDC
+			register "unwanted_vpci[1]" = "0x80007F00"	# USB/OTG
+			register "unwanted_vpci[2]" = "0"	# End of list has a zero
+      		end
+    	end
+end
+

Added: trunk/coreboot-v2/src/mainboard/pcengines/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/pcengines/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/pcengines/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,86 @@
+chip northbridge/amd/lx
+  	device pci_domain 0 on 
+    		device pci 1.0 on end
+		device pci 1.1 on end
+      		chip southbridge/amd/cs5536
+			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
+			# SIRQ Mode = Active(Quiet) mode. Save power....
+			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
+			# How to get these? Boot linux and do this:
+			# rdmsr 0x51400025
+			register "lpc_serirq_enable" = "0x0000105a"
+			# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
+			register "lpc_serirq_polarity" = "0x0000EFA5"
+			# mode is high 10 bits (determined from code)
+			register "lpc_serirq_mode" = "1"
+			# Don't yet know how to find this.
+			register "enable_gpio_int_route" = "0x0D0C0700"
+			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
+			register "enable_USBP4_device" = "0"	#0: host, 1:device
+			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
+			register "com1_enable" = "0"
+			register "com1_address" = "0x3F8"
+			register "com1_irq" = "4"
+			register "com2_enable" = "0"
+			register "com2_address" = "0x2F8"
+			register "com2_irq" = "3"
+			register "unwanted_vpci[0]" = "0"	# End of list has a zero
+        			device pci f.0 on	# ISA Bridge
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off #  Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.1 on #  Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+					end
+					device pnp 2e.2 on #  Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on #  Com2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.5 on #  Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6 off #  CIR
+						io 0x60 = 0x100
+					end
+					device pnp 2e.7 off #  GAME_MIDI_GIPO1
+						io 0x60 = 0x220
+						io 0x62 = 0x300
+						irq 0x70 = 9
+					end						
+					device pnp 2e.8 on end #  GPIO2
+					device pnp 2e.9 on end #  GPIO3
+					device pnp 2e.a on end #  ACPI
+					device pnp 2e.b on #  HW Monitor
+						io 0x60 = 0x290
+						irq 0x70 = 5
+					end
+				end
+			end
+			device pci f.1 on end	# Flash controller
+			device pci f.2 on end	# IDE controller
+        			device pci f.3 on end 	# Audio
+        			device pci f.4 on end	# OHCI
+			device pci f.5 on end	# EHCI
+      		end
+	end
+
+	# APIC cluster is late CPU init.
+	device apic_cluster 0 on
+		chip cpu/amd/model_lx
+			device apic 0 on end
+		end
+	end
+
+end
+

Added: trunk/coreboot-v2/src/mainboard/rca/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/rca/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/rca/rm4100/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,73 @@
+chip northbridge/intel/i82830		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip drivers/pci/onboard		# Onboard VGA
+      device pci 2.0 on end		# VGA (Intel 82830 CGC)
+      register "rom_address" = "0xfff00000"
+    end
+    chip southbridge/intel/i82801xx	# Southbridge
+      register "pirqa_routing" = "0x05"
+      register "pirqb_routing" = "0x06"
+      register "pirqc_routing" = "0x07"
+      register "pirqd_routing" = "0x09"
+      register "pirqe_routing" = "0x0a"
+      register "pirqf_routing" = "0x80"
+      register "pirqg_routing" = "0x80"
+      register "pirqh_routing" = "0x0b"
+
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
+      device pci 1d.0 on end		# USB UHCI Controller #1
+      device pci 1d.1 on end		# USB UHCI Controller #2
+      device pci 1d.2 on end		# USB UHCI Controller #3
+      device pci 1d.7 on end		# USB2 EHCI Controller
+      device pci 1e.0 on		# PCI bridge
+        device pci 08.0 on end		# Intel 82801DB PRO/100 VE Ethernet
+      end
+      device pci 1f.0 on		# ISA/LPC bridge
+        chip superio/smsc/smscsuperio	# Super I/O
+          device pnp 2e.0 off		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.3 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 4
+          end
+          device pnp 2e.4 on		# Com1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.5 on		# Com2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.7 on		# PS/2 keyboard/mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# Keyboard interrupt
+            irq 0x72 = 12		# Mouse interrupt
+          end
+          device pnp 2e.9 off end	# Game port
+          device pnp 2e.a on		# PME
+            io 0x60 = 0x800
+          end
+          device pnp 2e.b off end	# MPU-401
+        end
+      end
+      device pci 1f.1 on end		# IDE
+      device pci 1f.3 on end		# SMBus
+      device pci 1f.5 on end		# AC'97 audio
+      device pci 1f.6 on end		# AC'97 modem
+    end
+  end
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/socket_PGA370	# Mobile Celeron Micro-FCBGA Socket 479
+      device apic 0 on end		# APIC
+    end
+  end
+end
+

Added: trunk/coreboot-v2/src/mainboard/soyo/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/soyo/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/soyo/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/sunw/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/sunw/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/sunw/ultra40/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,155 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_940
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on end # link 0
+			device pci 18.0 on # link1 
+				#  devices on link 0, link 0 == LDT 0 
+			        chip southbridge/nvidia/ck804 
+					device pci 0.0 on end   # HT
+                			device pci 1.0 on # LPC
+                	                        chip superio/smsc/lpc47m10x
+                        	                        device pnp 2e.0 off #  Floppy
+                                	                         io 0x60 = 0x3f0
+                                        	                irq 0x70 = 6
+                                                	        drq 0x74 = 2
+	                                                end
+        	                                        device pnp 2e.3 off #  Parallel Port
+                	                                         io 0x60 = 0x378
+                        	                                irq 0x70 = 7
+                                	                end
+                                        	        device pnp 2e.4 on #  Com1
+                                                	        io 0x60 = 0x3f8
+	                                                        irq 0x70 = 4
+        	                                        end
+                	                                device pnp 2e.5 off #  Com2
+                        	                                io 0x60 = 0x2f8
+                                	                        irq 0x70 = 3
+                                        	        end
+	                                                device pnp 2e.7 off #  Keyboard
+        	                                                io 0x60 = 0x60
+                	                                        io 0x62 = 0x64
+                        	                                irq 0x70 = 1
+                                	                        irq 0x72 = 12
+                                        	        end
+                        	                end
+					end
+			                device pci 1.1 on # SM 0
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end  
+                                                end              
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end             
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end              
+                                                chip drivers/generic/generic #dimm 1-0-0
+                                                        device i2c 54 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-0-1
+                                                        device i2c 55 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-0
+                                                        device i2c 56 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-1
+                                                        device i2c 57 on end
+                                                end 
+					end # SM
+                                        device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#                                                chip drivers/generic/generic #PCIXA Slot1
+#                                                        device i2c 50 on end
+#                                                end
+#                                                chip drivers/generic/generic #PCIXB Slot1
+#                                                        device i2c 51 on end
+#                                                end     
+#                                                chip drivers/generic/generic #PCIXB Slot2
+#                                                        device i2c 52 on end
+#                                                end             
+#                                                chip drivers/generic/generic #PCI Slot1
+#                                                        device i2c 53 on end
+#                                                end              
+#                                                chip drivers/generic/generic #Master CK804 PCI-E
+#                                                        device i2c 54 on end
+#                                                end     
+#                                                chip drivers/generic/generic #Slave CK804 PCI-E
+#                                                        device i2c 55 on end
+#                                                end             
+                                                chip drivers/generic/generic #MAC EEPROM
+                                                        device i2c 51 on end
+                                                end 
+
+                                        end # SM 
+	                		device pci 2.0 on end # USB 1.1
+        	        		device pci 2.1 on end # USB 2
+	                		device pci 4.0 on end # ACI
+        	        		device pci 4.1 off end # MCI
+                			device pci 6.0 on end # IDE
+	                		device pci 7.0 on end # SATA 1
+        	        		device pci 8.0 on end # SATA 0
+                			device pci 9.0 on end # PCI
+	                		device pci a.0 on end # NIC
+        	       			device pci b.0 off end # PCI E 3
+                			device pci c.0 off end # PCI E 2
+                			device pci d.0 off end # PCI E 1
+                			device pci e.0 on end # PCI E 0
+	                                register "ide0_enable" = "1"
+        	                        register "ide1_enable" = "1"
+                	                register "sata0_enable" = "1"
+                        	        register "sata1_enable" = "1"
+#					register "nic_rom_address" = "0xfff80000" # 64k
+#					register "raid_rom_address" = "0xfff90000"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0 
+			device pci 18.0 on end # link 2
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+		
+		chip northbridge/amd/amdk8
+                	device pci 19.0 on end # link 0
+		device pci 19.0 on   
+                        	#  devices on link 1, link 1 == LDT 1
+                        	chip southbridge/nvidia/ck804 
+                                	device pci 0.0 on end   # HT
+                                	device pci 1.0 on end   # LPC
+                                	device pci 1.1 off end # SM
+                                	device pci 2.0 off end # USB 1.1
+                                	device pci 2.1 off end # USB 2
+                                	device pci 4.0 off end # ACI
+                                	device pci 4.1 off end # MCI
+                                	device pci 6.0 off end # IDE
+                                	device pci 7.0 off end # SATA 1
+                                	device pci 8.0 off end # SATA 0
+                                	device pci 9.0 off end # PCI
+                                	device pci a.0 on end # NIC
+                                	device pci b.0 off end # PCI E 3
+                                	device pci c.0 off end # PCI E 2
+                                	device pci d.0 off end # PCI E 1
+                                	device pci e.0 on end # PCI E 0
+#					register "nic_rom_address" = "0xfff80000" # 64k
+                                        register "mac_eeprom_smbus" = "3"
+                                        register "mac_eeprom_addr" = "0x51"
+                        	end
+                	end #  device pci 19.0 
+			
+			device pci 19.0 on end
+			device pci 19.1 on end
+			device pci 19.2 on end
+			device pci 19.3 on end
+		end
+	end # PCI domain
+	
+end #root_complex

Added: trunk/coreboot-v2/src/mainboard/supermicro/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/supermicro/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,143 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.0 on 
+				#  devices on link 0, link 0 == LDT 0 
+			        chip southbridge/nvidia/mcp55 
+					device pci 0.0 on end   # HT
+                			device pci 1.0 on # LPC
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	        			device pnp 2e.6 off  # SFI 
+                	                 			io 0x62 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GPIO_GAME_MIDI
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+                	        			device pnp 2e.8 off end #  WDTO_PLED
+                	        			device pnp 2e.9 off end #  GPIO_SUSLED
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
+						end
+					end
+			                device pci 1.1 on # SM 0
+						chip drivers/i2c/i2cmux2
+							device i2c 48 off end
+							device i2c 49 off end
+						end
+					end # SM
+                                        device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#                                                chip drivers/generic/generic #PCIXA Slot1
+#                                                        device i2c 50 on end
+#                                                end
+#                                                chip drivers/generic/generic #PCIXB Slot1
+#                                                        device i2c 51 on end
+#                                                end     
+#                                                chip drivers/generic/generic #PCIXB Slot2
+#                                                        device i2c 52 on end
+#                                                end             
+#                                                chip drivers/generic/generic #PCI Slot1
+#                                                        device i2c 53 on end
+#                                                end              
+#                                                chip drivers/generic/generic #Master MCP55 PCI-E
+#                                                        device i2c 54 on end
+#                                                end     
+#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
+#                                                        device i2c 55 on end
+#                                                end             
+                                                chip drivers/generic/generic #MAC EEPROM
+                                                        device i2c 51 on end
+                                                end
+
+                                        end # SM 
+	                		device pci 2.0 on end # USB 1.1
+        	        		device pci 2.1 on end # USB 2
+                			device pci 4.0 on end # IDE
+	                		device pci 5.0 on end # SATA 0
+	                		device pci 5.1 on end # SATA 1
+	                		device pci 5.2 on end # SATA 2
+                			device pci 6.0 on  # PCI
+                                                chip drivers/pci/onboard
+                                                        device pci 6.0 on end
+							register "rom_address" = "0xfff00000" #for 1M
+#                                                        register "rom_address" = "0xfff80000" #for 512K
+                                                end
+					end
+        	        		device pci 6.1 on end # AZA
+	                		device pci 8.0 on end # NIC
+	                		device pci 9.0 on end # NIC
+        	       			device pci a.0 on  # PCI E 5
+						device pci 0.0 on #nec pci-x
+						end
+						device pci 0.1 on #nec pci-x
+							device pci 4.0 on end #scsi
+							device pci 4.1 on end #scsi
+						end
+					end
+        	       			device pci b.0 on end # PCI E 4
+                			device pci c.0 on end # PCI E 3
+                			device pci d.0 on end # PCI E 2
+                			device pci e.0 on end # PCI E 1
+        	       			device pci f.0 on end # PCI E 0
+	                                register "ide0_enable" = "1"
+                	                register "sata0_enable" = "1"
+                        	        register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0 
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+		
+	end # PCI domain
+	
+#       chip drivers/generic/debug 
+#               device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 off end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 on end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#                device pnp 0.7 off end # tsc
+#                device pnp 0.8 off  end # io
+#                device pnp 0.9 on end # io
+#       end  
+end #root_complex

Added: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,163 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_F
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.0 on 
+				#  devices on link 0, link 0 == LDT 0 
+			        chip southbridge/nvidia/mcp55 
+					device pci 0.0 on end   # HT
+                			device pci 1.0 on # LPC
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	        			device pnp 2e.6 off  # SFI 
+                	                 			io 0x62 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GPIO_GAME_MIDI
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+                	        			device pnp 2e.8 off end #  WDTO_PLED
+                	        			device pnp 2e.9 off end #  GPIO_SUSLED
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
+						end
+					end
+			                device pci 1.1 on # SM 0
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end  
+                                                end              
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end             
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end              
+                                                chip drivers/generic/generic #dimm 1-0-0
+                                                        device i2c 54 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-0-1
+                                                        device i2c 55 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-0
+                                                        device i2c 56 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-1
+                                                        device i2c 57 on end
+                                                end 
+					end # SM
+                                        device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#                                                chip drivers/generic/generic #PCIXA Slot1
+#                                                        device i2c 50 on end
+#                                                end
+#                                                chip drivers/generic/generic #PCIXB Slot1
+#                                                        device i2c 51 on end
+#                                                end     
+#                                                chip drivers/generic/generic #PCIXB Slot2
+#                                                        device i2c 52 on end
+#                                                end             
+#                                                chip drivers/generic/generic #PCI Slot1
+#                                                        device i2c 53 on end
+#                                                end              
+#                                                chip drivers/generic/generic #Master MCP55 PCI-E
+#                                                        device i2c 54 on end
+#                                                end     
+#                                                chip drivers/generic/generic #Slave MCP55 PCI-E
+#                                                        device i2c 55 on end
+#                                                end             
+                                                chip drivers/generic/generic #MAC EEPROM
+                                                        device i2c 51 on end
+                                                end 
+
+                                        end # SM 
+	                		device pci 2.0 on end # USB 1.1
+        	        		device pci 2.1 on end # USB 2
+                			device pci 4.0 on end # IDE
+	                		device pci 5.0 on end # SATA 0
+	                		device pci 5.1 on end # SATA 1
+	                		device pci 5.2 on end # SATA 2
+                			device pci 6.0 on  # PCI
+                                                chip drivers/pci/onboard
+                                                        device pci 6.0 on end
+							register "rom_address" = "0xfff00000" #for 1M
+#                                                        register "rom_address" = "0xfff80000" #for 512K
+                                                end
+					end
+        	        		device pci 6.1 on end # AZA
+	                		device pci 8.0 on end # NIC
+	                		device pci 9.0 on end # NIC
+        	       			device pci a.0 on  # PCI E 5
+						device pci 0.0 on #nec pci-x
+						end
+						device pci 0.1 on #nec pci-x
+							device pci 4.0 on end #scsi
+							device pci 4.1 on end #scsi
+						end
+					end
+        	       			device pci b.0 on end # PCI E 4
+                			device pci c.0 on end # PCI E 3
+                			device pci d.0 on end # PCI E 2
+                			device pci e.0 on end # PCI E 1
+        	       			device pci f.0 on end # PCI E 0
+	                                register "ide0_enable" = "1"
+                	                register "sata0_enable" = "1"
+                        	        register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0 
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+		
+	end # PCI domain
+	
+#       chip drivers/generic/debug 
+#               device pnp 0.0 off end # chip name
+#                device pnp 0.1 on end # pci_regs_all
+#                device pnp 0.2 off end # mem
+#                device pnp 0.3 off end # cpuid
+#                device pnp 0.4 on end # smbus_regs_all
+#                device pnp 0.5 off end # dual core msr
+#                device pnp 0.6 off end # cache size
+#                device pnp 0.7 off end # tsc
+#                device pnp 0.8 off  end # io
+#                device pnp 0.9 on end # io
+#       end  
+end #root_complex

Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dai_g/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,64 @@
+chip northbridge/intel/e7525 # mch
+	device pci_domain 0 on
+		chip southbridge/intel/esb6300  # esb6300 
+			register "pirq_a_d" = "0x0b0a0a05"
+			register "pirq_e_h" = "0x0a0b0c80"
+		
+			device pci 1c.0 on end
+		
+			device pci 1d.0 on end
+			device pci 1d.1 on end
+			device pci 1d.4 on end
+			device pci 1d.5 on end
+			device pci 1d.7 on end
+		
+			device pci 1e.0 on end
+		
+			device pci 1f.0 on 
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off end
+					device pnp 2e.1 off end
+					device pnp 2e.2 on
+						 io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on
+						 io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.4 off end
+					device pnp 2e.5 off end
+					device pnp 2e.6 off end
+					device pnp 2e.7 off end
+					device pnp 2e.9 off end
+					device pnp 2e.a on  end
+					device pnp 2e.b off end
+					device pnp 2e.f off end
+					device pnp 2e.10 off end
+					device pnp 2e.14 off end
+				end
+			end
+			device pci 1f.1 on end
+			device pci 1f.2 on end
+			device pci 1f.3 on end
+			device pci 1f.5 off end
+			device pci 1f.6 on end
+		end
+		device pci 00.0 on end
+		device pci 00.1 on end 
+		device pci 00.2 on end
+		device pci 02.0 on end
+		device pci 03.0 on end
+		device pci 04.0 on end
+		device pci 08.0 on end
+	end
+	device apic_cluster 0 on
+		chip cpu/intel/socket_mPGA604 # cpu0
+			device apic 0 on end
+		end
+		chip cpu/intel/socket_mPGA604 # cpu1
+			device apic 6 on end
+		end
+	end
+end
+

Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,86 @@
+chip northbridge/intel/e7520  # MCH
+	chip drivers/generic/debug  # DEBUGGING
+		device pnp 00.0 on end
+		device pnp 00.1 off end
+		device pnp 00.2 off end
+		device pnp 00.3 off end
+	end
+	device pci_domain 0 on
+		chip southbridge/intel/esb6300	# ESB6300
+			register "pirq_a_d" = "0x0b070a05"
+			register "pirq_e_h" = "0x0a808080"
+
+			device pci 1c.0 on 
+				chip drivers/generic/generic 
+					device pci 01.0 on end	# onboard gige1
+					device pci 02.0 on end 	# onboard gige2
+				end
+			end
+
+			# USB ports
+			device pci 1d.0 on end
+			device pci 1d.1 on end
+			device pci 1d.4 on end	# Southbridge Watchdog timer
+			device pci 1d.5 on end	# Southbridge I/O apic1
+			device pci 1d.7 on end
+
+			# VGA / PCI 32-bit
+			device pci 1e.0 on 
+				chip drivers/generic/generic
+					device pci 01.0 on end 
+				end
+			end
+
+
+			device pci 1f.0 on 	# ISA bridge
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off end
+					device pnp 2e.2 on 
+						 io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on
+						 io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.4 off end
+					device pnp 2e.5 off end
+					device pnp 2e.6 off end
+					device pnp 2e.7 off end
+					device pnp 2e.9 off end
+					device pnp 2e.a on end
+					device pnp 2e.b off end
+				end
+			end
+			device pci 1f.1 on end
+			device pci 1f.2 off end
+			device pci 1f.3	on end		# SMBus
+			device pci 1f.5 off end
+			device pci 1f.6 off end
+		end
+
+		device pci 00.0	on end	# Northbridge
+		device pci 00.1	on end  # Northbridge Error reporting
+		device pci 01.0 on end
+		device pci 02.0 on 
+			chip southbridge/intel/pxhd	# PXHD 6700 
+				device pci 00.0 on end   # bridge 
+				device pci 00.1 on end   # I/O apic
+				device pci 00.2 on end   # bridge
+				device pci 00.3 on end   # I/O apic
+			end
+		end
+#	 	device register "intrline" = "0x00070105" 
+		device 	pci 04.0 on end	
+		device 	pci 06.0 on end	
+	end
+
+	device apic_cluster 0 on
+		chip cpu/intel/socket_mPGA604  	# CPU 0
+			device apic 0 on end
+		end
+		chip cpu/intel/socket_mPGA604 	# CPU 1
+			device apic 6 on end
+		end
+	end
+end

Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhe_g2/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,86 @@
+chip northbridge/intel/e7520  # MCH
+	chip drivers/generic/debug  # DEBUGGING
+		device pnp 00.0 off end
+		device pnp 00.1 off end
+		device pnp 00.2 off end
+		device pnp 00.3 off end
+	end
+	device pci_domain 0 on
+		chip southbridge/intel/i82801er	# ICH5R 
+			register "pirq_a_d" = "0x0b070a05"
+			register "pirq_e_h" = "0x0a808080"
+
+			device pci 1c.0 on 
+				chip drivers/generic/generic 
+					device pci 01.0 on end	# onboard gige1
+					device pci 02.0 on end 	# onboard gige2
+				end
+			end
+
+			# USB ports
+			device pci 1d.0 on end
+			device pci 1d.1 on end
+			device pci 1d.4 on end	# Southbridge Watchdog timer
+			device pci 1d.5 on end	# Southbridge I/O apic1
+			device pci 1d.7 on end
+
+			# VGA / PCI 32-bit
+			device pci 1e.0 on 
+				chip drivers/generic/generic
+					device pci 01.0 on end 
+				end
+			end
+
+
+			device pci 1f.0 on 	# ISA bridge
+				chip superio/nsc/pc87427
+					device pnp 2e.0 off end
+					device pnp 2e.2 on 
+						 io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on
+						 io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.4 off end
+					device pnp 2e.5 off end
+					device pnp 2e.6 off end
+					device pnp 2e.7 off end
+					device pnp 2e.9 off end
+					device pnp 2e.a on end
+					device pnp 2e.b off end
+				end
+			end
+			device pci 1f.1 on end
+			device pci 1f.2 on end
+			device pci 1f.3	on end		# SMBus
+			device pci 1f.5 off end
+			device pci 1f.6 off end
+		end
+
+		device pci 00.0	on end	# Northbridge
+		device pci 00.1	on end  # Northbridge Error reporting
+		device pci 01.0 on end
+		device pci 02.0 on 
+			chip southbridge/intel/pxhd	# PXHD 6700 
+				device pci 00.0 on end   # bridge 
+				device pci 00.1 on end   # I/O apic
+				device pci 00.2 on end   # bridge
+				device pci 00.3 on end   # I/O apic
+			end
+		end
+#	 	device register "intrline" = "0x00070105" 
+		device 	pci 04.0 on end	
+		device 	pci 06.0 on end	
+	end
+
+	device apic_cluster 0 on
+		chip cpu/intel/socket_mPGA604  	# CPU 0
+			device apic 0 on end
+		end
+		chip cpu/intel/socket_mPGA604 	# CPU 1
+			device apic 6 on end
+		end
+	end
+end

Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,84 @@
+chip northbridge/intel/e7520 # mch
+	device pci_domain 0 on 
+		chip southbridge/intel/i82801er # i82801er
+			# USB ports
+			device pci 1d.0 on end
+			device pci 1d.1 on end
+			device pci 1d.2 on end 
+			device pci 1d.3 on end
+			device pci 1d.7 on end
+		
+			# -> VGA
+			device pci 1e.0 on end
+		
+			# -> IDE
+			device pci 1f.0 on 
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off end
+					device pnp 2e.2 on 
+						 io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on
+						 io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.4 off end
+					device pnp 2e.5 off end
+					device pnp 2e.6 off end
+					device pnp 2e.7 off end
+					device pnp 2e.9 off end
+					device pnp 2e.a on  end
+					device pnp 2e.b off end
+				end
+			end
+			device pci 1f.1 on end
+			device pci 1f.2 on end
+			device pci 1f.3 on end
+
+			register "pirq_a_d" = "0x0b070a05"
+			register "pirq_e_h" = "0x0a808080"
+		end
+		device pci 00.0 on end 
+		device pci 00.1  on end
+		device pci 01.0 on end 
+		device pci 02.0 on end 
+		device pci 03.0 on 
+			chip southbridge/intel/pxhd # pxhd1
+				# Bus bridges and ioapics usually bus 2
+				device pci 0.0 on end
+				device pci 0.1 on end
+				device pci 0.2 on 
+				# On board gig e1000
+					chip drivers/generic/generic 
+        		        	        device pci 02.0 on end
+        		        	        device pci 02.1 on end
+        		        	end
+				end
+				device pci 0.3 on end
+			end
+		end
+		device pci 04.0 on 
+			chip southbridge/intel/pxhd # pxhd2
+				# Bus bridges and ioapics usually bus 5
+				device pci 0.0 on end
+				# Slot 6  is usually 6:2.0
+				device pci 0.1 on end
+				device pci 0.2 on end
+				# Slot 7 is usually 7:2.0
+				device pci 0.3 on end
+			end
+		end
+		device pci 06.0 on end
+	end
+	device apic_cluster 0 on
+		chip cpu/intel/socket_mPGA604 # cpu 0
+			device apic 0 on end
+		end
+		chip cpu/intel/socket_mPGA604 # cpu 1
+			device apic 6 on end
+		end
+	end
+	register "intrline" = "0x00070105"
+end
+

Added: trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/supermicro/x6dhr_ig2/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,75 @@
+chip northbridge/intel/e7520 # mch
+	device pci_domain 0 on 
+		chip southbridge/intel/i82801er # i82801er
+			# USB ports
+			device pci 1d.0 on end
+			device pci 1d.1 on end
+			device pci 1d.2 on end 
+			device pci 1d.3 on end
+			device pci 1d.7 on end
+		
+			# -> Bridge
+			device pci 1e.0 on end
+		
+			# -> ISA
+			device pci 1f.0 on 
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 off end
+					device pnp 2e.2 on 
+						 io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on
+						 io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.4 off end
+					device pnp 2e.5 off end
+					device pnp 2e.6 off end
+					device pnp 2e.7 off end
+					device pnp 2e.9 off end
+					device pnp 2e.a on  end
+					device pnp 2e.b off end
+				end
+			end
+			# -> IDE
+			device pci 1f.1 on end
+			# -> SATA 
+			device pci 1f.2 on end
+			device pci 1f.3 on end
+
+			register "pirq_a_d" = "0x0b070a05"
+			register "pirq_e_h" = "0x0a808080"
+		end
+		device pci 00.0 on end 
+		device pci 00.1 on end
+		device pci 01.0 on end 
+		device pci 02.0 on 
+			chip southbridge/intel/pxhd # pxhd1
+				# Bus bridges and ioapics usually bus 1
+				device pci 0.0 on 
+				# On board gig e1000
+					chip drivers/generic/generic 
+        		        	        device pci 03.0 on end
+        		        	        device pci 03.1 on end
+        		        	end
+				end
+				device pci 0.1 on end
+				device pci 0.2 on end
+				device pci 0.3 on end
+			end
+		end
+		device pci 04.0 on end
+		device pci 06.0 on end
+	end
+	device apic_cluster 0 on
+		chip cpu/intel/socket_mPGA604 # cpu 0
+			device apic 0 on end
+		end
+		chip cpu/intel/socket_mPGA604 # cpu 1
+			device apic 6 on end
+		end
+	end
+	register "intrline" = "0x00070105"
+end
+

Added: trunk/coreboot-v2/src/mainboard/technexion/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/technexion/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/technexion/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,117 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_S1G1
+		device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  southbridge
+				chip southbridge/amd/rs690
+					device pci 0.0 on end # HT  	0x7910
+					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
+						chip drivers/pci/onboard
+							device pci 5.0 on end	# Internal Graphics 0x791F
+							register "rom_address" = "0xfff80000"
+						end
+					end
+					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
+					device pci 3.0 off end # PCIE P2P bridge	0x791b
+					device pci 4.0 on end # PCIE P2P bridge 0x7914
+					device pci 5.0 on end # PCIE P2P bridge 0x7915
+					device pci 6.0 on end # PCIE P2P bridge 0x7916
+					device pci 7.0 on end # PCIE P2P bridge 0x7917
+					device pci 8.0 off end # NB/SB Link P2P bridge
+					register "vga_rom_address" = "0xfff80000"
+					register "gpp_configuration" = "4"
+					register "port_enable" = "0xfc"
+					register "gfx_dev2_dev3" = "1"
+					register "gfx_dual_slot" = "0"
+					register "gfx_lane_reversal" = "0"
+					register "gfx_tmds" = "0"
+					register "gfx_compliance" = "0"
+					register "gfx_reconfiguration" = "1"
+					register "gfx_link_width" = "0"
+				end
+				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
+					device pci 12.0 on end # SATA  0x4380
+					device pci 13.0 on end # USB   0x4387
+					device pci 13.1 on end # USB   0x4388
+					device pci 13.2 on end # USB   0x4389
+					device pci 13.3 on end # USB   0x438a
+					device pci 13.4 on end # USB   0x438b
+					device pci 13.5 on end # USB 2 0x4386
+	 				device pci 14.0 on # SM        0x4385
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+					end # SM
+					device pci 14.1 on end # IDE    0x438c
+					device pci 14.2 on end # HDA    0x4383
+					device pci 14.3 on # LPC	0x438d
+						chip superio/ite/it8712f
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.2 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.3 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.4 off end #  EC
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+							end
+							device pnp 2e.6 on #  Mouse
+								irq 0x70 = 12
+							end
+							device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
+							end
+							device pnp 2e.8 off #  MIDI
+								io 0x60 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.9 off #  GAME
+								io 0x60 = 0x220
+							end
+							device pnp 2e.a off end #  CIR
+						end	#superio/ite/it8712f
+					end		#LPC
+					device pci 14.4 on end # PCI 0x4384
+					device pci 14.5 on end # ACI 0x4382
+					device pci 14.6 on end # MCI 0x438e
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "hda_viddid" = "0x10ec0882"
+				end	#southbridge/amd/sb600
+			end #  device pci 18.0
+
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end		#northbridge/amd/amdk8
+	end #pci_domain
+end		#northbridge/amd/amdk8/root_complex
+

Added: trunk/coreboot-v2/src/mainboard/technologic/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/technologic/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/technologic/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/technologic/ts5300/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/technologic/ts5300/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/technologic/ts5300/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,16 @@
+chip cpu/amd/sc520
+	device pci_domain 0 on 
+		device pci 0.0 on end
+	
+#		chip drivers/pci/onboard
+#			device pci 12.0 on end # enet
+#		end
+#		chip drivers/pci/onboard
+#			device pci 14.0 on end # 69000
+#			register "rom_address" = "0x2000000"
+#		end
+#		register "com1" = "{1}"
+#		register "com1" = "{1, 0, 0x3f8, 4}"
+	end
+
+end

Added: trunk/coreboot-v2/src/mainboard/televideo/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/televideo/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/televideo/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/televideo/tc7020/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/televideo/tc7020/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/televideo/tc7020/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,57 @@
+chip northbridge/amd/gx1		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip southbridge/amd/cs5530		# Southbridge
+      device pci 12.0 on		# ISA bridge
+        chip superio/nsc/pc97317	# Super I/O
+          device pnp 2e.0 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.1 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.2 on		# RTC, Advanced power control (APC)
+            io 0x60 = 0x70
+            irq 0x70 = 8
+          end
+          device pnp 2e.3 off		# Floppy (N/A on this board)
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.4 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.5 on		# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.6 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.7 on		# GPIO
+            io 0x60 = 0xe0
+          end
+          device pnp 2e.8 on		# Power management
+            io 0x60 = 0xe8
+          end
+        end
+      end
+      device pci 12.1 off end		# SMI
+      device pci 12.2 on end		# IDE
+      device pci 12.3 on end		# Audio
+      device pci 12.4 on end		# VGA (onboard)
+      device pci 13.0 on end		# USB
+      device pci 14.0 on end		# MiniPCI slot
+      device pci 15.0 on end		# Ethernet (onboard)
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "0"	# Not available/needed on this board
+    end
+  end
+  chip cpu/amd/model_gx1		# CPU
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/thomson/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/thomson/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/thomson/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/thomson/ip1000/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/thomson/ip1000/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,73 @@
+chip northbridge/intel/i82830		# Northbridge
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    chip drivers/pci/onboard		# Onboard VGA
+      device pci 2.0 on end		# VGA (Intel 82830 CGC)
+      register "rom_address" = "0xfff00000"
+    end
+    chip southbridge/intel/i82801xx	# Southbridge
+      register "pirqa_routing" = "0x05"
+      register "pirqb_routing" = "0x06"
+      register "pirqc_routing" = "0x07"
+      register "pirqd_routing" = "0x09"
+      register "pirqe_routing" = "0x0a"
+      register "pirqf_routing" = "0x80"
+      register "pirqg_routing" = "0x80"
+      register "pirqh_routing" = "0x0b"
+
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+
+      device pci 1d.0 on end		# USB UHCI Controller #1
+      device pci 1d.1 on end		# USB UHCI Controller #2
+      device pci 1d.2 on end		# USB UHCI Controller #3
+      device pci 1d.7 on end		# USB2 EHCI Controller
+      device pci 1e.0 on		# PCI bridge
+        device pci 08.0 on end		# Intel 82801DB PRO/100 VE Ethernet
+      end
+      device pci 1f.0 on		# ISA/LPC bridge
+        chip superio/smsc/smscsuperio	# Super I/O
+          device pnp 2e.0 off		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.3 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 4
+          end
+          device pnp 2e.4 on		# Com1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.5 on		# Com2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.7 on		# PS/2 keyboard/mouse
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1		# Keyboard interrupt
+            irq 0x72 = 12		# Mouse interrupt
+          end
+          device pnp 2e.9 off end	# Game port
+          device pnp 2e.a on		# PME
+            io 0x60 = 0x800
+          end
+          device pnp 2e.b off end	# MPU-401
+        end
+      end
+      device pci 1f.1 on end		# IDE
+      device pci 1f.3 on end		# SMBus
+      device pci 1f.5 on end		# AC'97 audio
+      device pci 1f.6 off end		# AC'97 modem
+    end
+  end
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/socket_PGA370	# Low Voltage PIII Micro-FCBGA Socket 479
+      device apic 0 on end		# APIC
+    end
+  end
+end
+

Added: trunk/coreboot-v2/src/mainboard/totalimpact/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/totalimpact/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/totalimpact/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/totalimpact/briq/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/totalimpact/briq/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/totalimpact/briq/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,22 @@
+chip northbridge/ibm/cpc710
+	device pci_domain 0 on # 32bit pci bridge
+		device pci 0.0 on 
+			chip southbridge/winbond/w83c553
+				# FIXME  The function numbers are ok but the device id is wrong here!
+				device pci 0.0 on end # pci to isa bridge
+				device pci 0.1 on end # pci ide controller
+			end
+		end
+	end
+	device cpu_bus 0 on 
+	#	chip cpu/ppc/ppc7xx
+	#		device cpu 0 on end
+	#	end
+	end
+end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"

Added: trunk/coreboot-v2/src/mainboard/tyan/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#

Added: trunk/coreboot-v2/src/mainboard/tyan/s1846/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s1846/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s1846/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,55 @@
+chip northbridge/intel/i440bx		# Northbridge
+  device apic_cluster 0 on		# APIC cluster
+    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
+      device apic 0 on end		# APIC
+    end
+  end
+  device pci_domain 0 on		# PCI domain
+    device pci 0.0 on end		# Host bridge
+    device pci 1.0 on end		# PCI/AGP bridge
+    chip southbridge/intel/i82371eb	# Southbridge
+      device pci 7.0 on			# ISA bridge
+        chip superio/nsc/pc87309	# Super I/O
+          device pnp 2e.0 on		# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on		# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+          end
+          device pnp 2e.2 on		# COM2 / IR
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.3 on		# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.4 on		# Power management
+          end
+          device pnp 2e.5 on		# PS/2 mouse
+            irq 0x70 = 12
+          end
+          device pnp 2e.6 on		# PS/2 keyboard
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+        end
+      end
+      device pci 7.1 on	end		# IDE
+      device pci 7.2 on	end		# USB
+      device pci 7.3 on end		# ACPI
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      register "ide_legacy_enable" = "1"
+      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
+      register "ide0_drive0_udma33_enable" = "0"
+      register "ide0_drive1_udma33_enable" = "0"
+      register "ide1_drive0_udma33_enable" = "0"
+      register "ide1_drive1_udma33_enable" = "0"
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/tyan/s2735/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2735/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2735/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,91 @@
+chip northbridge/intel/e7501
+        device pci_domain 0 on
+		device pci 0.0 on end
+        	device pci 0.1 on end
+        	device pci 2.0 on
+        		chip southbridge/intel/i82870
+        	        	device pci 1c.0 on end
+		                device pci 1d.0 on 
+					chip drivers/pci/onboard
+                                        	device pci 1.0 on end # intel lan
+                                                device pci 1.1 on end
+                                        end
+				end
+        	                device pci 1e.0 on end
+        	                device pci 1f.0 on end
+        		end
+		end
+        	device pci 6.0 on end
+        	chip southbridge/intel/i82801er
+        		device pci 1d.0 on end
+		        device pci 1d.1 on end
+        	        device pci 1d.2 on end
+        	        device pci 1d.3 on end
+		        device pci 1d.7 on end
+		        device pci 1e.0 on 
+                        	chip drivers/pci/onboard
+                                	device pci 1.0 on end # intel lan 10/100
+                                end
+                                chip drivers/pci/onboard
+                                        device pci 2.0 on end # ati 
+                                end
+			end
+		        device pci 1f.0 on
+				chip superio/winbond/w83627hf
+                                	device pnp 2e.0 on #  Floppy
+                                        	io 0x60 = 0x3f0
+                                                irq 0x70 = 6
+                                                drq 0x74 = 2
+                                        end
+	                                device pnp 2e.1 off #  Parallel Port
+                                                io 0x60 = 0x378
+                                                irq 0x70 = 7
+                                        end
+                                        device pnp 2e.2 on #  Com1
+        	                                io 0x60 = 0x3f8
+                                                irq 0x70 = 4
+                                        end
+                                        device pnp 2e.3 on #  Com2
+                                                io 0x60 = 0x2f8
+                                                irq 0x70 = 3
+                                        end
+                                        device pnp 2e.5 on #  Keyboard
+                                                io 0x60 = 0x60
+                                                io 0x62 = 0x64
+                                                irq 0x70 = 1
+                                                irq 0x72 = 12
+                                        end
+                                        device pnp 2e.6 off #  CIR
+                                                io 0x60 = 0x100
+                                        end
+                                        device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                                                io 0x60 = 0x220
+                                                io 0x62 = 0x300
+                                                irq 0x70 = 9
+                                        end                               
+                                        device pnp 2e.8 off end #  GPIO2
+                                        device pnp 2e.9 off end #  GPIO3
+                                        device pnp 2e.a off end #  ACPI
+                                        device pnp 2e.b on #  HW Monitor
+                                                io 0x60 = 0x290
+                                                irq 0x70 = 5
+                                        end
+				end
+		        end
+		        device pci 1f.1 off end
+        	        device pci 1f.2 on end
+        	        device pci 1f.3 on end
+        		device pci 1f.5 off end
+		        device pci 1f.6 off end
+		end # SB
+        end # PCI_DOMAIN
+        device apic_cluster 0 on
+                chip cpu/intel/socket_mPGA604
+                        device apic 0 on end
+                end
+                chip cpu/intel/socket_mPGA604
+                        device apic 6 on end
+                end
+        end
+end
+

Added: trunk/coreboot-v2/src/mainboard/tyan/s2850/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,98 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on                        
+                chip cpu/amd/socket_940                
+                        device apic 0 on end                    
+                end                                     
+        end 
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on # LDT0
+				#  devices on link 2, link 2 == LDT 2
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+                                                #chip drivers/ati/ragexl
+						chip drivers/pci/onboard
+                                                        device pci b.0 on end
+							register "rom_address" = "0xfff80000"
+                                                end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 on #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	                               device pnp 2e.6 off #  CIR
+                	                                        io 0x60 = 0x100
+                	                                end
+                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                	                                        io 0x60 = 0x220
+                	                                        io 0x62 = 0x300
+                	                                        irq 0x70 = 9
+                	                                end  
+                	                                device pnp 2e.8 off end #  GPIO2
+                	                                device pnp 2e.9 off end #  GPIO3
+                	                                device pnp 2e.a off end #  ACPI
+                	                                device pnp 2e.b on #  HW Monitor
+                	                                        io 0x60 = 0x290
+                	                                        irq 0x70 = 5
+                	                                end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on 
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end
+                                                end
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end
+					end
+					device pci 1.5 on end
+					device pci 1.6 off end
+                                        register "ide0_enable" = "1"
+                                        register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0 
+                	device pci 18.0 on end
+                	device pci 18.0 on end
+			
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+	end 
+end
+

Added: trunk/coreboot-v2/src/mainboard/tyan/s2875/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,90 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_940
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  northbridge 
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/amd/amd8151
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 1.0 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+                                                chip drivers/pci/onboard
+                                                        device pci 5.0 on end
+                                                        register "rom_address" = "0xfff80000"
+                                                end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 on #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.3 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+							device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end  
+							device pnp 2e.8 off end #  GPIO2
+							device pnp 2e.9 off end #  GPIO3
+							device pnp 2e.a off end #  ACPI
+							device pnp 2e.b on #  HW Monitor
+								io 0x60 = 0x290
+								irq 0x70 = 5
+							end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on end
+					device pci 1.5 on end
+					device pci 1.6 off end
+                                        register "ide0_enable" = "1"
+                                        register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0 
+			
+			device pci 18.0 on end
+			device pci 18.0 on end
+			
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+	end 
+end
+

Added: trunk/coreboot-v2/src/mainboard/tyan/s2880/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2880/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2880/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,105 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_940
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  northbridge 
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+					device pci 0.0 on
+                                                chip drivers/pci/onboard
+                                                        device pci 9.0 on end #broadcom
+							device pci 9.1 on end 
+                                                end
+#                                                chip drivers/lsi/53c1030
+#                                                        device pci a.0 on end
+#                                                        device pci a.1 on end
+#                                                        register "fw_address" = "0xfff8c000"
+#                                                end
+					end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+                                                chip drivers/pci/onboard
+                                                        device pci 5.0 on end #some sata
+                                                end
+                                                chip drivers/pci/onboard
+                                                        device pci 6.0 on end #adti
+                                                        register "rom_address" = "0xfff80000"
+                                                end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 on #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	                                device pnp 2e.6 off #  CIR
+                	                                        io 0x60 = 0x100
+                	                                end
+                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                	                                        io 0x60 = 0x220
+                	                                        io 0x62 = 0x300
+                	                                        irq 0x70 = 9
+                	                                end  
+                	                                device pnp 2e.8 off end #  GPIO2
+                	                                device pnp 2e.9 off end #  GPIO3
+                	                                device pnp 2e.a off end #  ACPI
+                	                                device pnp 2e.b on #  HW Monitor
+                	                                        io 0x60 = 0x290
+                	                                        irq 0x70 = 5
+                	                                end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on end
+					device pci 1.5 off end
+					device pci 1.6 off end
+                                        register "ide0_enable" = "1"
+                                        register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0 
+			
+                	device pci 18.0 on end
+                	device pci 18.0 on end
+			
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+	end 
+end
+

Added: trunk/coreboot-v2/src/mainboard/tyan/s2881/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,140 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_940
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on end # LDT0
+			device pci 18.0 on end # LDT1
+			device pci 18.0 on #  northbridge 
+				#  devices on link 2, link 2 == LDT 2
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+					device pci 0.0 on 
+                                                chip drivers/pci/onboard
+                                                        device pci 9.0 on end # Broadcom 5704
+                                                        device pci 9.1 on end
+                                                end
+                                                chip drivers/pci/onboard
+                                                        device pci a.0 on end # Adaptic
+                                                        device pci a.1 on end
+                                                end
+					end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+                                                chip drivers/pci/onboard
+                                                        device pci 5.0 on end # SiI
+                                                end
+                                                chip drivers/pci/onboard
+                                                        device pci 6.0 on end
+							register "rom_address" = "0xfff80000"
+                                                end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 on #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	                                device pnp 2e.6 off #  CIR
+                	                                        io 0x60 = 0x100
+                	                                end
+                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                	                                        io 0x60 = 0x220
+                	                                        io 0x62 = 0x300
+                	                                        irq 0x70 = 9
+                	                                end  
+                	                                device pnp 2e.8 off end #  GPIO2
+                	                                device pnp 2e.9 off end #  GPIO3
+                	                                device pnp 2e.a off end #  ACPI
+                	                                device pnp 2e.b on #  HW Monitor
+                	                                        io 0x60 = 0x290
+                	                                        irq 0x70 = 5
+                	                                end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+                                        device pci 1.3 on 
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end
+                                                end
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end
+                                                chip drivers/generic/generic #dimm 1-0-0
+                                                        device i2c 54 on end
+                                                end
+                                                chip drivers/generic/generic #dimm 1-0-1
+                                                        device i2c 55 on end
+                                                end
+                                                chip drivers/generic/generic #dimm 1-1-0
+                                                        device i2c 56 on end
+                                                end
+                                                chip drivers/generic/generic #dimm 1-1-1
+                                                        device i2c 57 on end
+                                                end
+                                                chip drivers/i2c/adm1027 # ADT7463A CPU0/1 temp, CPU1 vid, SYS FAN 1/2/3
+                                                        device i2c 2d on end
+                                                end
+                                                chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 4,CPU0 vid, CPU0/1 FAN
+                                                        device i2c 2a on end
+                                                end
+                                                chip drivers/generic/generic # Winbond HWM 0x92
+                                                        device i2c 49 on end
+                                                end
+                                                chip drivers/generic/generic # Winbond HWM 0x94
+                                                        device i2c 4a on end
+                                                end
+                                        end # acpi
+					device pci 1.5 off end
+					device pci 1.6 off end
+                                        register "ide0_enable" = "1"
+                                        register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0 
+			
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+	end 
+end
+

Added: trunk/coreboot-v2/src/mainboard/tyan/s2882/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,135 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_940
+                        device apic 0 on end
+                end
+        end
+
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on #  northbridge 
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+					device pci 0.0 on
+                                                chip drivers/pci/onboard 
+                                                        device pci 6.0 on end # adaptec
+                                                        device pci 6.1 on end
+                                                end 
+                                                chip drivers/pci/onboard
+                                                        device pci 9.0 on end # broadcom 5704
+                                                        device pci 9.1 on end
+                                                end
+					end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+                                                chip drivers/pci/onboard  
+                                                        device pci 5.0 on end
+                                                end
+                                        #       chip drivers/ati/ragexl
+                                                chip drivers/pci/onboard
+                                                        device pci 6.0 on end
+                                                        register "rom_address" = "0xfff00000"
+                                                end
+                                                chip drivers/pci/onboard 
+                                                        device pci 8.0 on end #intel 10/100
+                                                end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 on #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	                                device pnp 2e.6 off #  CIR
+                	                                        io 0x60 = 0x100
+                	                                end
+                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                	                                        io 0x60 = 0x220
+                	                                        io 0x62 = 0x300
+                	                                        irq 0x70 = 9
+                	                                end  
+                	                                device pnp 2e.8 off end #  GPIO2
+                	                                device pnp 2e.9 off end #  GPIO3
+                	                                device pnp 2e.a off end #  ACPI
+                	                                device pnp 2e.b on #  HW Monitor
+                	                                        io 0x60 = 0x290
+                	                                        irq 0x70 = 5
+                	                                end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on end
+					device pci 1.3 on 
+#						 chip drivers/generic/generic #dimm 0-0-0
+#							 device i2c 50 on end
+#						 end
+#						 chip drivers/generic/generic #dimm 0-0-1
+#							 device i2c 51 on end
+#						 end	 
+#						 chip drivers/generic/generic #dimm 0-1-0
+#							 device i2c 52 on end
+#						 end
+#						 chip drivers/generic/generic #dimm 0-1-1
+#							 device i2c 53 on end
+#						 end
+#						 chip drivers/generic/generic #dimm 1-0-0
+#							 device i2c 54 on end
+#						 end
+#						 chip drivers/generic/generic #dimm 1-0-1
+#							 device i2c 55 on end
+#						 end
+#						 chip drivers/generic/generic #dimm 1-1-0
+#							 device i2c 56 on end
+#						 end
+#						 chip drivers/generic/generic #dimm 1-1-1
+#							 device i2c 57 on end
+#						 end
+                                        end # acpi
+					device pci 1.5 off end
+					device pci 1.6 off end
+					register "ide0_enable" = "1"
+					register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0 
+			
+                	device pci 18.0 on end
+                	device pci 18.0 on end
+			
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # NB
+	end #pci_domain
+end
+

Added: trunk/coreboot-v2/src/mainboard/tyan/s2885/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,135 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_940
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on # LDT0
+				chip southbridge/amd/amd8151
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 1.0 on end
+				end
+			end
+			device pci 18.0 on end # LDT1
+			device pci 18.0 on #  northbridge 
+				#  devices on link 2, link 2 == LDT 2
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+					device pci 0.0 on 
+                                                chip drivers/pci/onboard
+                                                        device pci 9.0 on end # broadcom 5703
+                                                end
+					end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+                                                chip drivers/pci/onboard
+                                                        device pci b.0 on end # SiI 3114
+                                                end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 on #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 on #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	        			device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end						
+                	        			device pnp 2e.8 off end #  GPIO2
+                	        			device pnp 2e.9 off end #  GPIO3
+                	        			device pnp 2e.a off end #  ACPI
+                	        			device pnp 2e.b on #  HW Monitor
+ 					 			io 0x60 = 0x290
+								irq 0x70 = 5
+                					end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on
+                                                chip drivers/generic/generic #dimm 0-0-0
+                                                        device i2c 50 on end
+                                                end              
+                                                chip drivers/generic/generic #dimm 0-0-1
+                                                        device i2c 51 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 0-1-0
+                                                        device i2c 52 on end
+                                                end             
+                                                chip drivers/generic/generic #dimm 0-1-1
+                                                        device i2c 53 on end
+                                                end              
+                                                chip drivers/generic/generic #dimm 1-0-0
+                                                        device i2c 54 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-0-1
+                                                        device i2c 55 on end
+                                                end
+                                                chip drivers/generic/generic #dimm 1-1-0
+                                                        device i2c 56 on end
+                                                end     
+                                                chip drivers/generic/generic #dimm 1-1-1
+                                                        device i2c 57 on end
+                                                end 
+					end # acpi
+					device pci 1.5 on end
+					device pci 1.6 off end
+                	                register "ide0_enable" = "1"
+                	                register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0 
+			
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+
+	end #pci_domain
+
+#        chip drivers/generic/debug 
+#                device pnp 0.0 off end
+#                device pnp 0.1 off end 
+#                device pnp 0.2 off end
+#                device pnp 0.3 off end
+#		device pnp 0.4 off end
+#		device pnp 0.5 on end
+#        end
+end
+

Added: trunk/coreboot-v2/src/mainboard/tyan/s2891/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,158 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on #  northbridge
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/nvidia/ck804
+					device pci 0.0 on end   # HT
+					device pci 1.0 on # LPC
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.3 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+							device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.8 off end #  GPIO2
+							device pnp 2e.9 off end #  GPIO3
+							device pnp 2e.a off end #  ACPI
+							device pnp 2e.b off #  HW Monitor
+								io 0x60 = 0x290
+								irq 0x70 = 5
+							end
+						end
+					end
+					device pci 1.1 on # SM 0
+#						chip drivers/generic/generic #dimm 0-0-0
+#							device i2c 50 on end
+#						end
+#						chip drivers/generic/generic #dimm 0-0-1
+#							device i2c 51 on end
+#						end
+#						chip drivers/generic/generic #dimm 0-1-0
+#							device i2c 52 on end
+#						end
+#						chip drivers/generic/generic #dimm 0-1-1
+#							device i2c 53 on end
+#						end
+#						chip drivers/generic/generic #dimm 1-0-0
+#							device i2c 54 on end
+#						end
+#						chip drivers/generic/generic #dimm 1-0-1
+#							device i2c 55 on end
+#						end
+#						chip drivers/generic/generic #dimm 1-1-0
+#							device i2c 56 on end
+#						end
+#						chip drivers/generic/generic #dimm 1-1-1
+#							device i2c 57 on end
+#						end
+					end # SM
+#					device pci 1.1 on # SM 1
+#						chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
+#							device i2c 2d on end
+#						end
+#						chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
+#							device i2c 2e on end
+#						end
+#						chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
+#							device i2c 2a on end
+#						end
+#						chip drivers/generic/generic # Winbond HWM 0x92
+#							device i2c 49 on end
+#						end
+#						chip drivers/generic/generic # Winbond HWM 0x94
+#							device i2c 4a on end
+#						end
+#					end #SM
+					device pci 2.0 on end # USB 1.1
+					device pci 2.1 on end # USB 2
+					device pci 4.0 off end # ACI
+					device pci 4.1 off end # MCI
+					device pci 6.0 on end # IDE
+					device pci 7.0 on end # SATA 1
+					device pci 8.0 on end # SATA 0
+					device pci 9.0 on  # PCI
+					#	chip drivers/ati/ragexl
+						chip drivers/pci/onboard
+							device pci 7.0 on end
+							#register "rom_address" = "0xfff80000" #for 512K
+							register "rom_address" = "0xfff00000" #for 1M
+						end
+					end
+					device pci a.0 off end # NIC
+	       				device pci b.0 off end # PCI E 3
+					device pci c.0 off end # PCI E 2
+					device pci d.0 on end # PCI E 1
+					device pci e.0 on end # PCI E 0
+					register "ide0_enable" = "1"
+					register "ide1_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
+				end
+			end #  device pci 18.0
+			device pci 18.0 on end # Link 1
+			device pci 18.0 on
+			#  devices on link 2, link 2 == LDT 2
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on
+						chip drivers/pci/onboard
+							device pci 9.0 on end
+							device pci 9.1 on end
+						end
+					end
+					device pci 1.1 on end
+				end
+			end # device pci 18.0
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end #mc0
+
+	end # pci_domain
+
+#	chip drivers/generic/debug
+#		device pnp 0.0 off end # chip name
+#		device pnp 0.1 off end # pci_regs_all
+#		device pnp 0.2 off end # mem
+#		device pnp 0.3 off end # cpuid
+#		device pnp 0.4 off end # smbus_regs_all
+#		device pnp 0.5 off end # dual core msr
+#		device pnp 0.6 off end # cache size
+#		device pnp 0.7 off end # tsc
+#		device pnp 0.8 on  end # hard_reset
+#	end
+end # root_complex

Added: trunk/coreboot-v2/src/mainboard/tyan/s2892/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,158 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on #  northbridge
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/nvidia/ck804
+					device pci 0.0 on end   # HT
+					device pci 1.0 on # LPC
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 on #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 on #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+								drq 0x74 = 3
+							end
+							device pnp 2e.2 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.3 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp 2e.6 off #  CIR
+								io 0x60 = 0x100
+							end
+							device pnp 2e.7 off #  GAME_MIDI_GIPO1
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.8 off end #  GPIO2
+							device pnp 2e.9 off end #  GPIO3
+							device pnp 2e.a off end #  ACPI
+							device pnp 2e.b on #  HW Monitor
+								io 0x60 = 0x290
+								irq 0x70 = 5
+							end
+						end
+					end
+					device pci 1.1 on # SM 0
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-0
+							device i2c 54 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-1
+							device i2c 55 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-0
+							device i2c 56 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-1
+							device i2c 57 on end
+						end
+					end # SM
+					device pci 1.1 on # SM 1
+						chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
+							device i2c 2d on end
+						end
+						chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
+							device i2c 2e on end
+						end
+						chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
+							device i2c 2a on end
+						end
+						chip drivers/generic/generic # Winbond HWM 0x92
+							device i2c 49 on end
+						end
+						chip drivers/generic/generic # Winbond HWM 0x94
+							device i2c 4a on end
+						end
+					end #SM
+					device pci 2.0 on end # USB 1.1
+					device pci 2.1 on end # USB 2
+					device pci 4.0 off end # ACI
+					device pci 4.1 off end # MCI
+					device pci 6.0 on end # IDE
+					device pci 7.0 on end # SATA 1
+					device pci 8.0 on end # SATA 0
+					device pci 9.0 on  # PCI
+					#	chip drivers/ati/ragexl
+						chip drivers/pci/onboard
+							device pci 6.0 on end
+							register "rom_address" = "0xfff80000"
+						end
+						chip drivers/pci/onboard
+							device pci 8.0 on end
+						end
+					end
+					device pci a.0 off end # NIC
+	       				device pci b.0 off end # PCI E 3
+					device pci c.0 off end # PCI E 2
+					device pci d.0 on end # PCI E 1
+					device pci e.0 on end # PCI E 0
+					register "ide0_enable" = "1"
+					register "ide1_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
+				end
+			end #  device pci 18.0
+			device pci 18.0 on end # Link 1
+			device pci 18.0 on
+			#  devices on link 2, link 2 == LDT 2
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on
+						chip drivers/pci/onboard
+							device pci 9.0 on end # broadcom 5704
+							device pci 9.1 on end
+						end
+					end
+					device pci 1.1 on end
+				end
+			end # device pci 18.0
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end #mc0
+
+	end # pci_domain
+
+#	chip drivers/generic/debug
+#		device pnp 0.0 off end
+#		device pnp 0.1 off end
+#		device pnp 0.2 off end
+#		device pnp 0.3 off end
+#		device pnp 0.4 off end
+#		device pnp 0.5 on end
+#	end
+end # root_complex

Added: trunk/coreboot-v2/src/mainboard/tyan/s2895/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,173 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on #  northbridge
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/nvidia/ck804
+					device pci 0.0 on end   # HT
+					device pci 1.0 on # LPC
+						chip superio/smsc/lpc47b397
+							device pnp 2e.0 on #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.3 on #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+								drq 0x74 = 4
+							end
+							device pnp 2e.4 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.5 off #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.7 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp 2e.8 on # HW Monitor
+								io 0x60 = 0x480
+								chip drivers/generic/generic # LM95221 CPU temp
+									device i2c 2b on end
+								end
+								chip drivers/generic/generic # EMCT03
+									device i2c 54 on end
+								end
+							end
+							device	pnp 2e.a on #  RT
+								io 0x60 = 0x400
+							end
+						end
+					end
+					device pci 1.1 on # SM 0
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-0
+							device i2c 54 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-1
+							device i2c 55 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-0
+							device i2c 56 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-1
+							device i2c 57 on end
+						end
+					end # SM
+					device pci 1.1 on # SM 1
+						chip drivers/generic/generic #MAC EEPROM
+							device i2c 51 on end
+						end
+
+					end # SM
+					device pci 2.0 on end # USB 1.1
+					device pci 2.1 on end # USB 2
+					device pci 4.0 on end # ACI
+					device pci 4.1 off end # MCI
+					device pci 6.0 on end # IDE
+					device pci 7.0 on end # SATA 1
+					device pci 8.0 on end # SATA 0
+					device pci 9.0 on end # PCI
+					device pci a.0 on end # NIC
+		       			device pci b.0 off end # PCI E 3
+					device pci c.0 off end # PCI E 2
+					device pci d.0 off end # PCI E 1
+					device pci e.0 on end # PCI E 0
+					register "ide0_enable" = "1"
+					register "ide1_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
+#					register "nic_rom_address" = "0xfff80000" # 64k
+#					register "raid_rom_address" = "0xfff90000"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0
+			device pci 18.0 on end # Link 1
+			device pci 18.0 on
+			#  devices on link 2, link 2 == LDT 2
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 1.0 on
+						chip drivers/pci/onboard
+							device pci 6.0 on end # lsi scsi
+							device pci 6.1 on end
+						end
+					end
+					device pci 1.1 on end
+				end
+			end # device pci 18.0
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end #mc0
+
+		chip northbridge/amd/amdk8
+			device pci 19.0 on #  northbridge
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/nvidia/ck804
+					device pci 0.0 on end   # HT
+					device pci 1.0 on end   # LPC
+					device pci 1.1 off end # SM
+					device pci 2.0 off end # USB 1.1
+					device pci 2.1 off end # USB 2
+					device pci 4.0 off end # ACI
+					device pci 4.1 off end # MCI
+					device pci 6.0 off end # IDE
+					device pci 7.0 off end # SATA 1
+					device pci 8.0 off end # SATA 0
+					device pci 9.0 off end # PCI
+					device pci a.0 on end # NIC
+					device pci b.0 off end # PCI E 3
+					device pci c.0 off end # PCI E 2
+					device pci d.0 off end # PCI E 1
+					device pci e.0 on end # PCI E 0
+#					register "nic_rom_address" = "0xfff80000" # 64k
+					register "mac_eeprom_smbus" = "3"
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 19.0
+
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.1 on end
+			device pci 19.2 on end
+			device pci 19.3 on end
+		end
+	end # PCI domain
+
+#	chip drivers/generic/debug
+#		device pnp 0.0 off end # chip name
+#		device pnp 0.1 off end # pci_regs_all
+#		device pnp 0.2 off end # mem
+#		device pnp 0.3 off end # cpuid
+#		device pnp 0.4 on  end # smbus_regs_all
+#		device pnp 0.5 off end # dual core msr
+#		device pnp 0.6 off end # cache size
+#		device pnp 0.7 off end # tsc
+#	end
+end # root_complex

Added: trunk/coreboot-v2/src/mainboard/tyan/s2912/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,150 @@
+chip northbridge/amd/amdk8/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_F
+			device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8 #mc0
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.0 on
+				#  devices on link 0, link 0 == LDT 0
+				chip southbridge/nvidia/mcp55
+					device pci 0.0 on end   # HT
+					device pci 1.0 on # LPC
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.3 on #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp 2e.6 off  # SFI
+								io 0x62 = 0x100
+							end
+							device pnp 2e.7 off #  GPIO_GAME_MIDI
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.8 off end #  WDTO_PLED
+							device pnp 2e.9 off end #  GPIO_SUSLED
+							device pnp 2e.a off end #  ACPI
+							device pnp 2e.b on #  HW Monitor
+								io 0x60 = 0x290
+								irq 0x70 = 5
+							end
+						end
+					end
+					device pci 1.1 on # SM 0
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-0
+							device i2c 54 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-1
+							device i2c 55 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-0
+							device i2c 56 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-1
+							device i2c 57 on end
+						end
+					end # SM
+					device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#						chip drivers/generic/generic #PCIXA Slot1
+#							device i2c 50 on end
+#						end
+#						chip drivers/generic/generic #PCIXB Slot1
+#							device i2c 51 on end
+#						end
+#						chip drivers/generic/generic #PCIXB Slot2
+#							device i2c 52 on end
+#						end
+#						chip drivers/generic/generic #PCI Slot1
+#							device i2c 53 on end
+#						end
+#						chip drivers/generic/generic #Master MCP55 PCI-E
+#							device i2c 54 on end
+#						end
+#						chip drivers/generic/generic #Slave MCP55 PCI-E
+#							device i2c 55 on end
+#						end
+						chip drivers/generic/generic #MAC EEPROM
+							device i2c 51 on end
+						end
+
+					end # SM
+					device pci 2.0 on end # USB 1.1
+					device pci 2.1 on end # USB 2
+					device pci 4.0 on end # IDE
+					device pci 5.0 on end # SATA 0
+					device pci 5.1 on end # SATA 1
+					device pci 5.2 on end # SATA 2
+					device pci 6.0 on end # PCI
+					device pci 6.1 off end # AZA
+					device pci 8.0 on end # NIC
+					device pci 9.0 on end # NIC
+					device pci a.0 on end # PCI E 5
+					device pci b.0 off end # PCI E 4
+					device pci c.0 off end # PCI E 3
+					device pci d.0 on end # PCI E 2
+					device pci e.0 off end # PCI E 1
+					device pci f.0 on end # PCI E 0
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end # mc0
+
+	end # PCI domain
+
+#	chip drivers/generic/debug
+#		device pnp 0.0 off end # chip name
+#		device pnp 0.1 on end # pci_regs_all
+#		device pnp 0.2 on end # mem
+#		device pnp 0.3 off end # cpuid
+#		device pnp 0.4 on end # smbus_regs_all
+#		device pnp 0.5 off end # dual core msr
+#		device pnp 0.6 off end # cache size
+#		device pnp 0.7 off end # tsc
+#		device pnp 0.8 off  end # io
+#		device pnp 0.9 off end # io
+#	end
+end #root_complex

Added: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,156 @@
+chip northbridge/amd/amdfam10/root_complex
+	device apic_cluster 0 on
+		chip cpu/amd/socket_F_1207
+			device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		chip northbridge/amd/amdfam10 #mc0
+			device pci 18.0 on end
+			device pci 18.0 on end
+			device pci 18.0 on
+				#  SB on link 2.0.
+				chip southbridge/nvidia/mcp55
+					device pci 0.0 on end   # HT
+					device pci 1.0 on # LPC
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 off #  Floppy
+								io 0x60 = 0x3f0
+								irq 0x70 = 6
+								drq 0x74 = 2
+							end
+							device pnp 2e.1 off #  Parallel Port
+								io 0x60 = 0x378
+								irq 0x70 = 7
+							end
+							device pnp 2e.2 on #  Com1
+								io 0x60 = 0x3f8
+								irq 0x70 = 4
+							end
+							device pnp 2e.3 on #  Com2
+								io 0x60 = 0x2f8
+								irq 0x70 = 3
+							end
+							device pnp 2e.5 on #  Keyboard
+								io 0x60 = 0x60
+								io 0x62 = 0x64
+								irq 0x70 = 1
+								irq 0x72 = 12
+							end
+							device pnp 2e.6 off  # SFI
+								io 0x62 = 0x100
+							end
+							device pnp 2e.7 off #  GPIO_GAME_MIDI
+								io 0x60 = 0x220
+								io 0x62 = 0x300
+								irq 0x70 = 9
+							end
+							device pnp 2e.8 off end #  WDTO_PLED
+							device pnp 2e.9 off end #  GPIO_SUSLED
+							device pnp 2e.a off end #  ACPI
+							device pnp 2e.b on #  HW Monitor
+								io 0x60 = 0x290
+								irq 0x70 = 5
+							end
+						end
+					end
+					device pci 1.1 on # SM 0
+						chip drivers/generic/generic #dimm 0-0-0
+							device i2c 50 on end
+						end
+						chip drivers/generic/generic #dimm 0-0-1
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-0
+							device i2c 52 on end
+						end
+						chip drivers/generic/generic #dimm 0-1-1
+							device i2c 53 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-0
+							device i2c 54 on end
+						end
+						chip drivers/generic/generic #dimm 1-0-1
+							device i2c 55 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-0
+							device i2c 56 on end
+						end
+						chip drivers/generic/generic #dimm 1-1-1
+							device i2c 57 on end
+						end
+					end # SM
+					device pci 1.1 on # SM 1
+#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+#						chip drivers/generic/generic #PCIXA Slot1
+#							device i2c 50 on end
+#						end
+#						chip drivers/generic/generic #PCIXB Slot1
+#							device i2c 51 on end
+#						end
+#						chip drivers/generic/generic #PCIXB Slot2
+#							device i2c 52 on end
+#						end
+#						chip drivers/generic/generic #PCI Slot1
+#							device i2c 53 on end
+#						end
+#						chip drivers/generic/generic #Master MCP55 PCI-E
+#							device i2c 54 on end
+#						end
+#						chip drivers/generic/generic #Slave MCP55 PCI-E
+#							device i2c 55 on end
+#						end
+						chip drivers/generic/generic #MAC EEPROM
+							device i2c 51 on end
+						end
+
+					end # SM
+					device pci 2.0 on end # USB 1.1
+					device pci 2.1 on end # USB 2
+					device pci 4.0 on end # IDE
+					device pci 5.0 on end # SATA 0
+					device pci 5.1 on end # SATA 1
+					device pci 5.2 on end # SATA 2
+					device pci 6.0 on
+						chip drivers/pci/onboard
+							device pci 4.0 on end
+							register "rom_address" = "0xfff00000"
+						end
+					end # PCI
+					device pci 6.1 off end # AZA
+					device pci 8.0 on end # NIC
+					device pci 9.0 on end # NIC
+					device pci a.0 on end # PCI E 5
+					device pci b.0 off end # PCI E 4
+					device pci c.0 off end # PCI E 3
+					device pci d.0 on end # PCI E 2
+					device pci e.0 off end # PCI E 1
+					device pci f.0 on end # PCI E 0
+					register "ide0_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
+					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 18.0
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+			device pci 18.4 on end
+		end # mc0
+
+	end # PCI domain
+
+#	chip drivers/generic/debug
+#		device pnp 0.0 off end # chip name
+#		device pnp 0.1 on end # pci_regs_all
+#		device pnp 0.2 on end # mem
+#		device pnp 0.3 off end # cpuid
+#		device pnp 0.4 on end # smbus_regs_all
+#		device pnp 0.5 off end # dual core msr
+#		device pnp 0.6 off end # cache size
+#		device pnp 0.7 off end # tsc
+#		device pnp 0.8 off  end # io
+#		device pnp 0.9 off end # io
+#	end
+end #root_complex

Added: trunk/coreboot-v2/src/mainboard/tyan/s4880/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,103 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_940
+                        device apic 0 on end
+                end
+        end
+
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on end # LDT0
+			device pci 18.0 on end # LDT1
+			device pci 18.0 on #  northbridge 
+				#  devices on link 2, link 2 == LDT 2
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+                                        device pci 0.0 on
+#                                                chip drivers/lsi/53c1030
+#                                                        device pci 4.0 on end
+#                                                        device pci 4.1 on end
+#                                                        register "fw_address" = "0xfff8c000"
+#                                                end
+                                                chip drivers/pci/onboard
+                                                        device pci 9.0 on end
+                                                        device pci 9.1 on end
+                                                end
+					end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+                                                chip drivers/pci/onboard
+                                                        device pci 6.0 on end
+                                                        register "rom_address" = "0xfff80000"
+                                                end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 on #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 off #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	                                device pnp 2e.6 off #  CIR
+                	                                        io 0x60 = 0x100
+                	                                end
+                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                	                                        io 0x60 = 0x220
+                	                                        io 0x62 = 0x300
+                	                                        irq 0x70 = 9
+                	                                end  
+                	                                device pnp 2e.8 off end #  GPIO2
+                	                                device pnp 2e.9 off end #  GPIO3
+                	                                device pnp 2e.a off end #  ACPI
+                	                                device pnp 2e.b on #  HW Monitor
+                	                                        io 0x60 = 0x290
+                	                                        irq 0x70 = 5
+                	                                end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+					device pci 1.3 on end
+					device pci 1.5 off end
+					device pci 1.6 off end
+                                        register "ide0_enable" = "1"
+                                        register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0 
+			
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+
+	end #pci_domain
+end
+

Added: trunk/coreboot-v2/src/mainboard/tyan/s4882/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,211 @@
+chip northbridge/amd/amdk8/root_complex
+        device apic_cluster 0 on
+                chip cpu/amd/socket_940
+                        device apic 0 on end
+                end
+        end
+	device pci_domain 0 on
+		chip northbridge/amd/amdk8
+			device pci 18.0 on end # LDT0
+			device pci 18.0 on #  northbridge 
+				#  devices on link 1, link 1 == LDT 1
+				chip southbridge/amd/amd8131
+					# the on/off keyword is mandatory
+					device pci 0.0 on 
+#						chip drivers/lsi/53c1030
+#							device pci 4.0 on end
+#							device pci 4.1 on end
+#							register "fw_address" = "0xfff8c000"
+#						end
+                                                chip drivers/pci/onboard
+                                                        device pci 9.0 on end #Broadcom
+                                                        device pci 9.1 on end
+                                                end 
+					end
+					device pci 0.1 on end
+					device pci 1.0 on end
+					device pci 1.1 on end
+				end
+				chip southbridge/amd/amd8111
+					# this "device pci 0.0" is the parent the next one
+					# PCI bridge
+					device pci 0.0 on
+						device pci 0.0 on end
+						device pci 0.1 on end
+						device pci 0.2 off end
+						device pci 1.0 off end
+                                                #chip drivers/ati/ragexl
+                                                chip drivers/pci/onboard
+                                                        device pci 6.0 on end
+                                                        register "rom_address" = "0xfff80000"
+                                                end
+                                                chip drivers/pci/onboard
+                                                        device pci 5.0 on end #SiI
+                                                end
+					end
+					device pci 1.0 on
+						chip superio/winbond/w83627hf
+							device pnp 2e.0 on #  Floppy
+                	                 			io 0x60 = 0x3f0
+                	                			irq 0x70 = 6
+                	                			drq 0x74 = 2
+							end
+                	        			device pnp 2e.1 off #  Parallel Port
+                	                 			io 0x60 = 0x378
+                	                			irq 0x70 = 7
+							end
+                	        			device pnp 2e.2 on #  Com1
+                	                 			io 0x60 = 0x3f8
+                	                			irq 0x70 = 4
+							end
+                	        			device pnp 2e.3 on #  Com2
+                	                 			io 0x60 = 0x2f8
+                	                			irq 0x70 = 3
+							end
+                	        			device pnp 2e.5 on #  Keyboard
+                	                 			io 0x60 = 0x60
+                	                 			io 0x62 = 0x64
+                	                			irq 0x70 = 1
+								irq 0x72 = 12
+							end
+                	                                device pnp 2e.6 off #  CIR
+                	                                        io 0x60 = 0x100
+                	                                end
+                	                                device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                	                                        io 0x60 = 0x220
+                	                                        io 0x62 = 0x300
+                	                                        irq 0x70 = 9
+                	                                end  
+                	                                device pnp 2e.8 off end #  GPIO2
+                	                                device pnp 2e.9 off end #  GPIO3
+                	                                device pnp 2e.a off end #  ACPI
+                	                                device pnp 2e.b on #  HW Monitor
+                	                                        io 0x60 = 0x290
+                	                                        irq 0x70 = 5
+                	                                end
+						end
+					end
+					device pci 1.1 on end
+					device pci 1.2 on end
+                                        device pci 1.3 on 
+#                                                chip drivers/i2c/i2cmux # pca9556 smbus mux
+#                                                        device i2c 18 on #0 pca9516 2, 1
+#	  					                chip drivers/i2c/lm63 #cpu0 temp
+#                                                                        device i2c 4c on end
+#                                                                end 
+#							end
+#                                                        device i2c 18 on #1 pca9516 1, 1
+#                                                                chip drivers/generic/generic #dimm 1-0-0
+#                                                                        device i2c 50 on end
+#                                                                end
+#                                                                chip drivers/generic/generic #dimm 1-0-1
+#                                                                        device i2c 51 on end
+#                                                                end
+#                                                                chip drivers/generic/generic #dimm 1-1-0
+#                                                                        device i2c 52 on end
+#                                                                end
+#                                                                chip drivers/generic/generic #dimm 1-1-1
+#	                                                                device i2c 53 on end
+#								end
+#                                                        end
+#                                                        device i2c 18 on #2 pca9516 1, 2
+#                                                                chip drivers/generic/generic #dimm 0-0-0
+#                                                                        device i2c 50 on end
+#                                                                end
+#                                                                chip drivers/generic/generic #dimm 0-0-1
+#                                                                        device i2c 51 on end
+#                                                                end
+#                                                                chip drivers/generic/generic #dimm 0-1-0
+#                                                                        device i2c 52 on end
+#                                                                end
+#                                                                chip drivers/generic/generic #dimm 0-1-1
+#                                                                	device i2c 53 on end
+#								end
+#                                                        end
+#                                                        device i2c 18 on #3 pca9516 1, 3
+#                                                                chip drivers/generic/generic #dimm 3-0-0
+#                                                                        device i2c 50 on end
+#                                                                end
+#                                                                chip drivers/generic/generic #dimm 3-0-1
+#                                                                        device i2c 51 on end
+#                                                                end
+#                                                                chip drivers/generic/generic #dimm 3-1-0
+#                                                                        device i2c 52 on end
+#                                                                end
+#                                                                chip drivers/generic/generic #dimm 3-1-1
+#                                                                	device i2c 53 on end
+#								end
+#                                                        end
+#                                                        device i2c 18 on #4 pca9516 1, 4
+#                                                                chip drivers/generic/generic #dimm 2-0-0
+#                                                                        device i2c 50 on end
+#                                                                end
+#                                                                chip drivers/generic/generic #dimm 2-0-1
+#                                                                        device i2c 51 on end
+#                                                                end
+#                                                                chip drivers/generic/generic #dimm 2-1-0
+#                                                                        device i2c 52 on end
+#                                                                end
+#                                                                chip drivers/generic/generic #dimm 2-1-1
+#                                                                	device i2c 53 on end
+#								end
+#                                                        end
+#                                                        device i2c 18 on #5 pca9516 2, 2
+#                                                                chip drivers/i2c/lm63 #cpu1 temp
+#                                                                       device i2c 4c on end
+#                                                                end
+#                                                        end
+#                                                        device i2c 18 on #6 pca9516 2, 3
+#                                                                chip drivers/i2c/lm63 #cpu2 temp
+#                                                                        device i2c 4c on end
+#                                                                end
+#                                                        end
+#                                                        device i2c 18 on #7 pca9516 2, 4
+#                                                                chip drivers/i2c/lm63 #cpu3 temp
+#                                                                        device i2c 4c on end
+#                                                                end
+#                                                        end
+#                                                end # i2cmux
+#                                                chip drivers/i2c/adm1027 # ADM1027 CPU1 vid and System FAN...
+#                                                        device i2c 2e on end
+#                                                end
+#                                                chip drivers/generic/generic # Winbond HWM 0x54 CPU0 vid 
+#                                                        device i2c 2a on end
+#                                                end
+#                                                chip drivers/generic/generic # Winbond HWM 0x92
+#                                                        device i2c 49 on end
+#                                                end
+#                                                chip drivers/generic/generic # Winbond HWM 0x94
+#                                                        device i2c 4a on end
+#                                                end
+#                                                chip drivers/generic/generic # ??
+#                                                        device i2c 69 on end
+#                                                end
+                                        end # acpi
+					device pci 1.5 off end
+					device pci 1.6 off end
+					register "ide0_enable" = "1"
+                                        register "ide1_enable" = "1"
+				end
+			end #  device pci 18.0 
+			
+                	device pci 18.0 on end
+			
+			device pci 18.1 on end
+			device pci 18.2 on end
+			device pci 18.3 on end
+		end
+
+	end 
+#        chip drivers/generic/debug
+#                device pnp 0.0 off end # chip name
+#                device pnp 0.1 off end # pci_regs_all
+#                device pnp 0.2 off end # mem
+#                device pnp 0.3 on end # cpuid
+#                device pnp 0.4 off end # smbus_regs_all
+#		device pnp 0.5 on end # dual core msr
+#		device pnp 0.6 on end # cache size
+#		device pnp 0.7 on end # tsc
+#        end
+end
+

Added: trunk/coreboot-v2/src/mainboard/via/Kconfig
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,37 @@
+choice
+        prompt "Mainboard model"
+        depends on VENDOR_VIA
+
+config BOARD_VIA_VT8454C
+        bool "vt8454c"
+        select ARCH_X86
+        select CPU_VIA_C7
+        select NORTHBRIDGE_VIA_CX700
+#       select SOUTHBRIDGE_INTEL_I82801GX
+        select SUPERIO_VIA_VT1211
+        select PIRQ_TABLE
+#	select MMCONF_SUPPORT
+	select USE_PRINTK_IN_CAR
+        help
+          Kontron 986LCD-M Series mainboards
+endchoice
+
+config MAINBOARD_DIR
+	string
+	default via/vt8454c
+	depends on BOARD_VIA_VT8454C
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xffef0000
+	depends on BOARD_VIA_VT8454C
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x8000
+	depends on BOARD_VIA_VT8454C
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "VT8454C"
+	depends on BOARD_VIA_VT8454C

Added: trunk/coreboot-v2/src/mainboard/via/epia/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,65 @@
+chip northbridge/via/vt8601
+	device pci_domain 0 on
+    		device pci 0.0 on end			# Northbridge
+#		device pci 0.1 on			# AGP bridge
+		#	chip drivers/pci/onboard	# Integrated VGA
+		#		device pci 0.0 on end
+		#		register "rom_adress" = "0xfff80000"
+		#	end
+#		end
+		chip southbridge/via/vt8231
+			register "enable_native_ide" = "0"
+			register "enable_com_ports" = "1"
+			register "enable_keyboard" = "0"
+			device pci 11.0 on              # Southbrdge
+				chip superio/winbond/w83627hf
+					device pnp 2e.0 on      #  Floppy
+					   io 0x60 = 0x3f0
+					  irq 0x70 = 6
+					  drq 0x74 = 2
+					end
+					device pnp 2e.1 off     #  Parallel Port
+					   io 0x60 = 0x378
+					  irq 0x70 = 7
+					end
+					device pnp 2e.2 on      #  Com1
+					   io 0x60 = 0x3f8
+					  irq 0x70 = 4
+					end
+					device pnp 2e.3 off     #  Com2
+					   io 0x60 = 0x2f8
+					  irq 0x70 = 3
+					end
+					device pnp 2e.5 on      #  Keyboard
+					   io 0x60 = 0x60
+					   io 0x62 = 0x64
+					  irq 0x70 = 1
+					  irq 0x72 = 12
+	      				end
+				register "com1" = "{CONFIG_TTYS0_BAUD}"
+				end
+				device pnp 2e.6 off end 	#  CIR
+				device pnp 2e.7 off end 	#  GAME_MIDI_GIPO1
+				device pnp 2e.8 off end		#  GPIO2
+				device pnp 2e.9 off end 	#  GPIO3
+				device pnp 2e.a off end		#  ACPI
+				device pnp 2e.b on		#  HW Monitor
+					io 0x60 = 0x290
+				end
+			end
+			device pci 11.1 on  end		# Ide
+			device pci 11.2 off end		# Usb port 0-1
+			device pci 11.3 off end		# Usb port 2-3
+			device pci 11.4 off end		# ACPI
+			device pci 11.5 off end		# AC97 Audio
+			device pci 11.6 on  end		# AC97 Modem
+          		device pci 12.0 on  end		# Ethernet
+        	end
+	end
+
+        device apic_cluster 0 on
+                chip cpu/via/model_c3
+                        device apic 0 on end
+                end
+        end
+end

Added: trunk/coreboot-v2/src/mainboard/via/epia-cn/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,61 @@
+chip northbridge/via/cn700			# Northbridge
+  device pci_domain 0 on			# PCI domain
+    device pci 0.0 on end			# AGP Bridge
+    device pci 0.1 on end			# Error Reporting
+    device pci 0.2 on end			# Host Bus Control
+    device pci 0.3 on end			# Memory Controller
+    device pci 0.4 on end			# Power Management
+    device pci 0.7 on end			# V-Link Controller
+    device pci 1.0 on end			# PCI Bridge
+    chip southbridge/via/vt8237r		# Southbridge
+      # Enable both IDE channels.
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      # Both cables are 40pin.
+      register "ide0_80pin_cable" = "0"
+      register "ide1_80pin_cable" = "0"
+      device pci f.0 on end			# IDE
+      register "fn_ctrl_lo" = "0x80"
+      register "fn_ctrl_hi" = "0x1d"
+      device pci 10.0 on end			# OHCI
+      device pci 10.1 on end			# OHCI
+      device pci 10.2 on end			# OHCI
+      device pci 10.3 on end			# OHCI
+      device pci 10.4 on end			# EHCI
+      device pci 10.5 on end			# UDCI
+      device pci 11.0 on			# Southbridge LPC
+        chip superio/via/vt1211			# Super I/O
+          device pnp 2e.0 off			# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on			# Parallel Port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 2e.2 on			# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.3 on			# COM2
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.b on			# HWM
+            io 0x60 = 0xec00
+          end
+        end
+      end
+      device pci 11.5 on end			# AC'97 audio
+      # device pci 11.6 off end			# AC'97 Modem
+      device pci 12.0 on end			# Ethernet
+    end
+  end
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/via/model_c7			# VIA C7
+      device apic 0 on end			# APIC
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/via/epia-m/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,57 @@
+chip northbridge/via/vt8623
+
+	device apic_cluster 0 on
+		chip cpu/via/model_c3
+			device apic 0 on  end 
+		end
+	end
+
+	device pci_domain 0 on
+		chip southbridge/via/vt8235
+
+			device pci 10.0 on end # USB 1.1
+			device pci 10.1 on end # USB 1.1
+			device pci 10.2 on end # USB 1.1
+			device pci 10.3 on end # USB 2
+
+			device pci 11.0 on      # Southbridge
+				chip superio/via/vt1211
+					device pnp 2e.0 on	# Floppy
+						io 0x60 = 0x3f0
+						irq 0x70 = 6
+						drq 0x74 = 2
+					end
+					device pnp 2e.1 on	# Parallel Port
+						io 0x60 = 0x378
+						irq 0x70 = 7
+						drq 0x74 = 3
+					end
+					device pnp 2e.2 on	# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 on	# COM2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 2e.b on	# HWM
+						io 0x60 = 0xec00
+					end
+
+				end
+			end
+			
+			device pci 11.1 on  end # IDE
+			# 2-4 non existant?
+			device pci 11.5 on  end # AC97 Audio
+			device pci 11.6 off end # AC97 Modem
+			device pci 12.0 on end  # Ethernet
+		end
+#		This is on the EPIA MII, not the M.
+		chip southbridge/ricoh/rl5c476
+			register "enable_cf" = "1"
+			device pci 0a.0 on end
+			device pci 0a.1 on end	
+		end
+	end
+end

Added: trunk/coreboot-v2/src/mainboard/via/epia-m700/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-m700/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/epia-m700/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,24 @@
+chip northbridge/via/vx800	# Northbridge
+  device pci_domain 0 on
+    device pci 0.0 on end	# AGP Bridge
+    device pci 0.1 on end	# Error Reporting
+    device pci 0.2 on end	# Host Bus Control
+    device pci 0.3 on end	# Memory Controller
+    device pci 0.4 on end	# Power Management
+    device pci 0.7 on end	# V-Link Controller
+    device pci 1.0 on end	# PCI Bridge
+    # device pci f.0 on end	# IDE/SATA
+    # device pci f.1 on end	# IDE
+    # device pci 10.0 on end	# USB 1.1
+    # device pci 10.1 on end	# USB 1.1
+    # device pci 10.2 on end	# USB 1.1
+    # device pci 10.4 on end	# USB 2.0
+    # device pci 11.0 on	# Southbridge LPC
+    # end
+  end
+  device apic_cluster 0 on	# APIC cluster
+    chip cpu/via/model_c7	# VIA C7
+      device apic 0 on end	# APIC
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/via/pc2500e/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/pc2500e/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/pc2500e/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,88 @@
+chip northbridge/via/cn700			# Northbridge
+  device pci_domain 0 on			# PCI domain
+    device pci 0.0 on end			# AGP Bridge
+    device pci 0.1 on end			# Error Reporting
+    device pci 0.2 on end			# Host Bus Control
+    device pci 0.3 on end			# Memory Controller
+    device pci 0.4 on end			# Power Management
+    device pci 0.7 on end			# V-Link Controller
+    device pci 1.0 on end			# PCI Bridge
+    chip southbridge/via/vt8237r		# Southbridge
+      # Enable both IDE channels.
+      register "ide0_enable" = "1"
+      register "ide1_enable" = "1"
+      # Both cables are 40pin.
+      register "ide0_80pin_cable" = "0"
+      register "ide1_80pin_cable" = "0"
+      device pci f.0 on end			# SATA
+      device pci f.1 on end			# IDE
+      register "fn_ctrl_lo" = "0x80"
+      register "fn_ctrl_hi" = "0x1d"
+      device pci 10.0 on end			# UHCI
+      device pci 10.1 on end			# UHCI
+      device pci 10.2 on end			# UHCI
+      device pci 10.3 on end			# UHCI
+      device pci 10.4 on end			# EHCI
+      device pci 10.5 on end			# UDCI
+      device pci 11.0 on			# Southbridge LPC
+        chip superio/ite/it8716f		# Super I/O
+          device pnp 2e.0 on			# Floppy
+            io 0x60 = 0x3f0
+            irq 0x70 = 6
+            drq 0x74 = 2
+          end
+          device pnp 2e.1 on			# COM1
+            io 0x60 = 0x3f8
+            irq 0x70 = 4
+          end
+          device pnp 2e.2 off			# COM2 (N/A on this board)
+            io 0x60 = 0x2f8
+            irq 0x70 = 3
+          end
+          device pnp 2e.3 on			# Parallel port
+            io 0x60 = 0x378
+            irq 0x70 = 7
+            drq 0x74 = 3
+          end
+          device pnp 2e.4 on			# Environment controller
+            io 0x60 = 0x290
+            io 0x62 = 0x0000
+            irq 0x70 = 9
+          end
+          device pnp 2e.5 off			# PS/2 keyboard (not used)
+            io 0x60 = 0x60
+            io 0x62 = 0x64
+            irq 0x70 = 1
+          end
+          device pnp 2e.6 off			# PS/2 mouse (not used)
+            irq 0x70 = 12
+          end
+          device pnp 2e.7 on			# GPIO
+            io 0x60 = 0x0000
+            io 0x62 = 0x0800
+            io 0x64 = 0x0000
+          end
+          device pnp 2e.8 off			# MIDI port (N/A)
+            io 0x60 = 0x300
+            irq 0x70 = 10
+          end
+          device pnp 2e.9 off			# Game port (N/A)
+            io 0x60 = 0x201
+          end
+          device pnp 2e.a on			# Consumer IR
+            io 0x60 = 0x310
+            irq 0x70 = 11
+          end
+        end
+      end
+      device pci 11.5 on end			# AC'97 audio
+      # device pci 11.6 off end			# AC'97 modem (N/A)
+      device pci 12.0 on end			# Ethernet
+    end
+  end
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/via/model_c7			# VIA C7
+      device apic 0 on end			# APIC
+    end
+  end
+end

Added: trunk/coreboot-v2/src/mainboard/via/vt8454c/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/vt8454c/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/vt8454c/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,64 @@
+##
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+## 
+
+driver-y +=  mainboard.o
+
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  fadt.o
+
+initobj-y += crt0.o
+# FIXME in $(top)/Makefile
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/via/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+ifdef POST_EVALUATION
+
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+	mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h
+	$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@
+	perl -e 's/\.rodata/.rom.data/g' -pi $@
+	perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+endif
+

Added: trunk/coreboot-v2/src/mainboard/via/vt8454c/devicetree.cb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/vt8454c/devicetree.cb	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/via/vt8454c/devicetree.cb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,59 @@
+chip northbridge/via/cx700
+	device apic_cluster 0 on
+		chip cpu/via/model_c7
+			device apic 0 on end
+		end
+	end
+	device pci_domain 0 on
+		device pci 0.0 on end # AGP Bridge
+		device pci 0.1 on end # Error Reporting
+		device pci 0.2 on end # Host Bus Control
+		device pci 0.3 on end # Memory Controller
+		device pci 0.4 on end # Power Management
+		device pci 0.7 on end # V-Link Controller
+		device pci 1.0 on     # PCI Bridge
+			chip drivers/pci/onboard
+				device pci 0.0 on end
+				#register "rom_address" = "0xfffc0000" #256k image
+				register "rom_address" = "0xfff80000" #512k image
+				#register "rom_address" = "0xfff00000" #1024k image
+			end # Onboard Video
+		end # PCI Bridge
+		device pci f.0 on end # IDE/SATA
+		#device pci f.1 on end # IDE
+		device pci 10.0 on end # USB 1.1
+		device pci 10.1 on end # USB 1.1
+		device pci 10.2 on end # USB 1.1
+		device pci 10.4 on end # USB 2.0
+		device pci 11.0 on      # Southbridge LPC
+			chip superio/via/vt1211
+				device pnp 2e.0 on	# Floppy
+					io 0x60 = 0x3f0
+					irq 0x70 = 6
+					drq 0x74 = 2
+				end
+				device pnp 2e.1 on	# Parallel Port
+					io 0x60 = 0x378
+					irq 0x70 = 7
+					drq 0x74 = 3
+				end
+				device pnp 2e.2 on	# COM1
+					io 0x60 = 0x3f8
+					irq 0x70 = 4
+				end
+				device pnp 2e.3 on	# COM2
+					io 0x60 = 0x2f8
+					irq 0x70 = 3
+				end
+				device pnp 2e.b on	# HWM
+					io 0x60 = 0xec00
+				end
+			end # superio
+		end # pci 11.0
+		# 1-4 non existant
+		#device pci 11.5 on end # AC97 Audio
+		#device pci 11.6 off end # AC97 Modem
+		#device pci 12.0 on end  # Ethernet
+	end # pci domain 0
+end # cx700
+

Added: trunk/coreboot-v2/src/northbridge/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,5 @@
+#source src/northbridge/amd/Kconfig
+#source src/northbridge/ibm/Kconfig
+source src/northbridge/intel/Kconfig
+#source src/northbridge/motorola/Kconfig
+source src/northbridge/via/Kconfig

Added: trunk/coreboot-v2/src/northbridge/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/northbridge/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,5 @@
+#subdirs-y += amd
+#subdirs-y += ibm
+subdirs-y += intel
+#subdirs-y += motorola
+subdirs-y += via

Added: trunk/coreboot-v2/src/northbridge/amd/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/amd/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,7 @@
+#source src/northbridge/amd/amdfam10/Kconfig
+#source src/northbridge/amd/amdht/Kconfig
+source src/northbridge/amd/amdk8/Kconfig
+#source src/northbridge/amd/amdmct/Kconfig
+#source src/northbridge/amd/gx1/Kconfig
+#source src/northbridge/amd/gx2/Kconfig
+#source src/northbridge/amd/lx/Kconfig

Added: trunk/coreboot-v2/src/northbridge/amd/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/amd/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,8 @@
+subdirs-$(CPU_AMD_K10) += amdfam10
+subdirs-$(CPU_AMD_HT) += amdht
+subdirs-$(CPU_AMD_K8) += amdk8
+subdirs-$(CPU_AMD_MCT) += amdmct
+subdirs-$(CPU_AMD_GX1) += gx1
+subdirs-$(CPU_AMD_GX2) += gx2
+subdirs-$(CPU_AMD_LX) += lx
+

Added: trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+config NORTHBRIDGE_AMD_AMDK8
+	bool
+	default n

Added: trunk/coreboot-v2/src/northbridge/amd/amdk8/root_complex/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/root_complex/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/root_complex/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+config NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
+	bool
+	default n

Added: trunk/coreboot-v2/src/northbridge/ibm/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/ibm/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/ibm/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#source src/northbridge/ibm/cpc710/Kconfig
+#source src/northbridge/ibm/cpc925/Kconfig

Added: trunk/coreboot-v2/src/northbridge/ibm/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/northbridge/ibm/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/ibm/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+subdirs-y += cpc710
+subdirs-y += cpc925

Added: trunk/coreboot-v2/src/northbridge/intel/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/intel/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,10 @@
+#source src/northbridge/intel/e7501/Kconfig
+#source src/northbridge/intel/e7520/Kconfig
+#source src/northbridge/intel/e7525/Kconfig
+#source src/northbridge/intel/i3100/Kconfig
+#source src/northbridge/intel/i440bx/Kconfig
+source src/northbridge/intel/i82810/Kconfig
+#source src/northbridge/intel/i82830/Kconfig
+#source src/northbridge/intel/i855gme/Kconfig
+#source src/northbridge/intel/i855pm/Kconfig
+source src/northbridge/intel/i945/Kconfig

Added: trunk/coreboot-v2/src/northbridge/intel/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/intel/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,10 @@
+#subdirs-y += e7501
+#subdirs-y += e7520
+#subdirs-y += e7525
+#subdirs-y += i3100
+#subdirs-y += i440bx
+subdirs-y += i82810
+#subdirs-y += i82830
+#subdirs-y += i855gme
+#subdirs-y += i855pm
+subdirs-y += i945

Added: trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/intel/i82810/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,28 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config HAVE_HIGH_TABLES
+	bool "Do we have high tables"
+	default y
+
+config NORTHBRIDGE_INTEL_I82810
+	bool
+	default n
+

Added: trunk/coreboot-v2/src/northbridge/intel/i82810/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i82810/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/intel/i82810/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+driver-$(CONFIG_NORTHBRIDGE_INTEL_I82810) += northbridge.o
+

Added: trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/intel/i945/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+config NORTHBRIDGE_INTEL_I945
+	bool
+	default n

Added: trunk/coreboot-v2/src/northbridge/intel/i945/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i945/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/intel/i945/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,24 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2009 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+driver-$(CONFIG_NORTHBRIDGE_INTEL_I945) += northbridge.o
+driver-$(CONFIG_NORTHBRIDGE_INTEL_I945) += gma.o
+ifeq ($(CONFIG_HAVE_ACPI_TABLES),y)
+	obj-$(CONFIG_NORTHBRIDGE_INTEL_I945) += acpi.o
+endif

Added: trunk/coreboot-v2/src/northbridge/motorola/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/motorola/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/motorola/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+#source src/northbridge/motorola/mpc107/Kconfig

Added: trunk/coreboot-v2/src/northbridge/motorola/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/northbridge/motorola/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/motorola/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+subdirs-y += mpc107

Added: trunk/coreboot-v2/src/northbridge/via/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,5 @@
+#source src/northbridge/via/cn700/Kconfig
+source src/northbridge/via/cx700/Kconfig
+#source src/northbridge/via/vt8601/Kconfig
+#source src/northbridge/via/vt8623/Kconfig
+#source src/northbridge/via/vx800/Kconfig

Added: trunk/coreboot-v2/src/northbridge/via/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,6 @@
+#subdirs-y += vt8601
+#subdirs-y += vt8623
+#subdirs-y += cn700
+subdirs-y += cx700
+#subdirs-y += vx800
+

Added: trunk/coreboot-v2/src/northbridge/via/cx700/Kconfig
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cx700/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cx700/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,3 @@
+config NORTHBRIDGE_VIA_CX700
+	bool
+	default n

Added: trunk/coreboot-v2/src/northbridge/via/cx700/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cx700/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/northbridge/via/cx700/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,25 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+
+obj-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_reset.o
+obj-$(CONFIG_NORTHBRIDGE_VIA_CX700) += northbridge.o
+obj-$(CONFIG_NORTHBRIDGE_VIA_CX700) += vgabios.o
+
+driver-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_agp.o
+driver-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_lpc.o
+driver-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_sata.o
+driver-$(CONFIG_NORTHBRIDGE_VIA_CX700) += cx700_vga.o

Added: trunk/coreboot-v2/src/pc80/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/pc80/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/pc80/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,9 @@
+obj-y +=  mc146818rtc.o
+obj-y +=  isa-dma.o
+obj-y +=  i8259.o 
+#obj-y +=  udelay_timer2.o CONFIG_UDELAY_TIMER2
+obj-$(CONFIG_UDELAY_IO) +=  udelay_io.o
+obj-y +=  keyboard.o
+
+#initobj-y +=  serial.o
+

Modified: trunk/coreboot-v2/src/pc80/serial.c
===================================================================
--- trunk/coreboot-v2/src/pc80/serial.c	2009-08-12 05:49:48 UTC (rev 4533)
+++ trunk/coreboot-v2/src/pc80/serial.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -71,7 +71,7 @@
 	uart_wait_until_sent();
 }
 
-static void uart_init(void)
+void uart_init(void)
 {
 	/* disable interrupts */
 	outb(0x0, CONFIG_TTYS0_BASE + UART_IER);

Added: trunk/coreboot-v2/src/southbridge/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,8 @@
+#source src/southbridge/amd/Kconfig
+#source src/southbridge/broadcom/Kconfig
+source src/southbridge/intel/Kconfig
+#source src/southbridge/nvidia/Kconfig
+#source src/southbridge/ricoh/Kconfig
+#source src/southbridge/sis/Kconfig
+#source src/southbridge/via/Kconfig
+#source src/southbridge/winbond/Kconfig

Added: trunk/coreboot-v2/src/southbridge/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,8 @@
+#subdirs-y += amd
+#subdirs-y += broadcom
+subdirs-y += intel
+#subdirs-y += nvidia
+#subdirs-y += ricoh
+#subdirs-y += sis
+#subdirs-y += via
+#subdirs-y += winbond

Added: trunk/coreboot-v2/src/southbridge/amd/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,10 @@
+source src/southbridge/amd/amd8111/Kconfig
+source src/southbridge/amd/amd8131/Kconfig
+source src/southbridge/amd/amd8131-disable/Kconfig
+source src/southbridge/amd/amd8132/Kconfig
+source src/southbridge/amd/amd8151/Kconfig
+source src/southbridge/amd/cs5530/Kconfig
+source src/southbridge/amd/cs5535/Kconfig
+source src/southbridge/amd/cs5536/Kconfig
+source src/southbridge/amd/rs690/Kconfig
+source src/southbridge/amd/sb600/Kconfig

Added: trunk/coreboot-v2/src/southbridge/amd/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,11 @@
+subdirs-$(SOUTHBRIDGE_AMD_AMD8111) += amd8111
+subdirs-$(SOUTHBRIDGE_AMD_AMD8131) += amd8131
+subdirs-$(SOUTHBRIDGE_AMD_AMD8112) += amd8132
+subdirs-$(SOUTHBRIDGE_AMD_AMD8151) += amd8151
+subdirs-$(SOUTHBRIDGE_AMD_RS690) += rs690
+subdirs-$(SOUTHBRIDGE_AMD_SB600) += sb600
+
+subdirs-$(SOUTHBRIDGE_AMD_CS5530) += cs5530
+subdirs-$(SOUTHBRIDGE_AMD_CS5535) += cs5535
+subdirs-$(SOUTHBRIDGE_AMD_CS5536) += cs5536
+

Added: trunk/coreboot-v2/src/southbridge/amd/amd8111/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/amd8111/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/amd/amd8111/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config SOUTHBRIDGE_AMD_AMD8111
+	bool
+	default n
+

Added: trunk/coreboot-v2/src/southbridge/broadcom/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/broadcom/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/broadcom/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,3 @@
+source src/southbridge/broadcom/bcm21000/Kconfig
+source src/southbridge/broadcom/bcm5780/Kconfig
+source src/southbridge/broadcom/bcm5785/Kconfig

Added: trunk/coreboot-v2/src/southbridge/broadcom/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/broadcom/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/broadcom/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,4 @@
+subdirs-y += bcm21000
+subdirs-y += bcm5780
+subdirs-y += bcm5785
+

Added: trunk/coreboot-v2/src/southbridge/intel/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/intel/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,10 @@
+#source src/southbridge/intel/esb6300/Kconfig
+#source src/southbridge/intel/i3100/Kconfig
+source src/southbridge/intel/i82371eb/Kconfig
+#source src/southbridge/intel/i82801ca/Kconfig
+#source src/southbridge/intel/i82801dbm/Kconfig
+#source src/southbridge/intel/i82801er/Kconfig
+source src/southbridge/intel/i82801gx/Kconfig
+source src/southbridge/intel/i82801xx/Kconfig
+#source src/southbridge/intel/i82870/Kconfig
+#source src/southbridge/intel/pxhd/Kconfig

Added: trunk/coreboot-v2/src/southbridge/intel/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/intel/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,11 @@
+#subdirs-y += esb6300
+#subdirs-y += i3100
+subdirs-y += i82371eb
+#subdirs-y += i82801ca
+#subdirs-y += i82801dbm
+#subdirs-y += i82801er
+subdirs-y += i82801gx
+subdirs-y += i82801xx
+#subdirs-y += i82870
+#subdirs-y += pxhd
+

Added: trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,3 @@
+config SOUTHBRIDGE_INTEL_I82371EB
+        boolean
+

Added: trunk/coreboot-v2/src/southbridge/intel/i82371eb/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82371eb/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/intel/i82371eb/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) +=  i82371eb.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) +=  i82371eb_isa.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) +=  i82371eb_ide.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) +=  i82371eb_usb.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) +=  i82371eb_smbus.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) +=  i82371eb_reset.o
+
+#initobj-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb_early_rom.o

Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801gx/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config SOUTHBRIDGE_INTEL_I82801GX
+	bool
+	default n
+

Added: trunk/coreboot-v2/src/southbridge/intel/i82801gx/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801gx/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801gx/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,40 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008-2009 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_ac97.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_azalia.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_ide.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_lpc.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_nic.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_pci.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_pcie.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_sata.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_smbus.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_usb.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_usb_ehci.o
+
+object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_reset.o
+object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_watchdog.o
+
+# arg. How does the linux kconfig handle compound conditionals?
+ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
+	object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_smi.o
+	smmobj-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) +=  i82801gx_smihandler.o
+endif

Added: trunk/coreboot-v2/src/southbridge/intel/i82801xx/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config SOUTHBRIDGE_INTEL_I82801XX
+	bool
+	default n
+

Added: trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801xx/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_ac97.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_ide.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_lpc.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_nic.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_pci.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_sata.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_smbus.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_usb.o
+driver-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_usb_ehci.o
+
+object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_reset.o
+object-$(CONFIG_SOUTHBRIDGE_INTEL_I82801XX) +=  i82801xx_watchdog.o
+
+# TODO: What about cmos_failover.c?
+

Added: trunk/coreboot-v2/src/southbridge/nvidia/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/nvidia/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+source src/southbridge/nvidia/ck804/Kconfig
+source src/southbridge/nvidia/mcp55/Kconfig

Added: trunk/coreboot-v2/src/southbridge/nvidia/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/nvidia/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,3 @@
+subdirs-y += ck804
+subdirs-y += mcp55
+

Added: trunk/coreboot-v2/src/southbridge/ricoh/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/ricoh/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/ricoh/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+source src/southbridge/ricoh/rl5c476/Kconfig

Added: trunk/coreboot-v2/src/southbridge/ricoh/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/ricoh/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/ricoh/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+subdirs-y += rl5c476

Added: trunk/coreboot-v2/src/southbridge/sis/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/sis/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/sis/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+source src/southbridge/sis/sis966/Kconfig

Added: trunk/coreboot-v2/src/southbridge/sis/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/sis/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/sis/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+subdirs-y += sis966
+

Added: trunk/coreboot-v2/src/southbridge/via/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/via/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,5 @@
+source src/southbridge/via/k8t890/Kconfig
+source src/southbridge/via/vt8231/Kconfig
+source src/southbridge/via/vt8235/Kconfig
+source src/southbridge/via/vt8237r/Kconfig
+source src/southbridge/via/vt82c686/Kconfig

Added: trunk/coreboot-v2/src/southbridge/via/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/via/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,5 @@
+subdirs-y += k8t890
+subdirs-y += vt8231
+subdirs-y += vt8235
+subdirs-y += vt8237r
+subdirs-y += vt82c686

Added: trunk/coreboot-v2/src/southbridge/winbond/Kconfig
===================================================================
--- trunk/coreboot-v2/src/southbridge/winbond/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/winbond/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+source src/southbridge/winbond/w83c553/Kconfig

Added: trunk/coreboot-v2/src/southbridge/winbond/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/southbridge/winbond/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/winbond/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+subdirs-y += w83c553

Added: trunk/coreboot-v2/src/superio/Kconfig
===================================================================
--- trunk/coreboot-v2/src/superio/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,8 @@
+source src/superio/fintek/Kconfig
+source src/superio/intel/Kconfig
+source src/superio/ite/Kconfig
+source src/superio/nsc/Kconfig
+source src/superio/serverengines/Kconfig
+source src/superio/smsc/Kconfig
+source src/superio/via/Kconfig
+source src/superio/winbond/Kconfig

Added: trunk/coreboot-v2/src/superio/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,10 @@
+
+subdirs-y += fintek 
+subdirs-y += intel
+subdirs-y += ite
+subdirs-y += nsc
+#subdirs-y += serverengine
+subdirs-y += smsc
+subdirs-y += via
+subdirs-y += winbond
+

Added: trunk/coreboot-v2/src/superio/fintek/Kconfig
===================================================================
--- trunk/coreboot-v2/src/superio/fintek/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/fintek/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+config SUPERIO_FINTEK_F71805F
+	bool

Added: trunk/coreboot-v2/src/superio/fintek/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/fintek/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/fintek/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+subdirs-y += f71805f

Added: trunk/coreboot-v2/src/superio/fintek/f71805f/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/fintek/f71805f/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/fintek/f71805f/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Corey Osgood <corey.osgood at gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_FINTEK_F71805F) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/intel/Kconfig
===================================================================
--- trunk/coreboot-v2/src/superio/intel/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/intel/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+config SUPERIO_FINTEK_I3100
+	bool

Added: trunk/coreboot-v2/src/superio/intel/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/intel/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/intel/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+subdirs-y += i3100

Added: trunk/coreboot-v2/src/superio/intel/i3100/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/intel/i3100/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/intel/i3100/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Arastra, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_INTEL_I3100) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/ite/Kconfig
===================================================================
--- trunk/coreboot-v2/src/superio/ite/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/ite/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,14 @@
+config SUPERIO_ITE_IT8661F
+	bool
+config SUPERIO_ITE_IT8671F
+	bool
+config SUPERIO_ITE_IT8673F
+	bool
+config SUPERIO_ITE_IT8705F
+	bool
+config SUPERIO_ITE_IT8712F
+	bool
+config SUPERIO_ITE_IT8716F
+	bool
+config SUPERIO_ITE_IT8718F
+	bool

Added: trunk/coreboot-v2/src/superio/ite/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/ite/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/ite/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,7 @@
+subdirs-y += it8661f
+subdirs-y += it8671f
+subdirs-y += it8673f
+subdirs-y += it8705f
+subdirs-y += it8712f
+subdirs-y += it8716f
+subdirs-y += it8718f

Added: trunk/coreboot-v2/src/superio/ite/it8661f/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8661f/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/ite/it8661f/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8661F) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/ite/it8671f/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8671f/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/ite/it8671f/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8671F) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/ite/it8673f/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8673f/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/ite/it8673f/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8673F) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/ite/it8705f/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8705f/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/ite/it8705f/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8705F) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/ite/it8712f/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8712f/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/ite/it8712f/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8712F) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/ite/it8716f/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8716f/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/ite/it8716f/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8716F) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/ite/it8718f/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/ite/it8718f/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/ite/it8718f/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_ITE_IT8718F) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/nsc/Kconfig
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/nsc/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,18 @@
+config SUPERIO_NSC_PC8374
+	bool
+config SUPERIO_NSC_PC87309
+	bool
+config SUPERIO_NSC_PC87351
+	bool
+config SUPERIO_NSC_PC87360
+	bool
+config SUPERIO_NSC_PC87366
+	bool
+config SUPERIO_NSC_PC87417
+	bool
+config SUPERIO_NSC_PC87427
+	bool
+config SUPERIO_NSC_PC97307
+	bool
+config SUPERIO_NSC_PC97317
+	bool

Added: trunk/coreboot-v2/src/superio/nsc/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/nsc/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,9 @@
+subdirs-y += pc8374
+subdirs-y += pc87309
+subdirs-y += pc87351
+subdirs-y += pc87360
+subdirs-y += pc87366
+subdirs-y += pc87417
+subdirs-y += pc87427
+subdirs-y += pc97307
+subdirs-y += pc97317

Added: trunk/coreboot-v2/src/superio/nsc/pc8374/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc8374/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/nsc/pc8374/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC8374) +=  superio.o

Added: trunk/coreboot-v2/src/superio/nsc/pc87309/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc87309/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/nsc/pc87309/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+## 
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC87309) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/nsc/pc87351/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc87351/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/nsc/pc87351/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC87351) +=  superio.o

Added: trunk/coreboot-v2/src/superio/nsc/pc87360/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc87360/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/nsc/pc87360/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC87360) +=  superio.o

Added: trunk/coreboot-v2/src/superio/nsc/pc87366/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc87366/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/nsc/pc87366/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC87366) +=  superio.o

Added: trunk/coreboot-v2/src/superio/nsc/pc87417/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc87417/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/nsc/pc87417/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC87417) +=  superio.o

Added: trunk/coreboot-v2/src/superio/nsc/pc87427/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc87427/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/nsc/pc87427/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC87427) +=  superio.o

Added: trunk/coreboot-v2/src/superio/nsc/pc97307/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc97307/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/nsc/pc97307/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC97307) +=  superio.o

Added: trunk/coreboot-v2/src/superio/nsc/pc97317/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/nsc/pc97317/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/nsc/pc97317/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_NSC_PC97317) +=  superio.o

Added: trunk/coreboot-v2/src/superio/serverengines/Kconfig
===================================================================
--- trunk/coreboot-v2/src/superio/serverengines/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/serverengines/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+config SERVERENGINES_ITE_PILOT
+	bool

Added: trunk/coreboot-v2/src/superio/smsc/Kconfig
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/smsc/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,12 @@
+config SUPERIO_SMCSC_FDC37M60X
+	bool
+config SUPERIO_SMCSC_LPC47B272
+	bool
+config SUPERIO_SMCSC_LPC47B397
+	bool
+config SUPERIO_SMCSC_LPC47M10X
+	bool
+config SUPERIO_SMCSC_LPC47N217
+	bool
+config SUPERIO_SMCSC_SMSCSUPERIO
+	bool

Added: trunk/coreboot-v2/src/superio/smsc/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/smsc/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,6 @@
+subdirs-y += fdc37m60x
+subdirs-y += lpc47b272
+subdirs-y += lpc47b397
+subdirs-y += lpc47m10x
+subdirs-y += lpc47n217
+subdirs-y += smscsuperio

Added: trunk/coreboot-v2/src/superio/smsc/fdc37m60x/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/fdc37m60x/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/smsc/fdc37m60x/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2006 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_SMSC_FDC37M60X) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/smsc/lpc47b272/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47b272/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47b272/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2005 Digital Design Corporation
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_SMSC_DEVICE) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/smsc/lpc47b397/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47b397/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_SMSC_LPC47B397) +=  superio.o

Added: trunk/coreboot-v2/src/superio/smsc/lpc47m10x/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47m10x/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47m10x/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_SMSC_LPC47M10X) +=  superio.o

Added: trunk/coreboot-v2/src/superio/smsc/lpc47n217/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47n217/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47n217/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,22 @@
+## 
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2005 Digital Design Corporation
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_SMSC_LPC47N217) +=  superio.o

Added: trunk/coreboot-v2/src/superio/smsc/smscsuperio/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/smscsuperio/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/smsc/smscsuperio/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/via/Kconfig
===================================================================
--- trunk/coreboot-v2/src/superio/via/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/via/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+config SUPERIO_VIA_VT1211
+	bool

Added: trunk/coreboot-v2/src/superio/via/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/via/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/via/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1 @@
+subdirs-y += vt1211

Added: trunk/coreboot-v2/src/superio/via/vt1211/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/via/vt1211/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/via/vt1211/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_VIA_VT1211) +=  vt1211.o

Added: trunk/coreboot-v2/src/superio/winbond/Kconfig
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/Kconfig	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/winbond/Kconfig	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,18 @@
+config SUPERIO_WINBOND_W83627DHG
+	boolean
+config SUPERIO_WINBOND_W83627EHG
+	boolean
+config SUPERIO_WINBOND_W83627HF
+	boolean
+config SUPERIO_WINBOND_W83627THF
+	boolean
+config SUPERIO_WINBOND_W83627THG
+	boolean
+config SUPERIO_WINBOND_W83627UHG
+	boolean
+config SUPERIO_WINBOND_W83697HF
+	boolean
+config SUPERIO_WINBOND_W83977F
+	boolean
+config SUPERIO_WINBOND_W83977TF
+	boolean

Added: trunk/coreboot-v2/src/superio/winbond/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/winbond/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,9 @@
+subdirs-y += w83627dhg
+subdirs-y += w83627ehg
+subdirs-y += w83627hf
+subdirs-y += w83627thf
+subdirs-y += w83627thg
+subdirs-y += w83627uhg
+subdirs-y += w83697hf
+subdirs-y += w83977f
+subdirs-y += w83977tf

Added: trunk/coreboot-v2/src/superio/winbond/w83627dhg/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627dhg/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/winbond/w83627dhg/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Uwe Hermann <uwe at hermann-uwe.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83627DHG) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/winbond/w83627ehg/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627ehg/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/winbond/w83627ehg/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,24 @@
+## 
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007 AMD
+## Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83627EHG) +=  superio.o
+

Added: trunk/coreboot-v2/src/superio/winbond/w83627hf/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627hf/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/winbond/w83627hf/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83627HF) +=  superio.o

Added: trunk/coreboot-v2/src/superio/winbond/w83627thf/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627thf/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/winbond/w83627thf/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83627THF) +=  superio.o

Added: trunk/coreboot-v2/src/superio/winbond/w83627thg/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627thg/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/winbond/w83627thg/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83627THG) +=  superio.o

Added: trunk/coreboot-v2/src/superio/winbond/w83627uhg/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627uhg/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/winbond/w83627uhg/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Dynon Avionics
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 $
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83627UHG) +=  superio.o

Added: trunk/coreboot-v2/src/superio/winbond/w83697hf/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83697hf/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/winbond/w83697hf/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Sean Nelson <snelson at nmt.edu>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83697HF) +=  superio.o

Added: trunk/coreboot-v2/src/superio/winbond/w83977f/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83977f/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/winbond/w83977f/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,22 @@
+## 
+## This file is part of the coreboot project.
+## 
+## Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov at gmail.com>
+## 
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+## 
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+## 
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+## 
+
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83977F) +=  superio.o

Added: trunk/coreboot-v2/src/superio/winbond/w83977tf/Makefile.inc
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83977tf/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/src/superio/winbond/w83977tf/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2 @@
+#config chip.h
+obj-$(CONFIG_SUPERIO_WINBOND_W83977TF) +=  superio.o

Modified: trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb	2009-08-12 05:49:48 UTC (rev 4533)
+++ trunk/coreboot-v2/targets/kontron/986lcd-m/Config.lb	2009-08-12 15:00:51 UTC (rev 4534)
@@ -5,9 +5,14 @@
 ## (normal AND fallback images and payloads).
 option CONFIG_ROM_SIZE = 1024 * 1024
 
+option CONFIG_CBFS=1
+option HAVE_HIGH_TABLES=1
+option MAXIMUM_CONSOLE_LOGLEVEL=9
+option DEFAULT_CONSOLE_LOGLEVEL=9
+
 romimage "fallback"
 	option CONFIG_USE_FALLBACK_IMAGE = 1
-	payload ../payload.elf
+	payload /tmp/bios.bin.elf
 end
 
 buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"

Modified: trunk/coreboot-v2/util/abuild/abuild
===================================================================
--- trunk/coreboot-v2/util/abuild/abuild	2009-08-12 05:49:48 UTC (rev 4533)
+++ trunk/coreboot-v2/util/abuild/abuild	2009-08-12 15:00:51 UTC (rev 4534)
@@ -103,7 +103,7 @@
 {
 	# make this a function so we can easily select
 	# without breaking readability
-	ls -1 "$LBROOT/src/mainboard" | grep -v CVS
+	ls -1 "$LBROOT/src/mainboard" | grep -v Kconfig
 }
 
 function mainboards
@@ -113,7 +113,7 @@
 	
 	VENDOR=$1
 	
-	ls -1 $LBROOT/src/mainboard/$VENDOR | grep -v CVS 
+	ls -1 $LBROOT/src/mainboard/$VENDOR | grep -v Kconfig
 }
 
 function architecture

Added: trunk/coreboot-v2/util/cbfstool/Makefile.inc
===================================================================
--- trunk/coreboot-v2/util/cbfstool/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/util/cbfstool/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,39 @@
+#
+#
+#
+
+ifdef POST_EVALUATION
+
+cbfsobj :=
+# commands
+cbfsobj += create.o
+cbfsobj += bootblock.o
+cbfsobj += delete.o
+cbfsobj += extract.o 
+cbfsobj += add.o 
+cbfsobj += print.o
+cbfsobj += resize.o
+# main tool
+cbfsobj += cbfstool.o
+cbfsobj += util.o
+cbfsobj += fs.o
+
+cbfsinc := cbfstool.h cbfs.h
+
+$(obj)/util/cbfstool:
+	$(Q)mkdir -p $@
+	$(Q)mkdir -p $@/tools/lzma
+
+$(obj)/util/cbfstool/%.o: $(top)/util/cbfstool/%.c
+	$(Q)printf "    HOSTCC     $(subst $(obj)/,,$(@))\n"
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) -c -o $@ $<
+
+$(obj)/util/cbfstool/cbfstool: $(obj)/util/cbfstool $(obj)/util/cbfstool/tools/cbfs-mkpayload $(obj)/util/cbfstool/tools/cbfs-mkstage $(addprefix $(obj)/util/cbfstool/,$(cbfsobj))
+	$(Q)printf "    HOSTCC     $(subst $(obj)/,,$(@)) (link)\n"
+	$(Q)$(HOSTCC) -o $@ $(addprefix $(obj)/util/cbfstool/,$(cbfsobj))
+
+endif
+
+include $(top)/util/cbfstool/tools/Makefile.inc
+
+

Added: trunk/coreboot-v2/util/cbfstool/tools/Makefile.inc
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/util/cbfstool/tools/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,23 @@
+
+tobj ?= $(obj)/util/cbfstool/tools
+tsrc ?= $(top)/util/cbfstool/tools
+
+include $(tsrc)/lzma/Makefile.inc
+
+COMMON = common.o compress.o $(LZMA_OBJ)
+
+ifdef POST_EVALUATION
+
+$(tobj)/cbfs-mkstage: $(tobj)/cbfs-mkstage.o $(patsubst %,$(tobj)/%,$(COMMON))
+	$(Q)printf "    HOSTCXX    $(subst $(obj)/,,$(@)) (link)\n"
+	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ $^
+
+$(tobj)/cbfs-mkpayload: $(tobj)/cbfs-mkpayload.o $(patsubst %,$(tobj)/%,$(COMMON))
+	$(Q)printf "    HOSTCXX    $(subst $(obj)/,,$(@)) (link)\n"
+	$(Q)$(HOSTCXX) $(HOSTCFLAGS) -o $@ $^
+
+$(tobj)/%.o: $(tsrc)/%.c
+	$(Q)printf "    HOSTCC     $(subst $(obj)/,,$(@))\n"
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) -c -o $@ $<
+
+endif

Added: trunk/coreboot-v2/util/cbfstool/tools/lzma/Makefile.inc
===================================================================
--- trunk/coreboot-v2/util/cbfstool/tools/lzma/Makefile.inc	                        (rev 0)
+++ trunk/coreboot-v2/util/cbfstool/tools/lzma/Makefile.inc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,60 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+LZMA_OBJ := lzma/LZMAEncoder.o lzma/LZInWindow.o
+LZMA_OBJ += lzma/RangeCoderBit.o lzma/StreamUtils.o
+LZMA_OBJ += lzma/OutBuffer.o lzma/Alloc.o
+LZMA_OBJ += lzma/CRC.o
+LZMA_OBJ += lzma/lzma-compress.o
+
+ifdef POST_EVALUATION
+$(tobj)/lzma/lzma-compress.o: $(tsrc)/lzma/minilzma.cc
+	$(Q)printf "    HOSTCXX    $(subst $(obj)/,,$(@))\n"
+	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c -DCOMPACT $<
+
+$(tobj)/lzma/%.o: $(tsrc)/lzma/C/7zip/Compress/LZMA/%.cpp
+	$(Q)printf "    HOSTCXX    $(subst $(obj)/,,$(@))\n"
+	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
+
+$(tobj)/lzma/%.o: $(tsrc)/lzma/C/7zip/Compress/LZ/%.cpp
+	$(Q)printf "    HOSTCXX    $(subst $(obj)/,,$(@))\n"
+	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
+
+$(tobj)/lzma/%.o: $(tsrc)/lzma/C/7zip/Compress/RangeCoder/%.cpp
+	$(Q)printf "    HOSTCXX    $(subst $(obj)/,,$(@))\n"
+	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
+
+$(tobj)/lzma/%.o: $(tsrc)/lzma/C/7zip/Decompress/%.cpp
+	$(Q)printf "    HOSTCXX    $(subst $(obj)/,,$(@))\n"
+	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
+
+$(tobj)/lzma/%.o: $(tsrc)/lzma/C/7zip/Common/%.cpp
+	$(Q)printf "    HOSTCXX    $(subst $(obj)/,,$(@))\n"
+	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
+
+$(tobj)/lzma/%.o: $(tsrc)/lzma/C/Common/%.cpp
+	$(Q)printf "    HOSTCXX    $(subst $(obj)/,,$(@))\n"
+	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
+
+$(tobj)/lzma/%.o: $(tsrc)/lzma/%.cc
+	$(Q)printf "    HOSTCXX    $(subst $(obj)/,,$(@))\n"
+	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) -o $@ -c $<
+
+endif

Added: trunk/coreboot-v2/util/kconfig/Makefile
===================================================================
--- trunk/coreboot-v2/util/kconfig/Makefile	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/Makefile	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,337 @@
+# ===========================================================================
+# Kernel configuration targets
+# These targets are used from top-level makefile
+
+PHONY += oldconfig xconfig gconfig menuconfig config silentoldconfig update-po-config
+
+Kconfig := src/Kconfig
+
+xconfig: prepare $(objk)/qconf
+	$(Q)$(objk)/qconf $(Kconfig)
+
+gconfig: prepare $(objk)/gconf
+	$(Q)$(objk)/gconf $(Kconfig)
+
+menuconfig: prepare $(objk)/mconf
+	$(Q)$(objk)/mconf $(Kconfig)
+
+config: prepare $(objk)/conf
+	$(Q)$(objk)/conf $(Kconfig)
+
+oldconfig: prepare $(objk)/conf
+	$(Q)$(objk)/conf -o $(Kconfig)
+
+silentoldconfig: prepare $(objk)/conf
+	$(Q)$(objk)/conf -s $(Kconfig)
+
+# --- UNUSED, ignore ----------------------------------------------------------
+# Create new linux.pot file
+# Adjust charset to UTF-8 in .po file to accept UTF-8 in Kconfig files
+# The symlink is used to repair a deficiency in arch/um
+update-po-config: $(obj)/kxgettext $(obj)/gconf.glade.h
+	$(Q)echo "  GEN config"
+	$(Q)xgettext --default-domain=linux              \
+	    --add-comments --keyword=_ --keyword=N_      \
+	    --from-code=UTF-8                            \
+	    --files-from=scripts/kconfig/POTFILES.in     \
+	    --output $(obj)/config.pot
+	$(Q)sed -i s/CHARSET/UTF-8/ $(obj)/config.pot
+	$(Q)ln -fs Kconfig.i386 arch/um/Kconfig.arch
+	$(Q)(for i in `ls arch/`;                        \
+	    do                                           \
+		echo "  GEN $$i";                        \
+		$(obj)/kxgettext arch/$$i/Kconfig        \
+		     >> $(obj)/config.pot;               \
+	    done )
+	$(Q)msguniq --sort-by-file --to-code=UTF-8 $(obj)/config.pot \
+	    --output $(obj)/linux.pot
+	$(Q)rm -f arch/um/Kconfig.arch
+	$(Q)rm -f $(obj)/config.pot
+# --- UNUSED, ignore ----------------------------------------------------------
+
+PHONY += randconfig allyesconfig allnoconfig allmodconfig defconfig
+
+randconfig: prepare $(objk)/conf
+	$(Q)$(objk)/conf -r $(Kconfig)
+
+allyesconfig: prepare $(objk)/conf
+	$(Q)$(objk)/conf -y $(Kconfig)
+
+allnoconfig: prepare $(objk)/conf
+	$(Q)$(objk)/conf -n $(Kconfig)
+
+allmodconfig: prepare $(objk)/conf
+	$(Q)$(objk)/conf -m $(Kconfig)
+
+defconfig: prepare $(objk)/conf
+ifeq ($(KBUILD_DEFCONFIG),)
+	$(Q)$(objk)/conf -d $(Kconfig)
+else
+	@echo "*** Default configuration is based on '$(KBUILD_DEFCONFIG)'"
+	$(Q)$(objk)/conf -D $(KBUILD_DEFCONFIG) $(Kconfig)
+endif
+
+%_defconfig: prepare $(objk)/conf
+	$(Q)$(objk)/conf -D configs/$@ $(Kconfig)
+
+# Help text used by make help
+help:
+	@echo  '  config	  - Update current config utilising a line-oriented program'
+	@echo  '  menuconfig	  - Update current config utilising a menu based program'
+	@echo  '  xconfig	  - Update current config utilising a QT based front-end'
+	@echo  '  gconfig	  - Update current config utilising a GTK based front-end'
+	@echo  '  oldconfig	  - Update current config utilising a provided .config as base'
+	@echo  '  silentoldconfig - Same as oldconfig, but quietly'
+	@echo  '  randconfig	  - New config with random answer to all options'
+	@echo  '  defconfig	  - New config with default answer to all options'
+	@echo  '  allmodconfig	  - New config selecting modules when possible'
+	@echo  '  allyesconfig	  - New config where all options are accepted with yes'
+	@echo  '  allnoconfig	  - New config where all options are answered with no'
+
+# lxdialog stuff
+check-lxdialog  := $(srck)/lxdialog/check-lxdialog.sh
+
+# Use recursively expanded variables so we do not call gcc unless
+# we really need to do so. (Do not call gcc as part of make mrproper)
+HOST_EXTRACFLAGS = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ccflags)
+HOST_LOADLIBES   = $(shell $(CONFIG_SHELL) $(check-lxdialog) -ldflags $(HOSTCC))
+
+HOST_EXTRACFLAGS += -DLOCALE
+
+
+# ===========================================================================
+# Shared Makefile for the various kconfig executables:
+# conf:	  Used for defconfig, oldconfig and related targets
+# mconf:  Used for the mconfig target.
+#         Utilizes the lxdialog package
+# qconf:  Used for the xconfig target
+#         Based on QT which needs to be installed to compile it
+# gconf:  Used for the gconfig target
+#         Based on GTK which needs to be installed to compile it
+# object files used by all kconfig flavours
+
+lxdialog := lxdialog/checklist.o lxdialog/util.o lxdialog/inputbox.o
+lxdialog += lxdialog/textbox.o lxdialog/yesno.o lxdialog/menubox.o
+
+conf-objs	:= conf.o  zconf.tab.o
+mconf-objs	:= mconf.o zconf.tab.o $(lxdialog)
+kxgettext-objs	:= kxgettext.o zconf.tab.o
+
+hostprogs-y := conf qconf gconf kxgettext
+
+ifeq ($(MAKECMDGOALS),menuconfig)
+	hostprogs-y += mconf
+endif
+
+ifeq ($(MAKECMDGOALS),xconfig)
+	qconf-target := 1
+endif
+ifeq ($(MAKECMDGOALS),gconfig)
+	gconf-target := 1
+endif
+
+
+ifeq ($(qconf-target),1)
+qconf-cxxobjs	:= qconf.o
+qconf-objs	:= kconfig_load.o zconf.tab.o
+endif
+
+ifeq ($(gconf-target),1)
+gconf-objs	:= gconf.o kconfig_load.o zconf.tab.o
+endif
+
+clean-files	:= lkc_defs.h qconf.moc .tmp_qtcheck \
+		   .tmp_gtkcheck zconf.tab.c lex.zconf.c zconf.hash.c gconf.glade.h
+clean-files     += mconf qconf gconf
+clean-files     += config.pot coreinfo.pot
+
+# Check that we have the required ncurses stuff installed for lxdialog (menuconfig)
+PHONY += $(objk)/dochecklxdialog
+$(addprefix $(obj)/,$(lxdialog)): $(objk)/dochecklxdialog
+$(objk)/dochecklxdialog:
+	$(Q)$(CONFIG_SHELL) $(check-lxdialog) -check $(HOSTCC) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES)
+
+always := dochecklxdialog
+
+# Add environment specific flags
+HOST_EXTRACFLAGS += $(shell $(CONFIG_SHELL) $(srck)/check.sh $(HOSTCC) $(HOSTCFLAGS))
+
+# generated files seem to need this to find local include files
+HOSTCFLAGS_lex.zconf.o	:= -I$(src)
+HOSTCFLAGS_zconf.tab.o	:= -I$(src)
+
+HOSTLOADLIBES_qconf	= $(KC_QT_LIBS) -ldl
+HOSTCXXFLAGS_qconf.o	= $(KC_QT_CFLAGS) -D LKC_DIRECT_LINK
+
+HOSTLOADLIBES_gconf	= `pkg-config --libs gtk+-2.0 gmodule-2.0 libglade-2.0`
+HOSTCFLAGS_gconf.o	= `pkg-config --cflags gtk+-2.0 gmodule-2.0 libglade-2.0` \
+                          -D LKC_DIRECT_LINK
+
+$(objk)/qconf.o: $(objk)/.tmp_qtcheck
+
+ifeq ($(qconf-target),1)
+$(objk)/.tmp_qtcheck: $(srck)/Makefile
+-include $(objk)/.tmp_qtcheck
+
+# QT needs some extra effort...
+$(objk)/.tmp_qtcheck: prepare
+	@set -e; dir=""; pkg=""; \
+	pkg-config --exists qt 2> /dev/null && pkg=qt; \
+	pkg-config --exists qt-mt 2> /dev/null && pkg=qt-mt; \
+	if [ -n "$$pkg" ]; then \
+	  cflags="\$$(shell pkg-config $$pkg --cflags)"; \
+	  libs="\$$(shell pkg-config $$pkg --libs)"; \
+	  moc="\$$(shell pkg-config $$pkg --variable=prefix)/bin/moc"; \
+	  dir="$$(pkg-config $$pkg --variable=prefix)"; \
+	else \
+	  for d in $$QTDIR /usr/share/qt* /usr/lib/qt*; do \
+	    if [ -f $$d/include/qconfig.h ]; then dir=$$d; break; fi; \
+	  done; \
+	  if [ -z "$$dir" ]; then \
+	    echo "*"; \
+	    echo "* Unable to find the QT3 installation. Please make sure that"; \
+	    echo "* the QT3 development package is correctly installed and"; \
+	    echo "* either install pkg-config or set the QTDIR environment"; \
+	    echo "* variable to the correct location."; \
+	    echo "*"; \
+	    false; \
+	  fi; \
+	  libpath=$$dir/lib; lib=qt; osdir=""; \
+	  $(HOSTCXX) -print-multi-os-directory > /dev/null 2>&1 && \
+	    osdir=x$$($(HOSTCXX) -print-multi-os-directory); \
+	  test -d $$libpath/$$osdir && libpath=$$libpath/$$osdir; \
+	  test -f $$libpath/libqt-mt.so && lib=qt-mt; \
+	  cflags="-I$$dir/include"; \
+	  libs="-L$$libpath -Wl,-rpath,$$libpath -l$$lib"; \
+	  moc="$$dir/bin/moc"; \
+	fi; \
+	if [ ! -x $$dir/bin/moc -a -x /usr/bin/moc ]; then \
+	  echo "*"; \
+	  echo "* Unable to find $$dir/bin/moc, using /usr/bin/moc instead."; \
+	  echo "*"; \
+	  moc="/usr/bin/moc"; \
+	fi; \
+	echo "KC_QT_CFLAGS=$$cflags" > $@; \
+	echo "KC_QT_LIBS=$$libs" >> $@; \
+	echo "KC_QT_MOC=$$moc" >> $@
+endif
+
+$(objk)/gconf.o: $(objk)/.tmp_gtkcheck
+
+ifeq ($(gconf-target),1)
+-include $(objk)/.tmp_gtkcheck
+
+# GTK needs some extra effort, too...
+$(objk)/.tmp_gtkcheck: prepare
+	@if `pkg-config --exists gtk+-2.0 gmodule-2.0 libglade-2.0`; then		\
+		if `pkg-config --atleast-version=2.0.0 gtk+-2.0`; then			\
+			touch $@;								\
+		else									\
+			echo "*"; 							\
+			echo "* GTK+ is present but version >= 2.0.0 is required.";	\
+			echo "*";							\
+			false;								\
+		fi									\
+	else										\
+		echo "*"; 								\
+		echo "* Unable to find the GTK+ installation. Please make sure that"; 	\
+		echo "* the GTK+ 2.0 development package is correctly installed..."; 	\
+		echo "* You need gtk+-2.0, glib-2.0 and libglade-2.0."; 		\
+		echo "*"; 								\
+		false;									\
+	fi
+endif
+
+# --- UNUSED, ignore ----------------------------------------------------------
+ifdef UNUSED
+$(obj)/zconf.tab.o: $(obj)/lex.zconf.c $(obj)/zconf.hash.c
+
+$(obj)/kconfig_load.o: $(obj)/lkc_defs.h
+
+$(obj)/qconf.o: $(obj)/qconf.moc $(obj)/lkc_defs.h
+
+$(obj)/gconf.o: $(obj)/lkc_defs.h
+
+$(obj)/%.moc: $(src)/%.h
+	$(KC_QT_MOC) -i $< -o $@
+
+$(obj)/lkc_defs.h: $(src)/lkc_proto.h
+	sed < $< > $@ 's/P(\([^,]*\),.*/#define \1 (\*\1_p)/'
+
+# Extract gconf menu items for I18N support
+$(obj)/gconf.glade.h: $(obj)/gconf.glade
+	intltool-extract --type=gettext/glade $(obj)/gconf.glade
+endif
+# --- UNUSED, ignore ----------------------------------------------------------
+
+###
+# The following requires flex/bison/gperf
+# By default we use the _shipped versions, uncomment the following line if
+# you are modifying the flex/bison src.
+# LKC_GENPARSER := 1
+
+ifdef LKC_GENPARSER
+
+# --- UNUSED, ignore ----------------------------------------------------------
+$(obj)/zconf.tab.c: $(src)/zconf.y
+$(obj)/lex.zconf.c: $(src)/zconf.l
+$(obj)/zconf.hash.c: $(src)/zconf.gperf
+
+%.tab.c: %.y
+	bison -l -b $* -p $(notdir $*) $<
+	cp $@ $@_shipped
+
+lex.%.c: %.l
+	flex -L -P$(notdir $*) -o$@ $<
+	cp $@ $@_shipped
+
+%.hash.c: %.gperf
+	gperf < $< > $@
+	cp $@ $@_shipped
+# --- UNUSED, ignore ----------------------------------------------------------
+
+endif
+
+$(objk)/qconf: $(patsubst %,$(objk)/%,$(qconf-cxxobjs)) \
+	       $(patsubst %,$(objk)/%,$(qconf-objs))
+	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTLOADLIBES_qconf) -o $@ $^
+$(objk)/gconf: $(patsubst %,$(objk)/%,$(gconf-objs))
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOSTLOADLIBES_gconf) -o $@ $^
+$(objk)/mconf: $(patsubst %,$(objk)/%,$(mconf-objs))
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) -o $@ $^
+$(objk)/conf: $(patsubst %,$(objk)/%,$(conf-objs))
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -o $@ $^
+
+$(objk)/mconf.o: $(srck)/mconf.c
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $<
+$(objk)/conf.o: $(srck)/conf.c
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $<
+
+$(objk)/zconf.tab.o: $(objk)/zconf.tab.c $(objk)/lex.zconf.c \
+		     $(objk)/zconf.hash.c
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) -c -o $@ $(objk)/zconf.tab.c
+$(objk)/kconfig_load.o: $(srck)/kconfig_load.c $(objk)/lkc_defs.h
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) -c -o $@ $<
+$(objk)/qconf.o: $(srck)/qconf.cc $(objk)/qconf.moc $(objk)/lkc_defs.h
+	$(Q)$(HOSTCXX) $(HOSTCXXFLAGS) $(HOSTCXXFLAGS_qconf.o) -c -o $@ $<
+$(objk)/gconf.o: $(srck)/gconf.c $(objk)/lkc_defs.h
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOSTCFLAGS_gconf.o) -c -o $@ $<
+$(objk)/%.moc: $(srck)/%.h
+	$(Q)$(KC_QT_MOC) -i $< -o $@
+$(objk)/lkc_defs.h: $(srck)/lkc_proto.h
+	$(Q)sed < $< > $@ 's/P(\([^,]*\),.*/#define \1 (\*\1_p)/'
+
+$(objk)/lex.zconf.c: $(srck)/lex.zconf.c_shipped
+	$(Q)cp $< $@
+$(objk)/zconf.hash.c: $(srck)/zconf.hash.c_shipped
+	$(Q)cp $< $@
+$(objk)/zconf.tab.c: $(srck)/zconf.tab.c_shipped
+	$(Q)cp $< $@
+
+$(objk)/lxdialog/lxdialog: $(objk)/dochecklxdialog \
+			   $(patsubst %,$(objk)/lxdialog/%,$(lxdialog))
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOST_LOADLIBES) \
+		$(patsubst %,$(objk)/lxdialog/%,$(lxdialog)) -o $@
+$(objk)/lxdialog/%.o: $(srck)/lxdialog/%.c
+	$(Q)$(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $^ -c -o $@
+

Added: trunk/coreboot-v2/util/kconfig/POTFILES.in
===================================================================
--- trunk/coreboot-v2/util/kconfig/POTFILES.in	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/POTFILES.in	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,12 @@
+util/kconfig/lxdialog/checklist.c
+util/kconfig/lxdialog/inputbox.c
+util/kconfig/lxdialog/menubox.c
+util/kconfig/lxdialog/textbox.c
+util/kconfig/lxdialog/util.c
+util/kconfig/lxdialog/yesno.c
+util/kconfig/mconf.c
+util/kconfig/conf.c
+util/kconfig/confdata.c
+util/kconfig/gconf.c
+util/kconfig/gconf.glade.h
+util/kconfig/qconf.cc

Added: trunk/coreboot-v2/util/kconfig/check.sh
===================================================================
--- trunk/coreboot-v2/util/kconfig/check.sh	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/check.sh	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,14 @@
+#!/bin/sh
+# Needed for systems without gettext
+$* -xc -o /dev/null - > /dev/null 2>&1 << EOF
+#include <libintl.h>
+int main()
+{
+	gettext("");
+	return 0;
+}
+EOF
+if [ ! "$?" -eq "0"  ]; then
+	echo -DKBUILD_NO_NLS;
+fi
+

Added: trunk/coreboot-v2/util/kconfig/conf.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/conf.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/conf.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,638 @@
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel at linux-m68k.org>
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#include <locale.h>
+#include <ctype.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include <unistd.h>
+#include <sys/stat.h>
+
+#define LKC_DIRECT_LINK
+#include "lkc.h"
+
+static void conf(struct menu *menu);
+static void check_conf(struct menu *menu);
+
+enum {
+	ask_all,
+	ask_new,
+	ask_silent,
+	set_default,
+	set_yes,
+	set_mod,
+	set_no,
+	set_random
+} input_mode = ask_all;
+char *defconfig_file;
+
+static int indent = 1;
+static int valid_stdin = 1;
+static int conf_cnt;
+static char line[128];
+static struct menu *rootEntry;
+
+static char nohelp_text[] = N_("Sorry, no help available for this option yet.\n");
+
+static const char *get_help(struct menu *menu)
+{
+	if (menu_has_help(menu))
+		return _(menu_get_help(menu));
+	else
+		return nohelp_text;
+}
+
+static void strip(char *str)
+{
+	char *p = str;
+	int l;
+
+	while ((isspace(*p)))
+		p++;
+	l = strlen(p);
+	if (p != str)
+		memmove(str, p, l + 1);
+	if (!l)
+		return;
+	p = str + l - 1;
+	while ((isspace(*p)))
+		*p-- = 0;
+}
+
+static void check_stdin(void)
+{
+	if (!valid_stdin && input_mode == ask_silent) {
+		printf(_("aborted!\n\n"));
+		printf(_("Console input/output is redirected. "));
+		printf(_("Run 'make oldconfig' to update configuration.\n\n"));
+		exit(1);
+	}
+}
+
+static int conf_askvalue(struct symbol *sym, const char *def)
+{
+	enum symbol_type type = sym_get_type(sym);
+	tristate val;
+
+	if (!sym_has_value(sym))
+		printf(_("(NEW) "));
+
+	line[0] = '\n';
+	line[1] = 0;
+
+	if (!sym_is_changable(sym)) {
+		printf("%s\n", def);
+		line[0] = '\n';
+		line[1] = 0;
+		return 0;
+	}
+
+	switch (input_mode) {
+	case set_no:
+	case set_mod:
+	case set_yes:
+	case set_random:
+		if (sym_has_value(sym)) {
+			printf("%s\n", def);
+			return 0;
+		}
+		break;
+	case ask_new:
+	case ask_silent:
+		if (sym_has_value(sym)) {
+			printf("%s\n", def);
+			return 0;
+		}
+		check_stdin();
+	case ask_all:
+		fflush(stdout);
+		fgets(line, 128, stdin);
+		return 1;
+	case set_default:
+		printf("%s\n", def);
+		return 1;
+	default:
+		break;
+	}
+
+	switch (type) {
+	case S_INT:
+	case S_HEX:
+	case S_STRING:
+		printf("%s\n", def);
+		return 1;
+	default:
+		;
+	}
+	switch (input_mode) {
+	case set_yes:
+		if (sym_tristate_within_range(sym, yes)) {
+			line[0] = 'y';
+			line[1] = '\n';
+			line[2] = 0;
+			break;
+		}
+	case set_mod:
+		if (type == S_TRISTATE) {
+			if (sym_tristate_within_range(sym, mod)) {
+				line[0] = 'm';
+				line[1] = '\n';
+				line[2] = 0;
+				break;
+			}
+		} else {
+			if (sym_tristate_within_range(sym, yes)) {
+				line[0] = 'y';
+				line[1] = '\n';
+				line[2] = 0;
+				break;
+			}
+		}
+	case set_no:
+		if (sym_tristate_within_range(sym, no)) {
+			line[0] = 'n';
+			line[1] = '\n';
+			line[2] = 0;
+			break;
+		}
+	case set_random:
+		do {
+			val = (tristate)(rand() % 3);
+		} while (!sym_tristate_within_range(sym, val));
+		switch (val) {
+		case no: line[0] = 'n'; break;
+		case mod: line[0] = 'm'; break;
+		case yes: line[0] = 'y'; break;
+		}
+		line[1] = '\n';
+		line[2] = 0;
+		break;
+	default:
+		break;
+	}
+	printf("%s", line);
+	return 1;
+}
+
+int conf_string(struct menu *menu)
+{
+	struct symbol *sym = menu->sym;
+	const char *def;
+
+	while (1) {
+		printf("%*s%s ", indent - 1, "", _(menu->prompt->text));
+		printf("(%s) ", sym->name);
+		def = sym_get_string_value(sym);
+		if (sym_get_string_value(sym))
+			printf("[%s] ", def);
+		if (!conf_askvalue(sym, def))
+			return 0;
+		switch (line[0]) {
+		case '\n':
+			break;
+		case '?':
+			/* print help */
+			if (line[1] == '\n') {
+				printf("\n%s\n", get_help(menu));
+				def = NULL;
+				break;
+			}
+		default:
+			line[strlen(line)-1] = 0;
+			def = line;
+		}
+		if (def && sym_set_string_value(sym, def))
+			return 0;
+	}
+}
+
+static int conf_sym(struct menu *menu)
+{
+	struct symbol *sym = menu->sym;
+	int type;
+	tristate oldval, newval;
+
+	while (1) {
+		printf("%*s%s ", indent - 1, "", _(menu->prompt->text));
+		if (sym->name)
+			printf("(%s) ", sym->name);
+		type = sym_get_type(sym);
+		putchar('[');
+		oldval = sym_get_tristate_value(sym);
+		switch (oldval) {
+		case no:
+			putchar('N');
+			break;
+		case mod:
+			putchar('M');
+			break;
+		case yes:
+			putchar('Y');
+			break;
+		}
+		if (oldval != no && sym_tristate_within_range(sym, no))
+			printf("/n");
+		if (oldval != mod && sym_tristate_within_range(sym, mod))
+			printf("/m");
+		if (oldval != yes && sym_tristate_within_range(sym, yes))
+			printf("/y");
+		if (menu_has_help(menu))
+			printf("/?");
+		printf("] ");
+		if (!conf_askvalue(sym, sym_get_string_value(sym)))
+			return 0;
+		strip(line);
+
+		switch (line[0]) {
+		case 'n':
+		case 'N':
+			newval = no;
+			if (!line[1] || !strcmp(&line[1], "o"))
+				break;
+			continue;
+		case 'm':
+		case 'M':
+			newval = mod;
+			if (!line[1])
+				break;
+			continue;
+		case 'y':
+		case 'Y':
+			newval = yes;
+			if (!line[1] || !strcmp(&line[1], "es"))
+				break;
+			continue;
+		case 0:
+			newval = oldval;
+			break;
+		case '?':
+			goto help;
+		default:
+			continue;
+		}
+		if (sym_set_tristate_value(sym, newval))
+			return 0;
+help:
+		printf("\n%s\n", get_help(menu));
+	}
+}
+
+static int conf_choice(struct menu *menu)
+{
+	struct symbol *sym, *def_sym;
+	struct menu *child;
+	int type;
+	bool is_new;
+
+	sym = menu->sym;
+	type = sym_get_type(sym);
+	is_new = !sym_has_value(sym);
+	if (sym_is_changable(sym)) {
+		conf_sym(menu);
+		sym_calc_value(sym);
+		switch (sym_get_tristate_value(sym)) {
+		case no:
+			return 1;
+		case mod:
+			return 0;
+		case yes:
+			break;
+		}
+	} else {
+		switch (sym_get_tristate_value(sym)) {
+		case no:
+			return 1;
+		case mod:
+			printf("%*s%s\n", indent - 1, "", _(menu_get_prompt(menu)));
+			return 0;
+		case yes:
+			break;
+		}
+	}
+
+	while (1) {
+		int cnt, def;
+
+		printf("%*s%s\n", indent - 1, "", _(menu_get_prompt(menu)));
+		def_sym = sym_get_choice_value(sym);
+		cnt = def = 0;
+		line[0] = 0;
+		for (child = menu->list; child; child = child->next) {
+			if (!menu_is_visible(child))
+				continue;
+			if (!child->sym) {
+				printf("%*c %s\n", indent, '*', _(menu_get_prompt(child)));
+				continue;
+			}
+			cnt++;
+			if (child->sym == def_sym) {
+				def = cnt;
+				printf("%*c", indent, '>');
+			} else
+				printf("%*c", indent, ' ');
+			printf(" %d. %s", cnt, _(menu_get_prompt(child)));
+			if (child->sym->name)
+				printf(" (%s)", child->sym->name);
+			if (!sym_has_value(child->sym))
+				printf(_(" (NEW)"));
+			printf("\n");
+		}
+		printf(_("%*schoice"), indent - 1, "");
+		if (cnt == 1) {
+			printf("[1]: 1\n");
+			goto conf_childs;
+		}
+		printf("[1-%d", cnt);
+		if (menu_has_help(menu))
+			printf("?");
+		printf("]: ");
+		switch (input_mode) {
+		case ask_new:
+		case ask_silent:
+			if (!is_new) {
+				cnt = def;
+				printf("%d\n", cnt);
+				break;
+			}
+			check_stdin();
+		case ask_all:
+			fflush(stdout);
+			fgets(line, 128, stdin);
+			strip(line);
+			if (line[0] == '?') {
+				printf("\n%s\n", get_help(menu));
+				continue;
+			}
+			if (!line[0])
+				cnt = def;
+			else if (isdigit(line[0]))
+				cnt = atoi(line);
+			else
+				continue;
+			break;
+		case set_random:
+			if (is_new)
+				def = (rand() % cnt) + 1;
+		case set_default:
+		case set_yes:
+		case set_mod:
+		case set_no:
+			cnt = def;
+			printf("%d\n", cnt);
+			break;
+		}
+
+	conf_childs:
+		for (child = menu->list; child; child = child->next) {
+			if (!child->sym || !menu_is_visible(child))
+				continue;
+			if (!--cnt)
+				break;
+		}
+		if (!child)
+			continue;
+		if (line[strlen(line) - 1] == '?') {
+			printf("\n%s\n", get_help(child));
+			continue;
+		}
+		sym_set_choice_value(sym, child->sym);
+		for (child = child->list; child; child = child->next) {
+			indent += 2;
+			conf(child);
+			indent -= 2;
+		}
+		return 1;
+	}
+}
+
+static void conf(struct menu *menu)
+{
+	struct symbol *sym;
+	struct property *prop;
+	struct menu *child;
+
+	if (!menu_is_visible(menu))
+		return;
+
+	sym = menu->sym;
+	prop = menu->prompt;
+	if (prop) {
+		const char *prompt;
+
+		switch (prop->type) {
+		case P_MENU:
+			if (input_mode == ask_silent && rootEntry != menu) {
+				check_conf(menu);
+				return;
+			}
+		case P_COMMENT:
+			prompt = menu_get_prompt(menu);
+			if (prompt)
+				printf("%*c\n%*c %s\n%*c\n",
+					indent, '*',
+					indent, '*', _(prompt),
+					indent, '*');
+		default:
+			;
+		}
+	}
+
+	if (!sym)
+		goto conf_childs;
+
+	if (sym_is_choice(sym)) {
+		conf_choice(menu);
+		if (sym->curr.tri != mod)
+			return;
+		goto conf_childs;
+	}
+
+	switch (sym->type) {
+	case S_INT:
+	case S_HEX:
+	case S_STRING:
+		conf_string(menu);
+		break;
+	default:
+		conf_sym(menu);
+		break;
+	}
+
+conf_childs:
+	if (sym)
+		indent += 2;
+	for (child = menu->list; child; child = child->next)
+		conf(child);
+	if (sym)
+		indent -= 2;
+}
+
+static void check_conf(struct menu *menu)
+{
+	struct symbol *sym;
+	struct menu *child;
+
+	if (!menu_is_visible(menu))
+		return;
+
+	sym = menu->sym;
+	if (sym && !sym_has_value(sym)) {
+		if (sym_is_changable(sym) ||
+		    (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes)) {
+			if (!conf_cnt++)
+				printf(_("*\n* Restart config...\n*\n"));
+			rootEntry = menu_get_parent_menu(menu);
+			conf(rootEntry);
+		}
+	}
+
+	for (child = menu->list; child; child = child->next)
+		check_conf(child);
+}
+
+int main(int ac, char **av)
+{
+	int opt;
+	const char *name;
+	struct stat tmpstat;
+
+	setlocale(LC_ALL, "");
+	bindtextdomain(PACKAGE, LOCALEDIR);
+	textdomain(PACKAGE);
+
+	while ((opt = getopt(ac, av, "osdD:nmyrh")) != -1) {
+		switch (opt) {
+		case 'o':
+			input_mode = ask_new;
+			break;
+		case 's':
+			input_mode = ask_silent;
+			valid_stdin = isatty(0) && isatty(1) && isatty(2);
+			break;
+		case 'd':
+			input_mode = set_default;
+			break;
+		case 'D':
+			input_mode = set_default;
+			defconfig_file = optarg;
+			break;
+		case 'n':
+			input_mode = set_no;
+			break;
+		case 'm':
+			input_mode = set_mod;
+			break;
+		case 'y':
+			input_mode = set_yes;
+			break;
+		case 'r':
+			input_mode = set_random;
+			srand(time(NULL));
+			break;
+		case 'h':
+			printf(_("See README for usage info\n"));
+			exit(0);
+			break;
+		default:
+			fprintf(stderr, _("See README for usage info\n"));
+			exit(1);
+		}
+	}
+	if (ac == optind) {
+		printf(_("%s: Kconfig file missing\n"), av[0]);
+		exit(1);
+	}
+	name = av[optind];
+	conf_parse(name);
+	//zconfdump(stdout);
+	switch (input_mode) {
+	case set_default:
+		if (!defconfig_file)
+			defconfig_file = conf_get_default_confname();
+		if (conf_read(defconfig_file)) {
+			printf(_("***\n"
+				"*** Can't find default configuration \"%s\"!\n"
+				"***\n"), defconfig_file);
+			exit(1);
+		}
+		break;
+	case ask_silent:
+		if (stat(".config", &tmpstat)) {
+			printf(_("***\n"
+				"*** You have not yet configured coreboot!\n"
+				"*** (missing .config file)\n"
+				"***\n"
+				"*** Please run some configurator (e.g. \"make oldconfig\" or\n"
+				"*** \"make menuconfig\" or \"make xconfig\").\n"
+				"***\n"));
+			exit(1);
+		}
+	case ask_all:
+	case ask_new:
+		conf_read(NULL);
+		break;
+	case set_no:
+	case set_mod:
+	case set_yes:
+	case set_random:
+		name = getenv("KCONFIG_ALLCONFIG");
+		if (name && !stat(name, &tmpstat)) {
+			conf_read_simple(name, S_DEF_USER);
+			break;
+		}
+		switch (input_mode) {
+		case set_no:	 name = "allno.config"; break;
+		case set_mod:	 name = "allmod.config"; break;
+		case set_yes:	 name = "allyes.config"; break;
+		case set_random: name = "allrandom.config"; break;
+		default: break;
+		}
+		if (!stat(name, &tmpstat))
+			conf_read_simple(name, S_DEF_USER);
+		else if (!stat("all.config", &tmpstat))
+			conf_read_simple("all.config", S_DEF_USER);
+		break;
+	default:
+		break;
+	}
+
+	if (input_mode != ask_silent) {
+		rootEntry = &rootmenu;
+		conf(&rootmenu);
+		if (input_mode == ask_all) {
+			input_mode = ask_silent;
+			valid_stdin = 1;
+		}
+	} else if (conf_get_changed()) {
+		name = getenv("KCONFIG_NOSILENTUPDATE");
+		if (name && *name) {
+			fprintf(stderr, _("\n*** coreboot configuration requires explicit update.\n\n"));
+			return 1;
+		}
+	} else
+		goto skip_check;
+
+	do {
+		conf_cnt = 0;
+		check_conf(&rootmenu);
+	} while (conf_cnt);
+	if (conf_write(NULL)) {
+		fprintf(stderr, _("\n*** Error during writing of the configuration.\n\n"));
+		return 1;
+	}
+	if (conf_write_autoconf()) {
+		fprintf(stderr, _("\n*** Error during writing of the configuration.\n\n"));
+		return 1;
+	}
+skip_check:
+	if (input_mode == ask_silent && conf_write_autoconf()) {
+		fprintf(stderr, _("\n*** Error during writing of the configuration.\n\n"));
+		return 1;
+	}
+
+	return 0;
+}

Added: trunk/coreboot-v2/util/kconfig/confdata.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/confdata.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/confdata.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,818 @@
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel at linux-m68k.org>
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#include <sys/stat.h>
+#include <ctype.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+#include <unistd.h>
+
+#define LKC_DIRECT_LINK
+#include "lkc.h"
+
+static void conf_warning(const char *fmt, ...)
+	__attribute__ ((format (printf, 1, 2)));
+
+static const char *conf_filename;
+static int conf_lineno, conf_warnings, conf_unsaved;
+
+const char conf_defname[] = "arch/$ARCH/defconfig";
+
+static void conf_warning(const char *fmt, ...)
+{
+	va_list ap;
+	va_start(ap, fmt);
+	fprintf(stderr, "%s:%d:warning: ", conf_filename, conf_lineno);
+	vfprintf(stderr, fmt, ap);
+	fprintf(stderr, "\n");
+	va_end(ap);
+	conf_warnings++;
+}
+
+const char *conf_get_configname(void)
+{
+	char *name = getenv("KCONFIG_CONFIG");
+
+	return name ? name : ".config";
+}
+
+static char *conf_expand_value(const char *in)
+{
+	struct symbol *sym;
+	const char *src;
+	static char res_value[SYMBOL_MAXLENGTH];
+	char *dst, name[SYMBOL_MAXLENGTH];
+
+	res_value[0] = 0;
+	dst = name;
+	while ((src = strchr(in, '$'))) {
+		strncat(res_value, in, src - in);
+		src++;
+		dst = name;
+		while (isalnum(*src) || *src == '_')
+			*dst++ = *src++;
+		*dst = 0;
+		sym = sym_lookup(name, 0);
+		sym_calc_value(sym);
+		strcat(res_value, sym_get_string_value(sym));
+		in = src;
+	}
+	strcat(res_value, in);
+
+	return res_value;
+}
+
+char *conf_get_default_confname(void)
+{
+	struct stat buf;
+	static char fullname[PATH_MAX+1];
+	char *env, *name;
+
+	name = conf_expand_value(conf_defname);
+	env = getenv(SRCTREE);
+	if (env) {
+		sprintf(fullname, "%s/%s", env, name);
+		if (!stat(fullname, &buf))
+			return fullname;
+	}
+	return name;
+}
+
+static int conf_set_sym_val(struct symbol *sym, int def, int def_flags, char *p)
+{
+	char *p2;
+
+	switch (sym->type) {
+	case S_TRISTATE:
+		if (p[0] == 'm') {
+			sym->def[def].tri = mod;
+			sym->flags |= def_flags;
+			break;
+		}
+	case S_BOOLEAN:
+		if (p[0] == 'y') {
+			sym->def[def].tri = yes;
+			sym->flags |= def_flags;
+			break;
+		}
+		if (p[0] == 'n') {
+			sym->def[def].tri = no;
+			sym->flags |= def_flags;
+			break;
+		}
+		conf_warning("symbol value '%s' invalid for %s", p, sym->name);
+		break;
+	case S_OTHER:
+		if (*p != '"') {
+			for (p2 = p; *p2 && !isspace(*p2); p2++)
+				;
+			sym->type = S_STRING;
+			goto done;
+		}
+	case S_STRING:
+		if (*p++ != '"')
+			break;
+		for (p2 = p; (p2 = strpbrk(p2, "\"\\")); p2++) {
+			if (*p2 == '"') {
+				*p2 = 0;
+				break;
+			}
+			memmove(p2, p2 + 1, strlen(p2));
+		}
+		if (!p2) {
+			conf_warning("invalid string found");
+			return 1;
+		}
+	case S_INT:
+	case S_HEX:
+	done:
+		if (sym_string_valid(sym, p)) {
+			sym->def[def].val = strdup(p);
+			sym->flags |= def_flags;
+		} else {
+			conf_warning("symbol value '%s' invalid for %s", p, sym->name);
+			return 1;
+		}
+		break;
+	default:
+		;
+	}
+	return 0;
+}
+
+int conf_read_simple(const char *name, int def)
+{
+	FILE *in = NULL;
+	char line[1024];
+	char *p, *p2;
+	struct symbol *sym;
+	int i, def_flags;
+
+	if (name) {
+		in = zconf_fopen(name);
+	} else {
+		struct property *prop;
+
+		name = conf_get_configname();
+		in = zconf_fopen(name);
+		if (in)
+			goto load;
+		sym_add_change_count(1);
+		if (!sym_defconfig_list)
+			return 1;
+
+		for_all_defaults(sym_defconfig_list, prop) {
+			if (expr_calc_value(prop->visible.expr) == no ||
+			    prop->expr->type != E_SYMBOL)
+				continue;
+			name = conf_expand_value(prop->expr->left.sym->name);
+			in = zconf_fopen(name);
+			if (in) {
+				printf(_("#\n"
+					 "# using defaults found in %s\n"
+					 "#\n"), name);
+				goto load;
+			}
+		}
+	}
+	if (!in)
+		return 1;
+
+load:
+	conf_filename = name;
+	conf_lineno = 0;
+	conf_warnings = 0;
+	conf_unsaved = 0;
+
+	def_flags = SYMBOL_DEF << def;
+	for_all_symbols(i, sym) {
+		sym->flags |= SYMBOL_CHANGED;
+		sym->flags &= ~(def_flags|SYMBOL_VALID);
+		if (sym_is_choice(sym))
+			sym->flags |= def_flags;
+		switch (sym->type) {
+		case S_INT:
+		case S_HEX:
+		case S_STRING:
+			if (sym->def[def].val)
+				free(sym->def[def].val);
+		default:
+			sym->def[def].val = NULL;
+			sym->def[def].tri = no;
+		}
+	}
+
+	while (fgets(line, sizeof(line), in)) {
+		conf_lineno++;
+		sym = NULL;
+		switch (line[0]) {
+		case '#':
+			if (memcmp(line + 2, "CONFIG_", 7))
+				continue;
+			p = strchr(line + 9, ' ');
+			if (!p)
+				continue;
+			*p++ = 0;
+			if (strncmp(p, "is not set", 10))
+				continue;
+			if (def == S_DEF_USER) {
+				sym = sym_find(line + 9);
+				if (!sym) {
+					conf_warning("trying to assign nonexistent symbol %s", line + 9);
+					break;
+				}
+			} else {
+				sym = sym_lookup(line + 9, 0);
+				if (sym->type == S_UNKNOWN)
+					sym->type = S_BOOLEAN;
+			}
+			if (sym->flags & def_flags) {
+				conf_warning("override: reassigning to symbol %s", sym->name);
+			}
+			switch (sym->type) {
+			case S_BOOLEAN:
+			case S_TRISTATE:
+				sym->def[def].tri = no;
+				sym->flags |= def_flags;
+				break;
+			default:
+				;
+			}
+			break;
+		case 'C':
+			if (memcmp(line, "CONFIG_", 7)) {
+				conf_warning("unexpected data");
+				continue;
+			}
+			p = strchr(line + 7, '=');
+			if (!p)
+				continue;
+			*p++ = 0;
+			p2 = strchr(p, '\n');
+			if (p2) {
+				*p2-- = 0;
+				if (*p2 == '\r')
+					*p2 = 0;
+			}
+			if (def == S_DEF_USER) {
+				sym = sym_find(line + 7);
+				if (!sym) {
+					conf_warning("trying to assign nonexistent symbol %s", line + 7);
+					break;
+				}
+			} else {
+				sym = sym_lookup(line + 7, 0);
+				if (sym->type == S_UNKNOWN)
+					sym->type = S_OTHER;
+			}
+			if (sym->flags & def_flags) {
+				conf_warning("override: reassigning to symbol %s", sym->name);
+			}
+			if (conf_set_sym_val(sym, def, def_flags, p))
+				continue;
+			break;
+		case '\r':
+		case '\n':
+			break;
+		default:
+			conf_warning("unexpected data");
+			continue;
+		}
+		if (sym && sym_is_choice_value(sym)) {
+			struct symbol *cs = prop_get_symbol(sym_get_choice_prop(sym));
+			switch (sym->def[def].tri) {
+			case no:
+				break;
+			case mod:
+				if (cs->def[def].tri == yes) {
+					conf_warning("%s creates inconsistent choice state", sym->name);
+					cs->flags &= ~def_flags;
+				}
+				break;
+			case yes:
+				if (cs->def[def].tri != no)
+					conf_warning("override: %s changes choice state", sym->name);
+				cs->def[def].val = sym;
+				break;
+			}
+			cs->def[def].tri = EXPR_OR(cs->def[def].tri, sym->def[def].tri);
+		}
+	}
+	fclose(in);
+
+	if (modules_sym)
+		sym_calc_value(modules_sym);
+	return 0;
+}
+
+int conf_read(const char *name)
+{
+	struct symbol *sym, *choice_sym;
+	struct property *prop;
+	struct expr *e;
+	int i, flags;
+
+	sym_set_change_count(0);
+
+	if (conf_read_simple(name, S_DEF_USER))
+		return 1;
+
+	for_all_symbols(i, sym) {
+		sym_calc_value(sym);
+		if (sym_is_choice(sym) || (sym->flags & SYMBOL_AUTO))
+			goto sym_ok;
+		if (sym_has_value(sym) && (sym->flags & SYMBOL_WRITE)) {
+			/* check that calculated value agrees with saved value */
+			switch (sym->type) {
+			case S_BOOLEAN:
+			case S_TRISTATE:
+				if (sym->def[S_DEF_USER].tri != sym_get_tristate_value(sym))
+					break;
+				if (!sym_is_choice(sym))
+					goto sym_ok;
+			default:
+				if (!strcmp(sym->curr.val, sym->def[S_DEF_USER].val))
+					goto sym_ok;
+				break;
+			}
+		} else if (!sym_has_value(sym) && !(sym->flags & SYMBOL_WRITE))
+			/* no previous value and not saved */
+			goto sym_ok;
+		conf_unsaved++;
+		/* maybe print value in verbose mode... */
+	sym_ok:
+		if (!sym_is_choice(sym))
+			continue;
+		/* The choice symbol only has a set value (and thus is not new)
+		 * if all its visible childs have values.
+		 */
+		prop = sym_get_choice_prop(sym);
+		flags = sym->flags;
+		expr_list_for_each_sym(prop->expr, e, choice_sym)
+			if (choice_sym->visible != no)
+				flags &= choice_sym->flags;
+		sym->flags &= flags | ~SYMBOL_DEF_USER;
+	}
+
+	for_all_symbols(i, sym) {
+		if (sym_has_value(sym) && !sym_is_choice_value(sym)) {
+			/* Reset values of generates values, so they'll appear
+			 * as new, if they should become visible, but that
+			 * doesn't quite work if the Kconfig and the saved
+			 * configuration disagree.
+			 */
+			if (sym->visible == no && !conf_unsaved)
+				sym->flags &= ~SYMBOL_DEF_USER;
+			switch (sym->type) {
+			case S_STRING:
+			case S_INT:
+			case S_HEX:
+				/* Reset a string value if it's out of range */
+				if (sym_string_within_range(sym, sym->def[S_DEF_USER].val))
+					break;
+				sym->flags &= ~(SYMBOL_VALID|SYMBOL_DEF_USER);
+				conf_unsaved++;
+				break;
+			default:
+				break;
+			}
+		}
+	}
+
+	sym_add_change_count(conf_warnings || conf_unsaved);
+
+	return 0;
+}
+
+int conf_write(const char *name)
+{
+	FILE *out;
+	struct symbol *sym;
+	struct menu *menu;
+	const char *basename;
+	char dirname[128], tmpname[128], newname[128];
+	int type, l;
+	const char *str;
+	time_t now;
+	int use_timestamp = 1;
+	char *env;
+
+	dirname[0] = 0;
+	if (name && name[0]) {
+		struct stat st;
+		char *slash;
+
+		if (!stat(name, &st) && S_ISDIR(st.st_mode)) {
+			strcpy(dirname, name);
+			strcat(dirname, "/");
+			basename = conf_get_configname();
+		} else if ((slash = strrchr(name, '/'))) {
+			int size = slash - name + 1;
+			memcpy(dirname, name, size);
+			dirname[size] = 0;
+			if (slash[1])
+				basename = slash + 1;
+			else
+				basename = conf_get_configname();
+		} else
+			basename = name;
+	} else
+		basename = conf_get_configname();
+
+	sprintf(newname, "%s%s", dirname, basename);
+	env = getenv("KCONFIG_OVERWRITECONFIG");
+	if (!env || !*env) {
+		sprintf(tmpname, "%s.tmpconfig.%d", dirname, (int)getpid());
+		out = fopen(tmpname, "w");
+	} else {
+		*tmpname = 0;
+		out = fopen(newname, "w");
+	}
+	if (!out)
+		return 1;
+
+	sym = sym_lookup("KERNELVERSION", 0);
+	sym_calc_value(sym);
+	time(&now);
+	env = getenv("KCONFIG_NOTIMESTAMP");
+	if (env && *env)
+		use_timestamp = 0;
+
+	fprintf(out, _("#\n"
+		       "# Automatically generated make config: don't edit\n"
+		       "# coreboot version: %s\n"
+		       "%s%s"
+		       "#\n"),
+		     getenv("KERNELVERSION")?getenv("KERNELVERSION"):"",
+		     use_timestamp ? "# " : "",
+		     use_timestamp ? ctime(&now) : "");
+
+	if (!conf_get_changed())
+		sym_clear_all_valid();
+
+	menu = rootmenu.list;
+	while (menu) {
+		sym = menu->sym;
+		if (!sym) {
+			if (!menu_is_visible(menu))
+				goto next;
+			str = menu_get_prompt(menu);
+			fprintf(out, "\n"
+				     "#\n"
+				     "# %s\n"
+				     "#\n", str);
+		} else if (!(sym->flags & SYMBOL_CHOICE)) {
+			sym_calc_value(sym);
+			if (!(sym->flags & SYMBOL_WRITE))
+				goto next;
+			sym->flags &= ~SYMBOL_WRITE;
+			type = sym->type;
+			if (type == S_TRISTATE) {
+				sym_calc_value(modules_sym);
+				if (modules_sym->curr.tri == no)
+					type = S_BOOLEAN;
+			}
+			switch (type) {
+			case S_BOOLEAN:
+			case S_TRISTATE:
+				switch (sym_get_tristate_value(sym)) {
+				case no:
+					fprintf(out, "# CONFIG_%s is not set\n", sym->name);
+					break;
+				case mod:
+					fprintf(out, "CONFIG_%s=m\n", sym->name);
+					break;
+				case yes:
+					fprintf(out, "CONFIG_%s=y\n", sym->name);
+					break;
+				}
+				break;
+			case S_STRING:
+				str = sym_get_string_value(sym);
+				fprintf(out, "CONFIG_%s=\"", sym->name);
+				while (1) {
+					l = strcspn(str, "\"\\");
+					if (l) {
+						fwrite(str, l, 1, out);
+						str += l;
+					}
+					if (!*str)
+						break;
+					fprintf(out, "\\%c", *str++);
+				}
+				fputs("\"\n", out);
+				break;
+			case S_HEX:
+				str = sym_get_string_value(sym);
+				if (str[0] != '0' || (str[1] != 'x' && str[1] != 'X')) {
+					fprintf(out, "CONFIG_%s=%s\n", sym->name, str);
+					break;
+				}
+			case S_INT:
+				str = sym_get_string_value(sym);
+				fprintf(out, "CONFIG_%s=%s\n", sym->name, str);
+				break;
+			}
+		}
+
+	next:
+		if (menu->list) {
+			menu = menu->list;
+			continue;
+		}
+		if (menu->next)
+			menu = menu->next;
+		else while ((menu = menu->parent)) {
+			if (menu->next) {
+				menu = menu->next;
+				break;
+			}
+		}
+	}
+	fclose(out);
+
+	if (*tmpname) {
+		strcat(dirname, basename);
+		strcat(dirname, ".old");
+		rename(newname, dirname);
+		if (rename(tmpname, newname))
+			return 1;
+	}
+
+	printf(_("#\n"
+		 "# configuration written to %s\n"
+		 "#\n"), newname);
+
+	sym_set_change_count(0);
+
+	return 0;
+}
+
+int conf_split_config(void)
+{
+	char *name, path[128];
+	char *s, *d, c;
+	struct symbol *sym;
+	struct stat sb;
+	int res, i, fd;
+
+	name = getenv("KCONFIG_AUTOCONFIG");
+	if (!name)
+		name = "include/config/auto.conf";
+	conf_read_simple(name, S_DEF_AUTO);
+
+	if (chdir("build"))
+		return 1;
+
+	res = 0;
+	for_all_symbols(i, sym) {
+		sym_calc_value(sym);
+		if ((sym->flags & SYMBOL_AUTO) || !sym->name)
+			continue;
+		if (sym->flags & SYMBOL_WRITE) {
+			if (sym->flags & SYMBOL_DEF_AUTO) {
+				/*
+				 * symbol has old and new value,
+				 * so compare them...
+				 */
+				switch (sym->type) {
+				case S_BOOLEAN:
+				case S_TRISTATE:
+					if (sym_get_tristate_value(sym) ==
+					    sym->def[S_DEF_AUTO].tri)
+						continue;
+					break;
+				case S_STRING:
+				case S_HEX:
+				case S_INT:
+					if (!strcmp(sym_get_string_value(sym),
+						    sym->def[S_DEF_AUTO].val))
+						continue;
+					break;
+				default:
+					break;
+				}
+			} else {
+				/*
+				 * If there is no old value, only 'no' (unset)
+				 * is allowed as new value.
+				 */
+				switch (sym->type) {
+				case S_BOOLEAN:
+				case S_TRISTATE:
+					if (sym_get_tristate_value(sym) == no)
+						continue;
+					break;
+				default:
+					break;
+				}
+			}
+		} else if (!(sym->flags & SYMBOL_DEF_AUTO))
+			/* There is neither an old nor a new value. */
+			continue;
+		/* else
+		 *	There is an old value, but no new value ('no' (unset)
+		 *	isn't saved in auto.conf, so the old value is always
+		 *	different from 'no').
+		 */
+
+		/* Replace all '_' and append ".h" */
+		s = sym->name;
+		d = path;
+		while ((c = *s++)) {
+			c = tolower(c);
+			*d++ = (c == '_') ? '/' : c;
+		}
+		strcpy(d, ".h");
+
+		/* Assume directory path already exists. */
+		fd = open(path, O_WRONLY | O_CREAT | O_TRUNC, 0644);
+		if (fd == -1) {
+			if (errno != ENOENT) {
+				res = 1;
+				break;
+			}
+			/*
+			 * Create directory components,
+			 * unless they exist already.
+			 */
+			d = path;
+			while ((d = strchr(d, '/'))) {
+				*d = 0;
+				if (stat(path, &sb) && mkdir(path, 0755)) {
+					res = 1;
+					goto out;
+				}
+				*d++ = '/';
+			}
+			/* Try it again. */
+			fd = open(path, O_WRONLY | O_CREAT | O_TRUNC, 0644);
+			if (fd == -1) {
+				res = 1;
+				break;
+			}
+		}
+		close(fd);
+	}
+out:
+	if (chdir("../.."))
+		return 1;
+
+	return res;
+}
+
+int conf_write_autoconf(void)
+{
+	struct symbol *sym;
+	const char *str;
+	char *name;
+	FILE *out, *out_h;
+	time_t now;
+	int i, l;
+
+	sym_clear_all_valid();
+
+	file_write_dep("build/auto.conf.cmd");
+
+#if 0
+	if (conf_split_config())
+		return 1;
+#endif
+
+	out = fopen(".tmpconfig", "w");
+	if (!out)
+		return 1;
+
+	out_h = fopen(".tmpconfig.h", "w");
+	if (!out_h) {
+		fclose(out);
+		return 1;
+	}
+
+	sym = sym_lookup("KERNELVERSION", 0);
+	sym_calc_value(sym);
+	time(&now);
+	fprintf(out, "#\n"
+		     "# Automatically generated make config: don't edit\n"
+		     "# coreboot version: %s\n"
+		     "# %s"
+		     "#\n",
+		     getenv("KERNELVERSION")?getenv("KERNELVERSION"):"", ctime(&now));
+	fprintf(out_h, "/*\n"
+		       " * Automatically generated C config: don't edit\n"
+		       " * coreboot version: %s\n"
+		       " * %s"
+		       " */\n"
+		       "#define AUTOCONF_INCLUDED\n",
+		       getenv("KERNELVERSION")?getenv("KERNELVERSION"):"", ctime(&now));
+
+	for_all_symbols(i, sym) {
+		sym_calc_value(sym);
+		if (!(sym->flags & SYMBOL_WRITE) || !sym->name)
+			continue;
+		switch (sym->type) {
+		case S_BOOLEAN:
+		case S_TRISTATE:
+			switch (sym_get_tristate_value(sym)) {
+			case no:
+				fprintf(out, "CONFIG_%s=n\n", sym->name);
+				fprintf(out_h, "#define CONFIG_%s 0\n", sym->name);
+				break;
+			case mod:
+				fprintf(out, "CONFIG_%s=m\n", sym->name);
+				fprintf(out_h, "#define CONFIG_%s_MODULE 1\n", sym->name);
+				break;
+			case yes:
+				fprintf(out, "CONFIG_%s=y\n", sym->name);
+				fprintf(out_h, "#define CONFIG_%s 1\n", sym->name);
+				break;
+			}
+			break;
+		case S_STRING:
+			str = sym_get_string_value(sym);
+			fprintf(out, "CONFIG_%s=\"", sym->name);
+			fprintf(out_h, "#define CONFIG_%s \"", sym->name);
+			while (1) {
+				l = strcspn(str, "\"\\");
+				if (l) {
+					fwrite(str, l, 1, out);
+					fwrite(str, l, 1, out_h);
+					str += l;
+				}
+				if (!*str)
+					break;
+				fprintf(out, "\\%c", *str);
+				fprintf(out_h, "\\%c", *str);
+				str++;
+			}
+			fputs("\"\n", out);
+			fputs("\"\n", out_h);
+			break;
+		case S_HEX:
+			str = sym_get_string_value(sym);
+			if (str[0] != '0' || (str[1] != 'x' && str[1] != 'X')) {
+				fprintf(out, "CONFIG_%s=%s\n", sym->name, str);
+				fprintf(out_h, "#define CONFIG_%s 0x%s\n", sym->name, str);
+				break;
+			}
+		case S_INT:
+			str = sym_get_string_value(sym);
+			fprintf(out, "CONFIG_%s=%s\n", sym->name, str);
+			fprintf(out_h, "#define CONFIG_%s %s\n", sym->name, str);
+			break;
+		default:
+			break;
+		}
+	}
+	fclose(out);
+	fclose(out_h);
+
+	name = getenv("KCONFIG_AUTOHEADER");
+	if (!name)
+		name = "include/linux/autoconf.h";
+	if (rename(".tmpconfig.h", name))
+		return 1;
+	name = getenv("KCONFIG_AUTOCONFIG");
+	if (!name)
+		name = "include/config/auto.conf";
+	/*
+	 * This must be the last step, kbuild has a dependency on auto.conf
+	 * and this marks the successful completion of the previous steps.
+	 */
+	if (rename(".tmpconfig", name))
+		return 1;
+
+	return 0;
+}
+
+static int sym_change_count;
+static void (*conf_changed_callback)(void);
+
+void sym_set_change_count(int count)
+{
+	int _sym_change_count = sym_change_count;
+	sym_change_count = count;
+	if (conf_changed_callback &&
+	    (bool)_sym_change_count != (bool)count)
+		conf_changed_callback();
+}
+
+void sym_add_change_count(int count)
+{
+	sym_set_change_count(count + sym_change_count);
+}
+
+bool conf_get_changed(void)
+{
+	return sym_change_count;
+}
+
+void conf_set_changed_callback(void (*fn)(void))
+{
+	conf_changed_callback = fn;
+}

Added: trunk/coreboot-v2/util/kconfig/expr.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/expr.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/expr.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,1106 @@
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel at linux-m68k.org>
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#define LKC_DIRECT_LINK
+#include "lkc.h"
+
+#define DEBUG_EXPR	0
+
+struct expr *expr_alloc_symbol(struct symbol *sym)
+{
+	struct expr *e = malloc(sizeof(*e));
+	memset(e, 0, sizeof(*e));
+	e->type = E_SYMBOL;
+	e->left.sym = sym;
+	return e;
+}
+
+struct expr *expr_alloc_one(enum expr_type type, struct expr *ce)
+{
+	struct expr *e = malloc(sizeof(*e));
+	memset(e, 0, sizeof(*e));
+	e->type = type;
+	e->left.expr = ce;
+	return e;
+}
+
+struct expr *expr_alloc_two(enum expr_type type, struct expr *e1, struct expr *e2)
+{
+	struct expr *e = malloc(sizeof(*e));
+	memset(e, 0, sizeof(*e));
+	e->type = type;
+	e->left.expr = e1;
+	e->right.expr = e2;
+	return e;
+}
+
+struct expr *expr_alloc_comp(enum expr_type type, struct symbol *s1, struct symbol *s2)
+{
+	struct expr *e = malloc(sizeof(*e));
+	memset(e, 0, sizeof(*e));
+	e->type = type;
+	e->left.sym = s1;
+	e->right.sym = s2;
+	return e;
+}
+
+struct expr *expr_alloc_and(struct expr *e1, struct expr *e2)
+{
+	if (!e1)
+		return e2;
+	return e2 ? expr_alloc_two(E_AND, e1, e2) : e1;
+}
+
+struct expr *expr_alloc_or(struct expr *e1, struct expr *e2)
+{
+	if (!e1)
+		return e2;
+	return e2 ? expr_alloc_two(E_OR, e1, e2) : e1;
+}
+
+struct expr *expr_copy(struct expr *org)
+{
+	struct expr *e;
+
+	if (!org)
+		return NULL;
+
+	e = malloc(sizeof(*org));
+	memcpy(e, org, sizeof(*org));
+	switch (org->type) {
+	case E_SYMBOL:
+		e->left = org->left;
+		break;
+	case E_NOT:
+		e->left.expr = expr_copy(org->left.expr);
+		break;
+	case E_EQUAL:
+	case E_UNEQUAL:
+		e->left.sym = org->left.sym;
+		e->right.sym = org->right.sym;
+		break;
+	case E_AND:
+	case E_OR:
+	case E_LIST:
+		e->left.expr = expr_copy(org->left.expr);
+		e->right.expr = expr_copy(org->right.expr);
+		break;
+	default:
+		printf("can't copy type %d\n", e->type);
+		free(e);
+		e = NULL;
+		break;
+	}
+
+	return e;
+}
+
+void expr_free(struct expr *e)
+{
+	if (!e)
+		return;
+
+	switch (e->type) {
+	case E_SYMBOL:
+		break;
+	case E_NOT:
+		expr_free(e->left.expr);
+		return;
+	case E_EQUAL:
+	case E_UNEQUAL:
+		break;
+	case E_OR:
+	case E_AND:
+		expr_free(e->left.expr);
+		expr_free(e->right.expr);
+		break;
+	default:
+		printf("how to free type %d?\n", e->type);
+		break;
+	}
+	free(e);
+}
+
+static int trans_count;
+
+#define e1 (*ep1)
+#define e2 (*ep2)
+
+static void __expr_eliminate_eq(enum expr_type type, struct expr **ep1, struct expr **ep2)
+{
+	if (e1->type == type) {
+		__expr_eliminate_eq(type, &e1->left.expr, &e2);
+		__expr_eliminate_eq(type, &e1->right.expr, &e2);
+		return;
+	}
+	if (e2->type == type) {
+		__expr_eliminate_eq(type, &e1, &e2->left.expr);
+		__expr_eliminate_eq(type, &e1, &e2->right.expr);
+		return;
+	}
+	if (e1->type == E_SYMBOL && e2->type == E_SYMBOL &&
+	    e1->left.sym == e2->left.sym &&
+	    (e1->left.sym == &symbol_yes || e1->left.sym == &symbol_no))
+		return;
+	if (!expr_eq(e1, e2))
+		return;
+	trans_count++;
+	expr_free(e1); expr_free(e2);
+	switch (type) {
+	case E_OR:
+		e1 = expr_alloc_symbol(&symbol_no);
+		e2 = expr_alloc_symbol(&symbol_no);
+		break;
+	case E_AND:
+		e1 = expr_alloc_symbol(&symbol_yes);
+		e2 = expr_alloc_symbol(&symbol_yes);
+		break;
+	default:
+		;
+	}
+}
+
+void expr_eliminate_eq(struct expr **ep1, struct expr **ep2)
+{
+	if (!e1 || !e2)
+		return;
+	switch (e1->type) {
+	case E_OR:
+	case E_AND:
+		__expr_eliminate_eq(e1->type, ep1, ep2);
+	default:
+		;
+	}
+	if (e1->type != e2->type) switch (e2->type) {
+	case E_OR:
+	case E_AND:
+		__expr_eliminate_eq(e2->type, ep1, ep2);
+	default:
+		;
+	}
+	e1 = expr_eliminate_yn(e1);
+	e2 = expr_eliminate_yn(e2);
+}
+
+#undef e1
+#undef e2
+
+int expr_eq(struct expr *e1, struct expr *e2)
+{
+	int res, old_count;
+
+	if (e1->type != e2->type)
+		return 0;
+	switch (e1->type) {
+	case E_EQUAL:
+	case E_UNEQUAL:
+		return e1->left.sym == e2->left.sym && e1->right.sym == e2->right.sym;
+	case E_SYMBOL:
+		return e1->left.sym == e2->left.sym;
+	case E_NOT:
+		return expr_eq(e1->left.expr, e2->left.expr);
+	case E_AND:
+	case E_OR:
+		e1 = expr_copy(e1);
+		e2 = expr_copy(e2);
+		old_count = trans_count;
+		expr_eliminate_eq(&e1, &e2);
+		res = (e1->type == E_SYMBOL && e2->type == E_SYMBOL &&
+		       e1->left.sym == e2->left.sym);
+		expr_free(e1);
+		expr_free(e2);
+		trans_count = old_count;
+		return res;
+	case E_LIST:
+	case E_RANGE:
+	case E_NONE:
+		/* panic */;
+	}
+
+	if (DEBUG_EXPR) {
+		expr_fprint(e1, stdout);
+		printf(" = ");
+		expr_fprint(e2, stdout);
+		printf(" ?\n");
+	}
+
+	return 0;
+}
+
+struct expr *expr_eliminate_yn(struct expr *e)
+{
+	struct expr *tmp;
+
+	if (e) switch (e->type) {
+	case E_AND:
+		e->left.expr = expr_eliminate_yn(e->left.expr);
+		e->right.expr = expr_eliminate_yn(e->right.expr);
+		if (e->left.expr->type == E_SYMBOL) {
+			if (e->left.expr->left.sym == &symbol_no) {
+				expr_free(e->left.expr);
+				expr_free(e->right.expr);
+				e->type = E_SYMBOL;
+				e->left.sym = &symbol_no;
+				e->right.expr = NULL;
+				return e;
+			} else if (e->left.expr->left.sym == &symbol_yes) {
+				free(e->left.expr);
+				tmp = e->right.expr;
+				*e = *(e->right.expr);
+				free(tmp);
+				return e;
+			}
+		}
+		if (e->right.expr->type == E_SYMBOL) {
+			if (e->right.expr->left.sym == &symbol_no) {
+				expr_free(e->left.expr);
+				expr_free(e->right.expr);
+				e->type = E_SYMBOL;
+				e->left.sym = &symbol_no;
+				e->right.expr = NULL;
+				return e;
+			} else if (e->right.expr->left.sym == &symbol_yes) {
+				free(e->right.expr);
+				tmp = e->left.expr;
+				*e = *(e->left.expr);
+				free(tmp);
+				return e;
+			}
+		}
+		break;
+	case E_OR:
+		e->left.expr = expr_eliminate_yn(e->left.expr);
+		e->right.expr = expr_eliminate_yn(e->right.expr);
+		if (e->left.expr->type == E_SYMBOL) {
+			if (e->left.expr->left.sym == &symbol_no) {
+				free(e->left.expr);
+				tmp = e->right.expr;
+				*e = *(e->right.expr);
+				free(tmp);
+				return e;
+			} else if (e->left.expr->left.sym == &symbol_yes) {
+				expr_free(e->left.expr);
+				expr_free(e->right.expr);
+				e->type = E_SYMBOL;
+				e->left.sym = &symbol_yes;
+				e->right.expr = NULL;
+				return e;
+			}
+		}
+		if (e->right.expr->type == E_SYMBOL) {
+			if (e->right.expr->left.sym == &symbol_no) {
+				free(e->right.expr);
+				tmp = e->left.expr;
+				*e = *(e->left.expr);
+				free(tmp);
+				return e;
+			} else if (e->right.expr->left.sym == &symbol_yes) {
+				expr_free(e->left.expr);
+				expr_free(e->right.expr);
+				e->type = E_SYMBOL;
+				e->left.sym = &symbol_yes;
+				e->right.expr = NULL;
+				return e;
+			}
+		}
+		break;
+	default:
+		;
+	}
+	return e;
+}
+
+/*
+ * bool FOO!=n => FOO
+ */
+struct expr *expr_trans_bool(struct expr *e)
+{
+	if (!e)
+		return NULL;
+	switch (e->type) {
+	case E_AND:
+	case E_OR:
+	case E_NOT:
+		e->left.expr = expr_trans_bool(e->left.expr);
+		e->right.expr = expr_trans_bool(e->right.expr);
+		break;
+	case E_UNEQUAL:
+		// FOO!=n -> FOO
+		if (e->left.sym->type == S_TRISTATE) {
+			if (e->right.sym == &symbol_no) {
+				e->type = E_SYMBOL;
+				e->right.sym = NULL;
+			}
+		}
+		break;
+	default:
+		;
+	}
+	return e;
+}
+
+/*
+ * e1 || e2 -> ?
+ */
+struct expr *expr_join_or(struct expr *e1, struct expr *e2)
+{
+	struct expr *tmp;
+	struct symbol *sym1, *sym2;
+
+	if (expr_eq(e1, e2))
+		return expr_copy(e1);
+	if (e1->type != E_EQUAL && e1->type != E_UNEQUAL && e1->type != E_SYMBOL && e1->type != E_NOT)
+		return NULL;
+	if (e2->type != E_EQUAL && e2->type != E_UNEQUAL && e2->type != E_SYMBOL && e2->type != E_NOT)
+		return NULL;
+	if (e1->type == E_NOT) {
+		tmp = e1->left.expr;
+		if (tmp->type != E_EQUAL && tmp->type != E_UNEQUAL && tmp->type != E_SYMBOL)
+			return NULL;
+		sym1 = tmp->left.sym;
+	} else
+		sym1 = e1->left.sym;
+	if (e2->type == E_NOT) {
+		if (e2->left.expr->type != E_SYMBOL)
+			return NULL;
+		sym2 = e2->left.expr->left.sym;
+	} else
+		sym2 = e2->left.sym;
+	if (sym1 != sym2)
+		return NULL;
+	if (sym1->type != S_BOOLEAN && sym1->type != S_TRISTATE)
+		return NULL;
+	if (sym1->type == S_TRISTATE) {
+		if (e1->type == E_EQUAL && e2->type == E_EQUAL &&
+		    ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_mod) ||
+		     (e1->right.sym == &symbol_mod && e2->right.sym == &symbol_yes))) {
+			// (a='y') || (a='m') -> (a!='n')
+			return expr_alloc_comp(E_UNEQUAL, sym1, &symbol_no);
+		}
+		if (e1->type == E_EQUAL && e2->type == E_EQUAL &&
+		    ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_no) ||
+		     (e1->right.sym == &symbol_no && e2->right.sym == &symbol_yes))) {
+			// (a='y') || (a='n') -> (a!='m')
+			return expr_alloc_comp(E_UNEQUAL, sym1, &symbol_mod);
+		}
+		if (e1->type == E_EQUAL && e2->type == E_EQUAL &&
+		    ((e1->right.sym == &symbol_mod && e2->right.sym == &symbol_no) ||
+		     (e1->right.sym == &symbol_no && e2->right.sym == &symbol_mod))) {
+			// (a='m') || (a='n') -> (a!='y')
+			return expr_alloc_comp(E_UNEQUAL, sym1, &symbol_yes);
+		}
+	}
+	if (sym1->type == S_BOOLEAN && sym1 == sym2) {
+		if ((e1->type == E_NOT && e1->left.expr->type == E_SYMBOL && e2->type == E_SYMBOL) ||
+		    (e2->type == E_NOT && e2->left.expr->type == E_SYMBOL && e1->type == E_SYMBOL))
+			return expr_alloc_symbol(&symbol_yes);
+	}
+
+	if (DEBUG_EXPR) {
+		printf("optimize (");
+		expr_fprint(e1, stdout);
+		printf(") || (");
+		expr_fprint(e2, stdout);
+		printf(")?\n");
+	}
+	return NULL;
+}
+
+struct expr *expr_join_and(struct expr *e1, struct expr *e2)
+{
+	struct expr *tmp;
+	struct symbol *sym1, *sym2;
+
+	if (expr_eq(e1, e2))
+		return expr_copy(e1);
+	if (e1->type != E_EQUAL && e1->type != E_UNEQUAL && e1->type != E_SYMBOL && e1->type != E_NOT)
+		return NULL;
+	if (e2->type != E_EQUAL && e2->type != E_UNEQUAL && e2->type != E_SYMBOL && e2->type != E_NOT)
+		return NULL;
+	if (e1->type == E_NOT) {
+		tmp = e1->left.expr;
+		if (tmp->type != E_EQUAL && tmp->type != E_UNEQUAL && tmp->type != E_SYMBOL)
+			return NULL;
+		sym1 = tmp->left.sym;
+	} else
+		sym1 = e1->left.sym;
+	if (e2->type == E_NOT) {
+		if (e2->left.expr->type != E_SYMBOL)
+			return NULL;
+		sym2 = e2->left.expr->left.sym;
+	} else
+		sym2 = e2->left.sym;
+	if (sym1 != sym2)
+		return NULL;
+	if (sym1->type != S_BOOLEAN && sym1->type != S_TRISTATE)
+		return NULL;
+
+	if ((e1->type == E_SYMBOL && e2->type == E_EQUAL && e2->right.sym == &symbol_yes) ||
+	    (e2->type == E_SYMBOL && e1->type == E_EQUAL && e1->right.sym == &symbol_yes))
+		// (a) && (a='y') -> (a='y')
+		return expr_alloc_comp(E_EQUAL, sym1, &symbol_yes);
+
+	if ((e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_no) ||
+	    (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_no))
+		// (a) && (a!='n') -> (a)
+		return expr_alloc_symbol(sym1);
+
+	if ((e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_mod) ||
+	    (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_mod))
+		// (a) && (a!='m') -> (a='y')
+		return expr_alloc_comp(E_EQUAL, sym1, &symbol_yes);
+
+	if (sym1->type == S_TRISTATE) {
+		if (e1->type == E_EQUAL && e2->type == E_UNEQUAL) {
+			// (a='b') && (a!='c') -> 'b'='c' ? 'n' : a='b'
+			sym2 = e1->right.sym;
+			if ((e2->right.sym->flags & SYMBOL_CONST) && (sym2->flags & SYMBOL_CONST))
+				return sym2 != e2->right.sym ? expr_alloc_comp(E_EQUAL, sym1, sym2)
+							     : expr_alloc_symbol(&symbol_no);
+		}
+		if (e1->type == E_UNEQUAL && e2->type == E_EQUAL) {
+			// (a='b') && (a!='c') -> 'b'='c' ? 'n' : a='b'
+			sym2 = e2->right.sym;
+			if ((e1->right.sym->flags & SYMBOL_CONST) && (sym2->flags & SYMBOL_CONST))
+				return sym2 != e1->right.sym ? expr_alloc_comp(E_EQUAL, sym1, sym2)
+							     : expr_alloc_symbol(&symbol_no);
+		}
+		if (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL &&
+			   ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_no) ||
+			    (e1->right.sym == &symbol_no && e2->right.sym == &symbol_yes)))
+			// (a!='y') && (a!='n') -> (a='m')
+			return expr_alloc_comp(E_EQUAL, sym1, &symbol_mod);
+
+		if (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL &&
+			   ((e1->right.sym == &symbol_yes && e2->right.sym == &symbol_mod) ||
+			    (e1->right.sym == &symbol_mod && e2->right.sym == &symbol_yes)))
+			// (a!='y') && (a!='m') -> (a='n')
+			return expr_alloc_comp(E_EQUAL, sym1, &symbol_no);
+
+		if (e1->type == E_UNEQUAL && e2->type == E_UNEQUAL &&
+			   ((e1->right.sym == &symbol_mod && e2->right.sym == &symbol_no) ||
+			    (e1->right.sym == &symbol_no && e2->right.sym == &symbol_mod)))
+			// (a!='m') && (a!='n') -> (a='m')
+			return expr_alloc_comp(E_EQUAL, sym1, &symbol_yes);
+
+		if ((e1->type == E_SYMBOL && e2->type == E_EQUAL && e2->right.sym == &symbol_mod) ||
+		    (e2->type == E_SYMBOL && e1->type == E_EQUAL && e1->right.sym == &symbol_mod) ||
+		    (e1->type == E_SYMBOL && e2->type == E_UNEQUAL && e2->right.sym == &symbol_yes) ||
+		    (e2->type == E_SYMBOL && e1->type == E_UNEQUAL && e1->right.sym == &symbol_yes))
+			return NULL;
+	}
+
+	if (DEBUG_EXPR) {
+		printf("optimize (");
+		expr_fprint(e1, stdout);
+		printf(") && (");
+		expr_fprint(e2, stdout);
+		printf(")?\n");
+	}
+	return NULL;
+}
+
+static void expr_eliminate_dups1(enum expr_type type, struct expr **ep1, struct expr **ep2)
+{
+#define e1 (*ep1)
+#define e2 (*ep2)
+	struct expr *tmp;
+
+	if (e1->type == type) {
+		expr_eliminate_dups1(type, &e1->left.expr, &e2);
+		expr_eliminate_dups1(type, &e1->right.expr, &e2);
+		return;
+	}
+	if (e2->type == type) {
+		expr_eliminate_dups1(type, &e1, &e2->left.expr);
+		expr_eliminate_dups1(type, &e1, &e2->right.expr);
+		return;
+	}
+	if (e1 == e2)
+		return;
+
+	switch (e1->type) {
+	case E_OR: case E_AND:
+		expr_eliminate_dups1(e1->type, &e1, &e1);
+	default:
+		;
+	}
+
+	switch (type) {
+	case E_OR:
+		tmp = expr_join_or(e1, e2);
+		if (tmp) {
+			expr_free(e1); expr_free(e2);
+			e1 = expr_alloc_symbol(&symbol_no);
+			e2 = tmp;
+			trans_count++;
+		}
+		break;
+	case E_AND:
+		tmp = expr_join_and(e1, e2);
+		if (tmp) {
+			expr_free(e1); expr_free(e2);
+			e1 = expr_alloc_symbol(&symbol_yes);
+			e2 = tmp;
+			trans_count++;
+		}
+		break;
+	default:
+		;
+	}
+#undef e1
+#undef e2
+}
+
+static void expr_eliminate_dups2(enum expr_type type, struct expr **ep1, struct expr **ep2)
+{
+#define e1 (*ep1)
+#define e2 (*ep2)
+	struct expr *tmp, *tmp1, *tmp2;
+
+	if (e1->type == type) {
+		expr_eliminate_dups2(type, &e1->left.expr, &e2);
+		expr_eliminate_dups2(type, &e1->right.expr, &e2);
+		return;
+	}
+	if (e2->type == type) {
+		expr_eliminate_dups2(type, &e1, &e2->left.expr);
+		expr_eliminate_dups2(type, &e1, &e2->right.expr);
+	}
+	if (e1 == e2)
+		return;
+
+	switch (e1->type) {
+	case E_OR:
+		expr_eliminate_dups2(e1->type, &e1, &e1);
+		// (FOO || BAR) && (!FOO && !BAR) -> n
+		tmp1 = expr_transform(expr_alloc_one(E_NOT, expr_copy(e1)));
+		tmp2 = expr_copy(e2);
+		tmp = expr_extract_eq_and(&tmp1, &tmp2);
+		if (expr_is_yes(tmp1)) {
+			expr_free(e1);
+			e1 = expr_alloc_symbol(&symbol_no);
+			trans_count++;
+		}
+		expr_free(tmp2);
+		expr_free(tmp1);
+		expr_free(tmp);
+		break;
+	case E_AND:
+		expr_eliminate_dups2(e1->type, &e1, &e1);
+		// (FOO && BAR) || (!FOO || !BAR) -> y
+		tmp1 = expr_transform(expr_alloc_one(E_NOT, expr_copy(e1)));
+		tmp2 = expr_copy(e2);
+		tmp = expr_extract_eq_or(&tmp1, &tmp2);
+		if (expr_is_no(tmp1)) {
+			expr_free(e1);
+			e1 = expr_alloc_symbol(&symbol_yes);
+			trans_count++;
+		}
+		expr_free(tmp2);
+		expr_free(tmp1);
+		expr_free(tmp);
+		break;
+	default:
+		;
+	}
+#undef e1
+#undef e2
+}
+
+struct expr *expr_eliminate_dups(struct expr *e)
+{
+	int oldcount;
+	if (!e)
+		return e;
+
+	oldcount = trans_count;
+	while (1) {
+		trans_count = 0;
+		switch (e->type) {
+		case E_OR: case E_AND:
+			expr_eliminate_dups1(e->type, &e, &e);
+			expr_eliminate_dups2(e->type, &e, &e);
+		default:
+			;
+		}
+		if (!trans_count)
+			break;
+		e = expr_eliminate_yn(e);
+	}
+	trans_count = oldcount;
+	return e;
+}
+
+struct expr *expr_transform(struct expr *e)
+{
+	struct expr *tmp;
+
+	if (!e)
+		return NULL;
+	switch (e->type) {
+	case E_EQUAL:
+	case E_UNEQUAL:
+	case E_SYMBOL:
+	case E_LIST:
+		break;
+	default:
+		e->left.expr = expr_transform(e->left.expr);
+		e->right.expr = expr_transform(e->right.expr);
+	}
+
+	switch (e->type) {
+	case E_EQUAL:
+		if (e->left.sym->type != S_BOOLEAN)
+			break;
+		if (e->right.sym == &symbol_no) {
+			e->type = E_NOT;
+			e->left.expr = expr_alloc_symbol(e->left.sym);
+			e->right.sym = NULL;
+			break;
+		}
+		if (e->right.sym == &symbol_mod) {
+			printf("boolean symbol %s tested for 'm'? test forced to 'n'\n", e->left.sym->name);
+			e->type = E_SYMBOL;
+			e->left.sym = &symbol_no;
+			e->right.sym = NULL;
+			break;
+		}
+		if (e->right.sym == &symbol_yes) {
+			e->type = E_SYMBOL;
+			e->right.sym = NULL;
+			break;
+		}
+		break;
+	case E_UNEQUAL:
+		if (e->left.sym->type != S_BOOLEAN)
+			break;
+		if (e->right.sym == &symbol_no) {
+			e->type = E_SYMBOL;
+			e->right.sym = NULL;
+			break;
+		}
+		if (e->right.sym == &symbol_mod) {
+			printf("boolean symbol %s tested for 'm'? test forced to 'y'\n", e->left.sym->name);
+			e->type = E_SYMBOL;
+			e->left.sym = &symbol_yes;
+			e->right.sym = NULL;
+			break;
+		}
+		if (e->right.sym == &symbol_yes) {
+			e->type = E_NOT;
+			e->left.expr = expr_alloc_symbol(e->left.sym);
+			e->right.sym = NULL;
+			break;
+		}
+		break;
+	case E_NOT:
+		switch (e->left.expr->type) {
+		case E_NOT:
+			// !!a -> a
+			tmp = e->left.expr->left.expr;
+			free(e->left.expr);
+			free(e);
+			e = tmp;
+			e = expr_transform(e);
+			break;
+		case E_EQUAL:
+		case E_UNEQUAL:
+			// !a='x' -> a!='x'
+			tmp = e->left.expr;
+			free(e);
+			e = tmp;
+			e->type = e->type == E_EQUAL ? E_UNEQUAL : E_EQUAL;
+			break;
+		case E_OR:
+			// !(a || b) -> !a && !b
+			tmp = e->left.expr;
+			e->type = E_AND;
+			e->right.expr = expr_alloc_one(E_NOT, tmp->right.expr);
+			tmp->type = E_NOT;
+			tmp->right.expr = NULL;
+			e = expr_transform(e);
+			break;
+		case E_AND:
+			// !(a && b) -> !a || !b
+			tmp = e->left.expr;
+			e->type = E_OR;
+			e->right.expr = expr_alloc_one(E_NOT, tmp->right.expr);
+			tmp->type = E_NOT;
+			tmp->right.expr = NULL;
+			e = expr_transform(e);
+			break;
+		case E_SYMBOL:
+			if (e->left.expr->left.sym == &symbol_yes) {
+				// !'y' -> 'n'
+				tmp = e->left.expr;
+				free(e);
+				e = tmp;
+				e->type = E_SYMBOL;
+				e->left.sym = &symbol_no;
+				break;
+			}
+			if (e->left.expr->left.sym == &symbol_mod) {
+				// !'m' -> 'm'
+				tmp = e->left.expr;
+				free(e);
+				e = tmp;
+				e->type = E_SYMBOL;
+				e->left.sym = &symbol_mod;
+				break;
+			}
+			if (e->left.expr->left.sym == &symbol_no) {
+				// !'n' -> 'y'
+				tmp = e->left.expr;
+				free(e);
+				e = tmp;
+				e->type = E_SYMBOL;
+				e->left.sym = &symbol_yes;
+				break;
+			}
+			break;
+		default:
+			;
+		}
+		break;
+	default:
+		;
+	}
+	return e;
+}
+
+int expr_contains_symbol(struct expr *dep, struct symbol *sym)
+{
+	if (!dep)
+		return 0;
+
+	switch (dep->type) {
+	case E_AND:
+	case E_OR:
+		return expr_contains_symbol(dep->left.expr, sym) ||
+		       expr_contains_symbol(dep->right.expr, sym);
+	case E_SYMBOL:
+		return dep->left.sym == sym;
+	case E_EQUAL:
+	case E_UNEQUAL:
+		return dep->left.sym == sym ||
+		       dep->right.sym == sym;
+	case E_NOT:
+		return expr_contains_symbol(dep->left.expr, sym);
+	default:
+		;
+	}
+	return 0;
+}
+
+bool expr_depends_symbol(struct expr *dep, struct symbol *sym)
+{
+	if (!dep)
+		return false;
+
+	switch (dep->type) {
+	case E_AND:
+		return expr_depends_symbol(dep->left.expr, sym) ||
+		       expr_depends_symbol(dep->right.expr, sym);
+	case E_SYMBOL:
+		return dep->left.sym == sym;
+	case E_EQUAL:
+		if (dep->left.sym == sym) {
+			if (dep->right.sym == &symbol_yes || dep->right.sym == &symbol_mod)
+				return true;
+		}
+		break;
+	case E_UNEQUAL:
+		if (dep->left.sym == sym) {
+			if (dep->right.sym == &symbol_no)
+				return true;
+		}
+		break;
+	default:
+		;
+	}
+ 	return false;
+}
+
+struct expr *expr_extract_eq_and(struct expr **ep1, struct expr **ep2)
+{
+	struct expr *tmp = NULL;
+	expr_extract_eq(E_AND, &tmp, ep1, ep2);
+	if (tmp) {
+		*ep1 = expr_eliminate_yn(*ep1);
+		*ep2 = expr_eliminate_yn(*ep2);
+	}
+	return tmp;
+}
+
+struct expr *expr_extract_eq_or(struct expr **ep1, struct expr **ep2)
+{
+	struct expr *tmp = NULL;
+	expr_extract_eq(E_OR, &tmp, ep1, ep2);
+	if (tmp) {
+		*ep1 = expr_eliminate_yn(*ep1);
+		*ep2 = expr_eliminate_yn(*ep2);
+	}
+	return tmp;
+}
+
+void expr_extract_eq(enum expr_type type, struct expr **ep, struct expr **ep1, struct expr **ep2)
+{
+#define e1 (*ep1)
+#define e2 (*ep2)
+	if (e1->type == type) {
+		expr_extract_eq(type, ep, &e1->left.expr, &e2);
+		expr_extract_eq(type, ep, &e1->right.expr, &e2);
+		return;
+	}
+	if (e2->type == type) {
+		expr_extract_eq(type, ep, ep1, &e2->left.expr);
+		expr_extract_eq(type, ep, ep1, &e2->right.expr);
+		return;
+	}
+	if (expr_eq(e1, e2)) {
+		*ep = *ep ? expr_alloc_two(type, *ep, e1) : e1;
+		expr_free(e2);
+		if (type == E_AND) {
+			e1 = expr_alloc_symbol(&symbol_yes);
+			e2 = expr_alloc_symbol(&symbol_yes);
+		} else if (type == E_OR) {
+			e1 = expr_alloc_symbol(&symbol_no);
+			e2 = expr_alloc_symbol(&symbol_no);
+		}
+	}
+#undef e1
+#undef e2
+}
+
+struct expr *expr_trans_compare(struct expr *e, enum expr_type type, struct symbol *sym)
+{
+	struct expr *e1, *e2;
+
+	if (!e) {
+		e = expr_alloc_symbol(sym);
+		if (type == E_UNEQUAL)
+			e = expr_alloc_one(E_NOT, e);
+		return e;
+	}
+	switch (e->type) {
+	case E_AND:
+		e1 = expr_trans_compare(e->left.expr, E_EQUAL, sym);
+		e2 = expr_trans_compare(e->right.expr, E_EQUAL, sym);
+		if (sym == &symbol_yes)
+			e = expr_alloc_two(E_AND, e1, e2);
+		if (sym == &symbol_no)
+			e = expr_alloc_two(E_OR, e1, e2);
+		if (type == E_UNEQUAL)
+			e = expr_alloc_one(E_NOT, e);
+		return e;
+	case E_OR:
+		e1 = expr_trans_compare(e->left.expr, E_EQUAL, sym);
+		e2 = expr_trans_compare(e->right.expr, E_EQUAL, sym);
+		if (sym == &symbol_yes)
+			e = expr_alloc_two(E_OR, e1, e2);
+		if (sym == &symbol_no)
+			e = expr_alloc_two(E_AND, e1, e2);
+		if (type == E_UNEQUAL)
+			e = expr_alloc_one(E_NOT, e);
+		return e;
+	case E_NOT:
+		return expr_trans_compare(e->left.expr, type == E_EQUAL ? E_UNEQUAL : E_EQUAL, sym);
+	case E_UNEQUAL:
+	case E_EQUAL:
+		if (type == E_EQUAL) {
+			if (sym == &symbol_yes)
+				return expr_copy(e);
+			if (sym == &symbol_mod)
+				return expr_alloc_symbol(&symbol_no);
+			if (sym == &symbol_no)
+				return expr_alloc_one(E_NOT, expr_copy(e));
+		} else {
+			if (sym == &symbol_yes)
+				return expr_alloc_one(E_NOT, expr_copy(e));
+			if (sym == &symbol_mod)
+				return expr_alloc_symbol(&symbol_yes);
+			if (sym == &symbol_no)
+				return expr_copy(e);
+		}
+		break;
+	case E_SYMBOL:
+		return expr_alloc_comp(type, e->left.sym, sym);
+	case E_LIST:
+	case E_RANGE:
+	case E_NONE:
+		/* panic */;
+	}
+	return NULL;
+}
+
+tristate expr_calc_value(struct expr *e)
+{
+	tristate val1, val2;
+	const char *str1, *str2;
+
+	if (!e)
+		return yes;
+
+	switch (e->type) {
+	case E_SYMBOL:
+		sym_calc_value(e->left.sym);
+		return e->left.sym->curr.tri;
+	case E_AND:
+		val1 = expr_calc_value(e->left.expr);
+		val2 = expr_calc_value(e->right.expr);
+		return EXPR_AND(val1, val2);
+	case E_OR:
+		val1 = expr_calc_value(e->left.expr);
+		val2 = expr_calc_value(e->right.expr);
+		return EXPR_OR(val1, val2);
+	case E_NOT:
+		val1 = expr_calc_value(e->left.expr);
+		return EXPR_NOT(val1);
+	case E_EQUAL:
+		sym_calc_value(e->left.sym);
+		sym_calc_value(e->right.sym);
+		str1 = sym_get_string_value(e->left.sym);
+		str2 = sym_get_string_value(e->right.sym);
+		return !strcmp(str1, str2) ? yes : no;
+	case E_UNEQUAL:
+		sym_calc_value(e->left.sym);
+		sym_calc_value(e->right.sym);
+		str1 = sym_get_string_value(e->left.sym);
+		str2 = sym_get_string_value(e->right.sym);
+		return !strcmp(str1, str2) ? no : yes;
+	default:
+		printf("expr_calc_value: %d?\n", e->type);
+		return no;
+	}
+}
+
+int expr_compare_type(enum expr_type t1, enum expr_type t2)
+{
+#if 0
+	return 1;
+#else
+	if (t1 == t2)
+		return 0;
+	switch (t1) {
+	case E_EQUAL:
+	case E_UNEQUAL:
+		if (t2 == E_NOT)
+			return 1;
+	case E_NOT:
+		if (t2 == E_AND)
+			return 1;
+	case E_AND:
+		if (t2 == E_OR)
+			return 1;
+	case E_OR:
+		if (t2 == E_LIST)
+			return 1;
+	case E_LIST:
+		if (t2 == 0)
+			return 1;
+	default:
+		return -1;
+	}
+	printf("[%dgt%d?]", t1, t2);
+	return 0;
+#endif
+}
+
+void expr_print(struct expr *e, void (*fn)(void *, struct symbol *, const char *), void *data, int prevtoken)
+{
+	if (!e) {
+		fn(data, NULL, "y");
+		return;
+	}
+
+	if (expr_compare_type(prevtoken, e->type) > 0)
+		fn(data, NULL, "(");
+	switch (e->type) {
+	case E_SYMBOL:
+		if (e->left.sym->name)
+			fn(data, e->left.sym, e->left.sym->name);
+		else
+			fn(data, NULL, "<choice>");
+		break;
+	case E_NOT:
+		fn(data, NULL, "!");
+		expr_print(e->left.expr, fn, data, E_NOT);
+		break;
+	case E_EQUAL:
+		if (e->left.sym->name)
+			fn(data, e->left.sym, e->left.sym->name);
+		else
+			fn(data, NULL, "<choice>");
+		fn(data, NULL, "=");
+		fn(data, e->right.sym, e->right.sym->name);
+		break;
+	case E_UNEQUAL:
+		if (e->left.sym->name)
+			fn(data, e->left.sym, e->left.sym->name);
+		else
+			fn(data, NULL, "<choice>");
+		fn(data, NULL, "!=");
+		fn(data, e->right.sym, e->right.sym->name);
+		break;
+	case E_OR:
+		expr_print(e->left.expr, fn, data, E_OR);
+		fn(data, NULL, " || ");
+		expr_print(e->right.expr, fn, data, E_OR);
+		break;
+	case E_AND:
+		expr_print(e->left.expr, fn, data, E_AND);
+		fn(data, NULL, " && ");
+		expr_print(e->right.expr, fn, data, E_AND);
+		break;
+	case E_LIST:
+		fn(data, e->right.sym, e->right.sym->name);
+		if (e->left.expr) {
+			fn(data, NULL, " ^ ");
+			expr_print(e->left.expr, fn, data, E_LIST);
+		}
+		break;
+	case E_RANGE:
+		fn(data, NULL, "[");
+		fn(data, e->left.sym, e->left.sym->name);
+		fn(data, NULL, " ");
+		fn(data, e->right.sym, e->right.sym->name);
+		fn(data, NULL, "]");
+		break;
+	default:
+	  {
+		char buf[32];
+		sprintf(buf, "<unknown type %d>", e->type);
+		fn(data, NULL, buf);
+		break;
+	  }
+	}
+	if (expr_compare_type(prevtoken, e->type) > 0)
+		fn(data, NULL, ")");
+}
+
+static void expr_print_file_helper(void *data, struct symbol *sym, const char *str)
+{
+	fwrite(str, strlen(str), 1, data);
+}
+
+void expr_fprint(struct expr *e, FILE *out)
+{
+	expr_print(e, expr_print_file_helper, out, E_NONE);
+}
+
+static void expr_print_gstr_helper(void *data, struct symbol *sym, const char *str)
+{
+	str_append((struct gstr*)data, str);
+}
+
+void expr_gstr_print(struct expr *e, struct gstr *gs)
+{
+	expr_print(e, expr_print_gstr_helper, gs, E_NONE);
+}

Added: trunk/coreboot-v2/util/kconfig/expr.h
===================================================================
--- trunk/coreboot-v2/util/kconfig/expr.h	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/expr.h	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel at linux-m68k.org>
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#ifndef EXPR_H
+#define EXPR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdio.h>
+#ifndef __cplusplus
+#ifndef __sun
+#include <stdbool.h>
+#else
+typedef short bool;
+enum { true=1, false=0};
+#endif
+#endif
+
+struct file {
+	struct file *next;
+	struct file *parent;
+	char *name;
+	int lineno;
+	int flags;
+};
+
+#define FILE_BUSY		0x0001
+#define FILE_SCANNED		0x0002
+
+typedef enum tristate {
+	no, mod, yes
+} tristate;
+
+enum expr_type {
+	E_NONE, E_OR, E_AND, E_NOT, E_EQUAL, E_UNEQUAL, E_LIST, E_SYMBOL, E_RANGE
+};
+
+union expr_data {
+	struct expr *expr;
+	struct symbol *sym;
+};
+
+struct expr {
+	enum expr_type type;
+	union expr_data left, right;
+};
+
+#define EXPR_OR(dep1, dep2)	(((dep1)>(dep2))?(dep1):(dep2))
+#define EXPR_AND(dep1, dep2)	(((dep1)<(dep2))?(dep1):(dep2))
+#define EXPR_NOT(dep)		(2-(dep))
+
+#define expr_list_for_each_sym(l, e, s) \
+	for (e = (l); e && (s = e->right.sym); e = e->left.expr)
+
+struct expr_value {
+	struct expr *expr;
+	tristate tri;
+};
+
+struct symbol_value {
+	void *val;
+	tristate tri;
+};
+
+enum symbol_type {
+	S_UNKNOWN, S_BOOLEAN, S_TRISTATE, S_INT, S_HEX, S_STRING, S_OTHER
+};
+
+enum {
+	S_DEF_USER,		/* main user value */
+	S_DEF_AUTO,
+};
+
+struct symbol {
+	struct symbol *next;
+	char *name;
+	enum symbol_type type;
+	struct symbol_value curr;
+	struct symbol_value def[4];
+	tristate visible;
+	int flags;
+	struct property *prop;
+	struct expr_value rev_dep;
+};
+
+#define for_all_symbols(i, sym) for (i = 0; i < 257; i++) for (sym = symbol_hash[i]; sym; sym = sym->next) if (sym->type != S_OTHER)
+
+#define SYMBOL_CONST		0x0001
+#define SYMBOL_CHECK		0x0008
+#define SYMBOL_CHOICE		0x0010
+#define SYMBOL_CHOICEVAL	0x0020
+#define SYMBOL_VALID		0x0080
+#define SYMBOL_OPTIONAL		0x0100
+#define SYMBOL_WRITE		0x0200
+#define SYMBOL_CHANGED		0x0400
+#define SYMBOL_AUTO		0x1000
+#define SYMBOL_CHECKED		0x2000
+#define SYMBOL_WARNED		0x8000
+#define SYMBOL_DEF		0x10000
+#define SYMBOL_DEF_USER		0x10000
+#define SYMBOL_DEF_AUTO		0x20000
+#define SYMBOL_DEF3		0x40000
+#define SYMBOL_DEF4		0x80000
+
+#define SYMBOL_MAXLENGTH	256
+#define SYMBOL_HASHSIZE		257
+#define SYMBOL_HASHMASK		0xff
+
+enum prop_type {
+	P_UNKNOWN, P_PROMPT, P_COMMENT, P_MENU, P_DEFAULT, P_CHOICE,
+	P_SELECT, P_RANGE, P_ENV
+};
+
+struct property {
+	struct property *next;
+	struct symbol *sym;
+	enum prop_type type;
+	const char *text;
+	struct expr_value visible;
+	struct expr *expr;
+	struct menu *menu;
+	struct file *file;
+	int lineno;
+};
+
+#define for_all_properties(sym, st, tok) \
+	for (st = sym->prop; st; st = st->next) \
+		if (st->type == (tok))
+#define for_all_defaults(sym, st) for_all_properties(sym, st, P_DEFAULT)
+#define for_all_choices(sym, st) for_all_properties(sym, st, P_CHOICE)
+#define for_all_prompts(sym, st) \
+	for (st = sym->prop; st; st = st->next) \
+		if (st->text)
+
+struct menu {
+	struct menu *next;
+	struct menu *parent;
+	struct menu *list;
+	struct symbol *sym;
+	struct property *prompt;
+	struct expr *dep;
+	unsigned int flags;
+	char *help;
+	struct file *file;
+	int lineno;
+	void *data;
+};
+
+#define MENU_CHANGED		0x0001
+#define MENU_ROOT		0x0002
+
+#ifndef SWIG
+
+extern struct file *file_list;
+extern struct file *current_file;
+struct file *lookup_file(const char *name);
+
+extern struct symbol symbol_yes, symbol_no, symbol_mod;
+extern struct symbol *modules_sym;
+extern struct symbol *sym_defconfig_list;
+extern int cdebug;
+struct expr *expr_alloc_symbol(struct symbol *sym);
+struct expr *expr_alloc_one(enum expr_type type, struct expr *ce);
+struct expr *expr_alloc_two(enum expr_type type, struct expr *e1, struct expr *e2);
+struct expr *expr_alloc_comp(enum expr_type type, struct symbol *s1, struct symbol *s2);
+struct expr *expr_alloc_and(struct expr *e1, struct expr *e2);
+struct expr *expr_alloc_or(struct expr *e1, struct expr *e2);
+struct expr *expr_copy(struct expr *org);
+void expr_free(struct expr *e);
+int expr_eq(struct expr *e1, struct expr *e2);
+void expr_eliminate_eq(struct expr **ep1, struct expr **ep2);
+tristate expr_calc_value(struct expr *e);
+struct expr *expr_eliminate_yn(struct expr *e);
+struct expr *expr_trans_bool(struct expr *e);
+struct expr *expr_eliminate_dups(struct expr *e);
+struct expr *expr_transform(struct expr *e);
+int expr_contains_symbol(struct expr *dep, struct symbol *sym);
+bool expr_depends_symbol(struct expr *dep, struct symbol *sym);
+struct expr *expr_extract_eq_and(struct expr **ep1, struct expr **ep2);
+struct expr *expr_extract_eq_or(struct expr **ep1, struct expr **ep2);
+void expr_extract_eq(enum expr_type type, struct expr **ep, struct expr **ep1, struct expr **ep2);
+struct expr *expr_trans_compare(struct expr *e, enum expr_type type, struct symbol *sym);
+
+void expr_fprint(struct expr *e, FILE *out);
+struct gstr; /* forward */
+void expr_gstr_print(struct expr *e, struct gstr *gs);
+
+static inline int expr_is_yes(struct expr *e)
+{
+	return !e || (e->type == E_SYMBOL && e->left.sym == &symbol_yes);
+}
+
+static inline int expr_is_no(struct expr *e)
+{
+	return e && (e->type == E_SYMBOL && e->left.sym == &symbol_no);
+}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EXPR_H */

Added: trunk/coreboot-v2/util/kconfig/gconf.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/gconf.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/gconf.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,1636 @@
+/* Hey EMACS -*- linux-c -*- */
+/*
+ *
+ * Copyright (C) 2002-2003 Romain Lievin <roms at tilp.info>
+ * Released under the terms of the GNU GPL v2.0.
+ *
+ */
+
+#ifdef HAVE_CONFIG_H
+#  include <config.h>
+#endif
+
+#include "lkc.h"
+#include "images.c"
+
+#include <glade/glade.h>
+#include <gtk/gtk.h>
+#include <glib.h>
+#include <gdk/gdkkeysyms.h>
+
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include <time.h>
+#include <stdlib.h>
+
+//#define DEBUG
+
+enum {
+	SINGLE_VIEW, SPLIT_VIEW, FULL_VIEW
+};
+
+static gint view_mode = FULL_VIEW;
+static gboolean show_name = TRUE;
+static gboolean show_range = TRUE;
+static gboolean show_value = TRUE;
+static gboolean show_all = FALSE;
+static gboolean show_debug = FALSE;
+static gboolean resizeable = FALSE;
+
+GtkWidget *main_wnd = NULL;
+GtkWidget *tree1_w = NULL;	// left  frame
+GtkWidget *tree2_w = NULL;	// right frame
+GtkWidget *text_w = NULL;
+GtkWidget *hpaned = NULL;
+GtkWidget *vpaned = NULL;
+GtkWidget *back_btn = NULL;
+GtkWidget *save_btn = NULL;
+GtkWidget *save_menu_item = NULL;
+
+GtkTextTag *tag1, *tag2;
+GdkColor color;
+
+GtkTreeStore *tree1, *tree2, *tree;
+GtkTreeModel *model1, *model2;
+static GtkTreeIter *parents[256];
+static gint indent;
+
+static struct menu *current; // current node for SINGLE view
+static struct menu *browsed; // browsed node for SPLIT view
+
+enum {
+	COL_OPTION, COL_NAME, COL_NO, COL_MOD, COL_YES, COL_VALUE,
+	COL_MENU, COL_COLOR, COL_EDIT, COL_PIXBUF,
+	COL_PIXVIS, COL_BTNVIS, COL_BTNACT, COL_BTNINC, COL_BTNRAD,
+	COL_NUMBER
+};
+
+static void display_list(void);
+static void display_tree(struct menu *menu);
+static void display_tree_part(void);
+static void update_tree(struct menu *src, GtkTreeIter * dst);
+static void set_node(GtkTreeIter * node, struct menu *menu, gchar ** row);
+static gchar **fill_row(struct menu *menu);
+static void conf_changed(void);
+
+/* Helping/Debugging Functions */
+
+
+const char *dbg_print_stype(int val)
+{
+	static char buf[256];
+
+	bzero(buf, 256);
+
+	if (val == S_UNKNOWN)
+		strcpy(buf, "unknown");
+	if (val == S_BOOLEAN)
+		strcpy(buf, "boolean");
+	if (val == S_TRISTATE)
+		strcpy(buf, "tristate");
+	if (val == S_INT)
+		strcpy(buf, "int");
+	if (val == S_HEX)
+		strcpy(buf, "hex");
+	if (val == S_STRING)
+		strcpy(buf, "string");
+	if (val == S_OTHER)
+		strcpy(buf, "other");
+
+#ifdef DEBUG
+	printf("%s", buf);
+#endif
+
+	return buf;
+}
+
+const char *dbg_print_flags(int val)
+{
+	static char buf[256];
+
+	bzero(buf, 256);
+
+	if (val & SYMBOL_CONST)
+		strcat(buf, "const/");
+	if (val & SYMBOL_CHECK)
+		strcat(buf, "check/");
+	if (val & SYMBOL_CHOICE)
+		strcat(buf, "choice/");
+	if (val & SYMBOL_CHOICEVAL)
+		strcat(buf, "choiceval/");
+	if (val & SYMBOL_VALID)
+		strcat(buf, "valid/");
+	if (val & SYMBOL_OPTIONAL)
+		strcat(buf, "optional/");
+	if (val & SYMBOL_WRITE)
+		strcat(buf, "write/");
+	if (val & SYMBOL_CHANGED)
+		strcat(buf, "changed/");
+	if (val & SYMBOL_AUTO)
+		strcat(buf, "auto/");
+
+	buf[strlen(buf) - 1] = '\0';
+#ifdef DEBUG
+	printf("%s", buf);
+#endif
+
+	return buf;
+}
+
+const char *dbg_print_ptype(int val)
+{
+	static char buf[256];
+
+	bzero(buf, 256);
+
+	if (val == P_UNKNOWN)
+		strcpy(buf, "unknown");
+	if (val == P_PROMPT)
+		strcpy(buf, "prompt");
+	if (val == P_COMMENT)
+		strcpy(buf, "comment");
+	if (val == P_MENU)
+		strcpy(buf, "menu");
+	if (val == P_DEFAULT)
+		strcpy(buf, "default");
+	if (val == P_CHOICE)
+		strcpy(buf, "choice");
+
+#ifdef DEBUG
+	printf("%s", buf);
+#endif
+
+	return buf;
+}
+
+
+void replace_button_icon(GladeXML * xml, GdkDrawable * window,
+			 GtkStyle * style, gchar * btn_name, gchar ** xpm)
+{
+	GdkPixmap *pixmap;
+	GdkBitmap *mask;
+	GtkToolButton *button;
+	GtkWidget *image;
+
+	pixmap = gdk_pixmap_create_from_xpm_d(window, &mask,
+					      &style->bg[GTK_STATE_NORMAL],
+					      xpm);
+
+	button = GTK_TOOL_BUTTON(glade_xml_get_widget(xml, btn_name));
+	image = gtk_image_new_from_pixmap(pixmap, mask);
+	gtk_widget_show(image);
+	gtk_tool_button_set_icon_widget(button, image);
+}
+
+/* Main Window Initialization */
+void init_main_window(const gchar * glade_file)
+{
+	GladeXML *xml;
+	GtkWidget *widget;
+	GtkTextBuffer *txtbuf;
+	char title[256];
+	GtkStyle *style;
+
+	xml = glade_xml_new(glade_file, "window1", NULL);
+	if (!xml)
+		g_error(_("GUI loading failed !\n"));
+	glade_xml_signal_autoconnect(xml);
+
+	main_wnd = glade_xml_get_widget(xml, "window1");
+	hpaned = glade_xml_get_widget(xml, "hpaned1");
+	vpaned = glade_xml_get_widget(xml, "vpaned1");
+	tree1_w = glade_xml_get_widget(xml, "treeview1");
+	tree2_w = glade_xml_get_widget(xml, "treeview2");
+	text_w = glade_xml_get_widget(xml, "textview3");
+
+	back_btn = glade_xml_get_widget(xml, "button1");
+	gtk_widget_set_sensitive(back_btn, FALSE);
+
+	widget = glade_xml_get_widget(xml, "show_name1");
+	gtk_check_menu_item_set_active((GtkCheckMenuItem *) widget,
+				       show_name);
+
+	widget = glade_xml_get_widget(xml, "show_range1");
+	gtk_check_menu_item_set_active((GtkCheckMenuItem *) widget,
+				       show_range);
+
+	widget = glade_xml_get_widget(xml, "show_data1");
+	gtk_check_menu_item_set_active((GtkCheckMenuItem *) widget,
+				       show_value);
+
+	save_btn = glade_xml_get_widget(xml, "button3");
+	save_menu_item = glade_xml_get_widget(xml, "save1");
+	conf_set_changed_callback(conf_changed);
+
+	style = gtk_widget_get_style(main_wnd);
+	widget = glade_xml_get_widget(xml, "toolbar1");
+
+#if 0	/* Use stock Gtk icons instead */
+	replace_button_icon(xml, main_wnd->window, style,
+			    "button1", (gchar **) xpm_back);
+	replace_button_icon(xml, main_wnd->window, style,
+			    "button2", (gchar **) xpm_load);
+	replace_button_icon(xml, main_wnd->window, style,
+			    "button3", (gchar **) xpm_save);
+#endif
+	replace_button_icon(xml, main_wnd->window, style,
+			    "button4", (gchar **) xpm_single_view);
+	replace_button_icon(xml, main_wnd->window, style,
+			    "button5", (gchar **) xpm_split_view);
+	replace_button_icon(xml, main_wnd->window, style,
+			    "button6", (gchar **) xpm_tree_view);
+
+#if 0
+	switch (view_mode) {
+	case SINGLE_VIEW:
+		widget = glade_xml_get_widget(xml, "button4");
+		g_signal_emit_by_name(widget, "clicked");
+		break;
+	case SPLIT_VIEW:
+		widget = glade_xml_get_widget(xml, "button5");
+		g_signal_emit_by_name(widget, "clicked");
+		break;
+	case FULL_VIEW:
+		widget = glade_xml_get_widget(xml, "button6");
+		g_signal_emit_by_name(widget, "clicked");
+		break;
+	}
+#endif
+	txtbuf = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w));
+	tag1 = gtk_text_buffer_create_tag(txtbuf, "mytag1",
+					  "foreground", "red",
+					  "weight", PANGO_WEIGHT_BOLD,
+					  NULL);
+	tag2 = gtk_text_buffer_create_tag(txtbuf, "mytag2",
+					  /*"style", PANGO_STYLE_OBLIQUE, */
+					  NULL);
+
+	sprintf(title, _("coreboot v%s Configuration"),
+		getenv("KERNELVERSION"));
+	gtk_window_set_title(GTK_WINDOW(main_wnd), title);
+
+	gtk_widget_show(main_wnd);
+}
+
+void init_tree_model(void)
+{
+	gint i;
+
+	tree = tree2 = gtk_tree_store_new(COL_NUMBER,
+					  G_TYPE_STRING, G_TYPE_STRING,
+					  G_TYPE_STRING, G_TYPE_STRING,
+					  G_TYPE_STRING, G_TYPE_STRING,
+					  G_TYPE_POINTER, GDK_TYPE_COLOR,
+					  G_TYPE_BOOLEAN, GDK_TYPE_PIXBUF,
+					  G_TYPE_BOOLEAN, G_TYPE_BOOLEAN,
+					  G_TYPE_BOOLEAN, G_TYPE_BOOLEAN,
+					  G_TYPE_BOOLEAN);
+	model2 = GTK_TREE_MODEL(tree2);
+
+	for (parents[0] = NULL, i = 1; i < 256; i++)
+		parents[i] = (GtkTreeIter *) g_malloc(sizeof(GtkTreeIter));
+
+	tree1 = gtk_tree_store_new(COL_NUMBER,
+				   G_TYPE_STRING, G_TYPE_STRING,
+				   G_TYPE_STRING, G_TYPE_STRING,
+				   G_TYPE_STRING, G_TYPE_STRING,
+				   G_TYPE_POINTER, GDK_TYPE_COLOR,
+				   G_TYPE_BOOLEAN, GDK_TYPE_PIXBUF,
+				   G_TYPE_BOOLEAN, G_TYPE_BOOLEAN,
+				   G_TYPE_BOOLEAN, G_TYPE_BOOLEAN,
+				   G_TYPE_BOOLEAN);
+	model1 = GTK_TREE_MODEL(tree1);
+}
+
+void init_left_tree(void)
+{
+	GtkTreeView *view = GTK_TREE_VIEW(tree1_w);
+	GtkCellRenderer *renderer;
+	GtkTreeSelection *sel;
+	GtkTreeViewColumn *column;
+
+	gtk_tree_view_set_model(view, model1);
+	gtk_tree_view_set_headers_visible(view, TRUE);
+	gtk_tree_view_set_rules_hint(view, FALSE);
+
+	column = gtk_tree_view_column_new();
+	gtk_tree_view_append_column(view, column);
+	gtk_tree_view_column_set_title(column, _("Options"));
+
+	renderer = gtk_cell_renderer_toggle_new();
+	gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column),
+					renderer, FALSE);
+	gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column),
+					    renderer,
+					    "active", COL_BTNACT,
+					    "inconsistent", COL_BTNINC,
+					    "visible", COL_BTNVIS,
+					    "radio", COL_BTNRAD, NULL);
+	renderer = gtk_cell_renderer_text_new();
+	gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column),
+					renderer, FALSE);
+	gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column),
+					    renderer,
+					    "text", COL_OPTION,
+					    "foreground-gdk",
+					    COL_COLOR, NULL);
+
+	sel = gtk_tree_view_get_selection(view);
+	gtk_tree_selection_set_mode(sel, GTK_SELECTION_SINGLE);
+	gtk_widget_realize(tree1_w);
+}
+
+static void renderer_edited(GtkCellRendererText * cell,
+			    const gchar * path_string,
+			    const gchar * new_text, gpointer user_data);
+static void renderer_toggled(GtkCellRendererToggle * cellrenderertoggle,
+			     gchar * arg1, gpointer user_data);
+
+void init_right_tree(void)
+{
+	GtkTreeView *view = GTK_TREE_VIEW(tree2_w);
+	GtkCellRenderer *renderer;
+	GtkTreeSelection *sel;
+	GtkTreeViewColumn *column;
+	gint i;
+
+	gtk_tree_view_set_model(view, model2);
+	gtk_tree_view_set_headers_visible(view, TRUE);
+	gtk_tree_view_set_rules_hint(view, FALSE);
+
+	column = gtk_tree_view_column_new();
+	gtk_tree_view_append_column(view, column);
+	gtk_tree_view_column_set_title(column, _("Options"));
+
+	renderer = gtk_cell_renderer_pixbuf_new();
+	gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column),
+					renderer, FALSE);
+	gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column),
+					    renderer,
+					    "pixbuf", COL_PIXBUF,
+					    "visible", COL_PIXVIS, NULL);
+	renderer = gtk_cell_renderer_toggle_new();
+	gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column),
+					renderer, FALSE);
+	gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column),
+					    renderer,
+					    "active", COL_BTNACT,
+					    "inconsistent", COL_BTNINC,
+					    "visible", COL_BTNVIS,
+					    "radio", COL_BTNRAD, NULL);
+	/*g_signal_connect(G_OBJECT(renderer), "toggled",
+	   G_CALLBACK(renderer_toggled), NULL); */
+	renderer = gtk_cell_renderer_text_new();
+	gtk_tree_view_column_pack_start(GTK_TREE_VIEW_COLUMN(column),
+					renderer, FALSE);
+	gtk_tree_view_column_set_attributes(GTK_TREE_VIEW_COLUMN(column),
+					    renderer,
+					    "text", COL_OPTION,
+					    "foreground-gdk",
+					    COL_COLOR, NULL);
+
+	renderer = gtk_cell_renderer_text_new();
+	gtk_tree_view_insert_column_with_attributes(view, -1,
+						    _("Name"), renderer,
+						    "text", COL_NAME,
+						    "foreground-gdk",
+						    COL_COLOR, NULL);
+	renderer = gtk_cell_renderer_text_new();
+	gtk_tree_view_insert_column_with_attributes(view, -1,
+						    "N", renderer,
+						    "text", COL_NO,
+						    "foreground-gdk",
+						    COL_COLOR, NULL);
+	renderer = gtk_cell_renderer_text_new();
+	gtk_tree_view_insert_column_with_attributes(view, -1,
+						    "M", renderer,
+						    "text", COL_MOD,
+						    "foreground-gdk",
+						    COL_COLOR, NULL);
+	renderer = gtk_cell_renderer_text_new();
+	gtk_tree_view_insert_column_with_attributes(view, -1,
+						    "Y", renderer,
+						    "text", COL_YES,
+						    "foreground-gdk",
+						    COL_COLOR, NULL);
+	renderer = gtk_cell_renderer_text_new();
+	gtk_tree_view_insert_column_with_attributes(view, -1,
+						    _("Value"), renderer,
+						    "text", COL_VALUE,
+						    "editable",
+						    COL_EDIT,
+						    "foreground-gdk",
+						    COL_COLOR, NULL);
+	g_signal_connect(G_OBJECT(renderer), "edited",
+			 G_CALLBACK(renderer_edited), NULL);
+
+	column = gtk_tree_view_get_column(view, COL_NAME);
+	gtk_tree_view_column_set_visible(column, show_name);
+	column = gtk_tree_view_get_column(view, COL_NO);
+	gtk_tree_view_column_set_visible(column, show_range);
+	column = gtk_tree_view_get_column(view, COL_MOD);
+	gtk_tree_view_column_set_visible(column, show_range);
+	column = gtk_tree_view_get_column(view, COL_YES);
+	gtk_tree_view_column_set_visible(column, show_range);
+	column = gtk_tree_view_get_column(view, COL_VALUE);
+	gtk_tree_view_column_set_visible(column, show_value);
+
+	if (resizeable) {
+		for (i = 0; i < COL_VALUE; i++) {
+			column = gtk_tree_view_get_column(view, i);
+			gtk_tree_view_column_set_resizable(column, TRUE);
+		}
+	}
+
+	sel = gtk_tree_view_get_selection(view);
+	gtk_tree_selection_set_mode(sel, GTK_SELECTION_SINGLE);
+}
+
+
+/* Utility Functions */
+
+
+static void text_insert_help(struct menu *menu)
+{
+	GtkTextBuffer *buffer;
+	GtkTextIter start, end;
+	const char *prompt = _(menu_get_prompt(menu));
+	gchar *name;
+	const char *help;
+
+	help = menu_get_help(menu);
+
+	/* Gettextize if the help text not empty */
+	if ((help != 0) && (help[0] != 0))
+		help = _(help);
+
+	if (menu->sym && menu->sym->name)
+		name = g_strdup_printf(menu->sym->name);
+	else
+		name = g_strdup("");
+
+	buffer = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w));
+	gtk_text_buffer_get_bounds(buffer, &start, &end);
+	gtk_text_buffer_delete(buffer, &start, &end);
+	gtk_text_view_set_left_margin(GTK_TEXT_VIEW(text_w), 15);
+
+	gtk_text_buffer_get_end_iter(buffer, &end);
+	gtk_text_buffer_insert_with_tags(buffer, &end, prompt, -1, tag1,
+					 NULL);
+	gtk_text_buffer_insert_at_cursor(buffer, " ", 1);
+	gtk_text_buffer_get_end_iter(buffer, &end);
+	gtk_text_buffer_insert_with_tags(buffer, &end, name, -1, tag1,
+					 NULL);
+	gtk_text_buffer_insert_at_cursor(buffer, "\n\n", 2);
+	gtk_text_buffer_get_end_iter(buffer, &end);
+	gtk_text_buffer_insert_with_tags(buffer, &end, help, -1, tag2,
+					 NULL);
+}
+
+
+static void text_insert_msg(const char *title, const char *message)
+{
+	GtkTextBuffer *buffer;
+	GtkTextIter start, end;
+	const char *msg = message;
+
+	buffer = gtk_text_view_get_buffer(GTK_TEXT_VIEW(text_w));
+	gtk_text_buffer_get_bounds(buffer, &start, &end);
+	gtk_text_buffer_delete(buffer, &start, &end);
+	gtk_text_view_set_left_margin(GTK_TEXT_VIEW(text_w), 15);
+
+	gtk_text_buffer_get_end_iter(buffer, &end);
+	gtk_text_buffer_insert_with_tags(buffer, &end, title, -1, tag1,
+					 NULL);
+	gtk_text_buffer_insert_at_cursor(buffer, "\n\n", 2);
+	gtk_text_buffer_get_end_iter(buffer, &end);
+	gtk_text_buffer_insert_with_tags(buffer, &end, msg, -1, tag2,
+					 NULL);
+}
+
+
+/* Main Windows Callbacks */
+
+void on_save_activate(GtkMenuItem * menuitem, gpointer user_data);
+gboolean on_window1_delete_event(GtkWidget * widget, GdkEvent * event,
+				 gpointer user_data)
+{
+	GtkWidget *dialog, *label;
+	gint result;
+
+	if (!conf_get_changed())
+		return FALSE;
+
+	dialog = gtk_dialog_new_with_buttons(_("Warning !"),
+					     GTK_WINDOW(main_wnd),
+					     (GtkDialogFlags)
+					     (GTK_DIALOG_MODAL |
+					      GTK_DIALOG_DESTROY_WITH_PARENT),
+					     GTK_STOCK_OK,
+					     GTK_RESPONSE_YES,
+					     GTK_STOCK_NO,
+					     GTK_RESPONSE_NO,
+					     GTK_STOCK_CANCEL,
+					     GTK_RESPONSE_CANCEL, NULL);
+	gtk_dialog_set_default_response(GTK_DIALOG(dialog),
+					GTK_RESPONSE_CANCEL);
+
+	label = gtk_label_new(_("\nSave configuration ?\n"));
+	gtk_container_add(GTK_CONTAINER(GTK_DIALOG(dialog)->vbox), label);
+	gtk_widget_show(label);
+
+	result = gtk_dialog_run(GTK_DIALOG(dialog));
+	switch (result) {
+	case GTK_RESPONSE_YES:
+		on_save_activate(NULL, NULL);
+		return FALSE;
+	case GTK_RESPONSE_NO:
+		return FALSE;
+	case GTK_RESPONSE_CANCEL:
+	case GTK_RESPONSE_DELETE_EVENT:
+	default:
+		gtk_widget_destroy(dialog);
+		return TRUE;
+	}
+
+	return FALSE;
+}
+
+
+void on_window1_destroy(GtkObject * object, gpointer user_data)
+{
+	gtk_main_quit();
+}
+
+
+void
+on_window1_size_request(GtkWidget * widget,
+			GtkRequisition * requisition, gpointer user_data)
+{
+	static gint old_h;
+	gint w, h;
+
+	if (widget->window == NULL)
+		gtk_window_get_default_size(GTK_WINDOW(main_wnd), &w, &h);
+	else
+		gdk_window_get_size(widget->window, &w, &h);
+
+	if (h == old_h)
+		return;
+	old_h = h;
+
+	gtk_paned_set_position(GTK_PANED(vpaned), 2 * h / 3);
+}
+
+
+/* Menu & Toolbar Callbacks */
+
+
+static void
+load_filename(GtkFileSelection * file_selector, gpointer user_data)
+{
+	const gchar *fn;
+
+	fn = gtk_file_selection_get_filename(GTK_FILE_SELECTION
+					     (user_data));
+
+	if (conf_read(fn))
+		text_insert_msg(_("Error"), _("Unable to load configuration !"));
+	else
+		display_tree(&rootmenu);
+}
+
+void on_load1_activate(GtkMenuItem * menuitem, gpointer user_data)
+{
+	GtkWidget *fs;
+
+	fs = gtk_file_selection_new(_("Load file..."));
+	g_signal_connect(GTK_OBJECT(GTK_FILE_SELECTION(fs)->ok_button),
+			 "clicked",
+			 G_CALLBACK(load_filename), (gpointer) fs);
+	g_signal_connect_swapped(GTK_OBJECT
+				 (GTK_FILE_SELECTION(fs)->ok_button),
+				 "clicked", G_CALLBACK(gtk_widget_destroy),
+				 (gpointer) fs);
+	g_signal_connect_swapped(GTK_OBJECT
+				 (GTK_FILE_SELECTION(fs)->cancel_button),
+				 "clicked", G_CALLBACK(gtk_widget_destroy),
+				 (gpointer) fs);
+	gtk_widget_show(fs);
+}
+
+
+void on_save_activate(GtkMenuItem * menuitem, gpointer user_data)
+{
+	if (conf_write(NULL))
+		text_insert_msg(_("Error"), _("Unable to save configuration !"));
+	if (conf_write_autoconf())
+		text_insert_msg(_("Error"), _("Unable to save configuration !"));
+}
+
+
+static void
+store_filename(GtkFileSelection * file_selector, gpointer user_data)
+{
+	const gchar *fn;
+
+	fn = gtk_file_selection_get_filename(GTK_FILE_SELECTION
+					     (user_data));
+
+	if (conf_write(fn))
+		text_insert_msg(_("Error"), _("Unable to save configuration !"));
+	if (conf_write_autoconf())
+		text_insert_msg(_("Error"), _("Unable to save configuration !"));
+
+	gtk_widget_destroy(GTK_WIDGET(user_data));
+}
+
+void on_save_as1_activate(GtkMenuItem * menuitem, gpointer user_data)
+{
+	GtkWidget *fs;
+
+	fs = gtk_file_selection_new(_("Save file as..."));
+	g_signal_connect(GTK_OBJECT(GTK_FILE_SELECTION(fs)->ok_button),
+			 "clicked",
+			 G_CALLBACK(store_filename), (gpointer) fs);
+	g_signal_connect_swapped(GTK_OBJECT
+				 (GTK_FILE_SELECTION(fs)->ok_button),
+				 "clicked", G_CALLBACK(gtk_widget_destroy),
+				 (gpointer) fs);
+	g_signal_connect_swapped(GTK_OBJECT
+				 (GTK_FILE_SELECTION(fs)->cancel_button),
+				 "clicked", G_CALLBACK(gtk_widget_destroy),
+				 (gpointer) fs);
+	gtk_widget_show(fs);
+}
+
+
+void on_quit1_activate(GtkMenuItem * menuitem, gpointer user_data)
+{
+	if (!on_window1_delete_event(NULL, NULL, NULL))
+		gtk_widget_destroy(GTK_WIDGET(main_wnd));
+}
+
+
+void on_show_name1_activate(GtkMenuItem * menuitem, gpointer user_data)
+{
+	GtkTreeViewColumn *col;
+
+	show_name = GTK_CHECK_MENU_ITEM(menuitem)->active;
+	col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_NAME);
+	if (col)
+		gtk_tree_view_column_set_visible(col, show_name);
+}
+
+
+void on_show_range1_activate(GtkMenuItem * menuitem, gpointer user_data)
+{
+	GtkTreeViewColumn *col;
+
+	show_range = GTK_CHECK_MENU_ITEM(menuitem)->active;
+	col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_NO);
+	if (col)
+		gtk_tree_view_column_set_visible(col, show_range);
+	col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_MOD);
+	if (col)
+		gtk_tree_view_column_set_visible(col, show_range);
+	col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_YES);
+	if (col)
+		gtk_tree_view_column_set_visible(col, show_range);
+
+}
+
+
+void on_show_data1_activate(GtkMenuItem * menuitem, gpointer user_data)
+{
+	GtkTreeViewColumn *col;
+
+	show_value = GTK_CHECK_MENU_ITEM(menuitem)->active;
+	col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), COL_VALUE);
+	if (col)
+		gtk_tree_view_column_set_visible(col, show_value);
+}
+
+
+void
+on_show_all_options1_activate(GtkMenuItem * menuitem, gpointer user_data)
+{
+	show_all = GTK_CHECK_MENU_ITEM(menuitem)->active;
+
+	gtk_tree_store_clear(tree2);
+	display_tree(&rootmenu);	// instead of update_tree to speed-up
+}
+
+
+void
+on_show_debug_info1_activate(GtkMenuItem * menuitem, gpointer user_data)
+{
+	show_debug = GTK_CHECK_MENU_ITEM(menuitem)->active;
+	update_tree(&rootmenu, NULL);
+}
+
+
+void on_introduction1_activate(GtkMenuItem * menuitem, gpointer user_data)
+{
+	GtkWidget *dialog;
+	const gchar *intro_text = _(
+	    "Welcome to gkc, the GTK+ graphical configuration tool\n"
+	    "for coreboot.\n"
+	    "For each option, a blank box indicates the feature is disabled, a\n"
+	    "check indicates it is enabled, and a dot indicates that it is to\n"
+	    "be compiled as a module.  Clicking on the box will cycle through the three states.\n"
+	    "\n"
+	    "If you do not see an option (e.g., a device driver) that you\n"
+	    "believe should be present, try turning on Show All Options\n"
+	    "under the Options menu.\n"
+	    "Although there is no cross reference yet to help you figure out\n"
+	    "what other options must be enabled to support the option you\n"
+	    "are interested in, you can still view the help of a grayed-out\n"
+	    "option.\n"
+	    "\n"
+	    "Toggling Show Debug Info under the Options menu will show \n"
+	    "the dependencies, which you can then match by examining other options.");
+
+	dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd),
+					GTK_DIALOG_DESTROY_WITH_PARENT,
+					GTK_MESSAGE_INFO,
+					GTK_BUTTONS_CLOSE, intro_text);
+	g_signal_connect_swapped(GTK_OBJECT(dialog), "response",
+				 G_CALLBACK(gtk_widget_destroy),
+				 GTK_OBJECT(dialog));
+	gtk_widget_show_all(dialog);
+}
+
+
+void on_about1_activate(GtkMenuItem * menuitem, gpointer user_data)
+{
+	GtkWidget *dialog;
+	const gchar *about_text =
+	    _("gkc is copyright (c) 2002 Romain Lievin <roms at lpg.ticalc.org>.\n"
+	      "Based on the source code from Roman Zippel.\n");
+
+	dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd),
+					GTK_DIALOG_DESTROY_WITH_PARENT,
+					GTK_MESSAGE_INFO,
+					GTK_BUTTONS_CLOSE, about_text);
+	g_signal_connect_swapped(GTK_OBJECT(dialog), "response",
+				 G_CALLBACK(gtk_widget_destroy),
+				 GTK_OBJECT(dialog));
+	gtk_widget_show_all(dialog);
+}
+
+
+void on_license1_activate(GtkMenuItem * menuitem, gpointer user_data)
+{
+	GtkWidget *dialog;
+	const gchar *license_text =
+	    _("gkc is released under the terms of the GNU GPL v2.\n"
+	      "For more information, please see the source code or\n"
+	      "visit http://www.fsf.org/licenses/licenses.html\n");
+
+	dialog = gtk_message_dialog_new(GTK_WINDOW(main_wnd),
+					GTK_DIALOG_DESTROY_WITH_PARENT,
+					GTK_MESSAGE_INFO,
+					GTK_BUTTONS_CLOSE, license_text);
+	g_signal_connect_swapped(GTK_OBJECT(dialog), "response",
+				 G_CALLBACK(gtk_widget_destroy),
+				 GTK_OBJECT(dialog));
+	gtk_widget_show_all(dialog);
+}
+
+
+void on_back_clicked(GtkButton * button, gpointer user_data)
+{
+	enum prop_type ptype;
+
+	current = current->parent;
+	ptype = current->prompt ? current->prompt->type : P_UNKNOWN;
+	if (ptype != P_MENU)
+		current = current->parent;
+	display_tree_part();
+
+	if (current == &rootmenu)
+		gtk_widget_set_sensitive(back_btn, FALSE);
+}
+
+
+void on_load_clicked(GtkButton * button, gpointer user_data)
+{
+	on_load1_activate(NULL, user_data);
+}
+
+
+void on_single_clicked(GtkButton * button, gpointer user_data)
+{
+	view_mode = SINGLE_VIEW;
+	gtk_paned_set_position(GTK_PANED(hpaned), 0);
+	gtk_widget_hide(tree1_w);
+	current = &rootmenu;
+	display_tree_part();
+}
+
+
+void on_split_clicked(GtkButton * button, gpointer user_data)
+{
+	gint w, h;
+	view_mode = SPLIT_VIEW;
+	gtk_widget_show(tree1_w);
+	gtk_window_get_default_size(GTK_WINDOW(main_wnd), &w, &h);
+	gtk_paned_set_position(GTK_PANED(hpaned), w / 2);
+	if (tree2)
+		gtk_tree_store_clear(tree2);
+	display_list();
+
+	/* Disable back btn, like in full mode. */
+	gtk_widget_set_sensitive(back_btn, FALSE);
+}
+
+
+void on_full_clicked(GtkButton * button, gpointer user_data)
+{
+	view_mode = FULL_VIEW;
+	gtk_paned_set_position(GTK_PANED(hpaned), 0);
+	gtk_widget_hide(tree1_w);
+	if (tree2)
+		gtk_tree_store_clear(tree2);
+	display_tree(&rootmenu);
+	gtk_widget_set_sensitive(back_btn, FALSE);
+}
+
+
+void on_collapse_clicked(GtkButton * button, gpointer user_data)
+{
+	gtk_tree_view_collapse_all(GTK_TREE_VIEW(tree2_w));
+}
+
+
+void on_expand_clicked(GtkButton * button, gpointer user_data)
+{
+	gtk_tree_view_expand_all(GTK_TREE_VIEW(tree2_w));
+}
+
+
+/* CTree Callbacks */
+
+/* Change hex/int/string value in the cell */
+static void renderer_edited(GtkCellRendererText * cell,
+			    const gchar * path_string,
+			    const gchar * new_text, gpointer user_data)
+{
+	GtkTreePath *path = gtk_tree_path_new_from_string(path_string);
+	GtkTreeIter iter;
+	const char *old_def, *new_def;
+	struct menu *menu;
+	struct symbol *sym;
+
+	if (!gtk_tree_model_get_iter(model2, &iter, path))
+		return;
+
+	gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1);
+	sym = menu->sym;
+
+	gtk_tree_model_get(model2, &iter, COL_VALUE, &old_def, -1);
+	new_def = new_text;
+
+	sym_set_string_value(sym, new_def);
+
+	update_tree(&rootmenu, NULL);
+
+	gtk_tree_path_free(path);
+}
+
+/* Change the value of a symbol and update the tree */
+static void change_sym_value(struct menu *menu, gint col)
+{
+	struct symbol *sym = menu->sym;
+	tristate oldval, newval;
+
+	if (!sym)
+		return;
+
+	if (col == COL_NO)
+		newval = no;
+	else if (col == COL_MOD)
+		newval = mod;
+	else if (col == COL_YES)
+		newval = yes;
+	else
+		return;
+
+	switch (sym_get_type(sym)) {
+	case S_BOOLEAN:
+	case S_TRISTATE:
+		oldval = sym_get_tristate_value(sym);
+		if (!sym_tristate_within_range(sym, newval))
+			newval = yes;
+		sym_set_tristate_value(sym, newval);
+		if (view_mode == FULL_VIEW)
+			update_tree(&rootmenu, NULL);
+		else if (view_mode == SPLIT_VIEW) {
+			update_tree(browsed, NULL);
+			display_list();
+		}
+		else if (view_mode == SINGLE_VIEW)
+			display_tree_part();	//fixme: keep exp/coll
+		break;
+	case S_INT:
+	case S_HEX:
+	case S_STRING:
+	default:
+		break;
+	}
+}
+
+static void toggle_sym_value(struct menu *menu)
+{
+	if (!menu->sym)
+		return;
+
+	sym_toggle_tristate_value(menu->sym);
+	if (view_mode == FULL_VIEW)
+		update_tree(&rootmenu, NULL);
+	else if (view_mode == SPLIT_VIEW) {
+		update_tree(browsed, NULL);
+		display_list();
+	}
+	else if (view_mode == SINGLE_VIEW)
+		display_tree_part();	//fixme: keep exp/coll
+}
+
+static void renderer_toggled(GtkCellRendererToggle * cell,
+			     gchar * path_string, gpointer user_data)
+{
+	GtkTreePath *path, *sel_path = NULL;
+	GtkTreeIter iter, sel_iter;
+	GtkTreeSelection *sel;
+	struct menu *menu;
+
+	path = gtk_tree_path_new_from_string(path_string);
+	if (!gtk_tree_model_get_iter(model2, &iter, path))
+		return;
+
+	sel = gtk_tree_view_get_selection(GTK_TREE_VIEW(tree2_w));
+	if (gtk_tree_selection_get_selected(sel, NULL, &sel_iter))
+		sel_path = gtk_tree_model_get_path(model2, &sel_iter);
+	if (!sel_path)
+		goto out1;
+	if (gtk_tree_path_compare(path, sel_path))
+		goto out2;
+
+	gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1);
+	toggle_sym_value(menu);
+
+      out2:
+	gtk_tree_path_free(sel_path);
+      out1:
+	gtk_tree_path_free(path);
+}
+
+static gint column2index(GtkTreeViewColumn * column)
+{
+	gint i;
+
+	for (i = 0; i < COL_NUMBER; i++) {
+		GtkTreeViewColumn *col;
+
+		col = gtk_tree_view_get_column(GTK_TREE_VIEW(tree2_w), i);
+		if (col == column)
+			return i;
+	}
+
+	return -1;
+}
+
+
+/* User click: update choice (full) or goes down (single) */
+gboolean
+on_treeview2_button_press_event(GtkWidget * widget,
+				GdkEventButton * event, gpointer user_data)
+{
+	GtkTreeView *view = GTK_TREE_VIEW(widget);
+	GtkTreePath *path;
+	GtkTreeViewColumn *column;
+	GtkTreeIter iter;
+	struct menu *menu;
+	gint col;
+
+#if GTK_CHECK_VERSION(2,1,4) // bug in ctree with earlier version of GTK
+	gint tx = (gint) event->x;
+	gint ty = (gint) event->y;
+	gint cx, cy;
+
+	gtk_tree_view_get_path_at_pos(view, tx, ty, &path, &column, &cx,
+				      &cy);
+#else
+	gtk_tree_view_get_cursor(view, &path, &column);
+#endif
+	if (path == NULL)
+		return FALSE;
+
+	if (!gtk_tree_model_get_iter(model2, &iter, path))
+		return FALSE;
+	gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1);
+
+	col = column2index(column);
+	if (event->type == GDK_2BUTTON_PRESS) {
+		enum prop_type ptype;
+		ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN;
+
+		if (ptype == P_MENU && view_mode != FULL_VIEW && col == COL_OPTION) {
+			// goes down into menu
+			current = menu;
+			display_tree_part();
+			gtk_widget_set_sensitive(back_btn, TRUE);
+		} else if ((col == COL_OPTION)) {
+			toggle_sym_value(menu);
+			gtk_tree_view_expand_row(view, path, TRUE);
+		}
+	} else {
+		if (col == COL_VALUE) {
+			toggle_sym_value(menu);
+			gtk_tree_view_expand_row(view, path, TRUE);
+		} else if (col == COL_NO || col == COL_MOD
+			   || col == COL_YES) {
+			change_sym_value(menu, col);
+			gtk_tree_view_expand_row(view, path, TRUE);
+		}
+	}
+
+	return FALSE;
+}
+
+/* Key pressed: update choice */
+gboolean
+on_treeview2_key_press_event(GtkWidget * widget,
+			     GdkEventKey * event, gpointer user_data)
+{
+	GtkTreeView *view = GTK_TREE_VIEW(widget);
+	GtkTreePath *path;
+	GtkTreeViewColumn *column;
+	GtkTreeIter iter;
+	struct menu *menu;
+	gint col;
+
+	gtk_tree_view_get_cursor(view, &path, &column);
+	if (path == NULL)
+		return FALSE;
+
+	if (event->keyval == GDK_space) {
+		if (gtk_tree_view_row_expanded(view, path))
+			gtk_tree_view_collapse_row(view, path);
+		else
+			gtk_tree_view_expand_row(view, path, FALSE);
+		return TRUE;
+	}
+	if (event->keyval == GDK_KP_Enter) {
+	}
+	if (widget == tree1_w)
+		return FALSE;
+
+	gtk_tree_model_get_iter(model2, &iter, path);
+	gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1);
+
+	if (!strcasecmp(event->string, "n"))
+		col = COL_NO;
+	else if (!strcasecmp(event->string, "m"))
+		col = COL_MOD;
+	else if (!strcasecmp(event->string, "y"))
+		col = COL_YES;
+	else
+		col = -1;
+	change_sym_value(menu, col);
+
+	return FALSE;
+}
+
+
+/* Row selection changed: update help */
+void
+on_treeview2_cursor_changed(GtkTreeView * treeview, gpointer user_data)
+{
+	GtkTreeSelection *selection;
+	GtkTreeIter iter;
+	struct menu *menu;
+
+	selection = gtk_tree_view_get_selection(treeview);
+	if (gtk_tree_selection_get_selected(selection, &model2, &iter)) {
+		gtk_tree_model_get(model2, &iter, COL_MENU, &menu, -1);
+		text_insert_help(menu);
+	}
+}
+
+
+/* User click: display sub-tree in the right frame. */
+gboolean
+on_treeview1_button_press_event(GtkWidget * widget,
+				GdkEventButton * event, gpointer user_data)
+{
+	GtkTreeView *view = GTK_TREE_VIEW(widget);
+	GtkTreePath *path;
+	GtkTreeViewColumn *column;
+	GtkTreeIter iter;
+	struct menu *menu;
+
+	gint tx = (gint) event->x;
+	gint ty = (gint) event->y;
+	gint cx, cy;
+
+	gtk_tree_view_get_path_at_pos(view, tx, ty, &path, &column, &cx,
+				      &cy);
+	if (path == NULL)
+		return FALSE;
+
+	gtk_tree_model_get_iter(model1, &iter, path);
+	gtk_tree_model_get(model1, &iter, COL_MENU, &menu, -1);
+
+	if (event->type == GDK_2BUTTON_PRESS) {
+		toggle_sym_value(menu);
+		current = menu;
+		display_tree_part();
+	} else {
+		browsed = menu;
+		display_tree_part();
+	}
+
+	gtk_widget_realize(tree2_w);
+	gtk_tree_view_set_cursor(view, path, NULL, FALSE);
+	gtk_widget_grab_focus(tree2_w);
+
+	return FALSE;
+}
+
+
+/* Fill a row of strings */
+static gchar **fill_row(struct menu *menu)
+{
+	static gchar *row[COL_NUMBER];
+	struct symbol *sym = menu->sym;
+	const char *def;
+	int stype;
+	tristate val;
+	enum prop_type ptype;
+	int i;
+
+	for (i = COL_OPTION; i <= COL_COLOR; i++)
+		g_free(row[i]);
+	bzero(row, sizeof(row));
+
+	row[COL_OPTION] =
+	    g_strdup_printf("%s %s", _(menu_get_prompt(menu)),
+			    sym && sym_has_value(sym) ? "(NEW)" : "");
+
+	if (show_all && !menu_is_visible(menu))
+		row[COL_COLOR] = g_strdup("DarkGray");
+	else
+		row[COL_COLOR] = g_strdup("Black");
+
+	ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN;
+	switch (ptype) {
+	case P_MENU:
+		row[COL_PIXBUF] = (gchar *) xpm_menu;
+		if (view_mode == SINGLE_VIEW)
+			row[COL_PIXVIS] = GINT_TO_POINTER(TRUE);
+		row[COL_BTNVIS] = GINT_TO_POINTER(FALSE);
+		break;
+	case P_COMMENT:
+		row[COL_PIXBUF] = (gchar *) xpm_void;
+		row[COL_PIXVIS] = GINT_TO_POINTER(FALSE);
+		row[COL_BTNVIS] = GINT_TO_POINTER(FALSE);
+		break;
+	default:
+		row[COL_PIXBUF] = (gchar *) xpm_void;
+		row[COL_PIXVIS] = GINT_TO_POINTER(FALSE);
+		row[COL_BTNVIS] = GINT_TO_POINTER(TRUE);
+		break;
+	}
+
+	if (!sym)
+		return row;
+	row[COL_NAME] = g_strdup(sym->name);
+
+	sym_calc_value(sym);
+	sym->flags &= ~SYMBOL_CHANGED;
+
+	if (sym_is_choice(sym)) {	// parse childs for getting final value
+		struct menu *child;
+		struct symbol *def_sym = sym_get_choice_value(sym);
+		struct menu *def_menu = NULL;
+
+		row[COL_BTNVIS] = GINT_TO_POINTER(FALSE);
+
+		for (child = menu->list; child; child = child->next) {
+			if (menu_is_visible(child)
+			    && child->sym == def_sym)
+				def_menu = child;
+		}
+
+		if (def_menu)
+			row[COL_VALUE] =
+			    g_strdup(_(menu_get_prompt(def_menu)));
+	}
+	if (sym->flags & SYMBOL_CHOICEVAL)
+		row[COL_BTNRAD] = GINT_TO_POINTER(TRUE);
+
+	stype = sym_get_type(sym);
+	switch (stype) {
+	case S_BOOLEAN:
+		if (GPOINTER_TO_INT(row[COL_PIXVIS]) == FALSE)
+			row[COL_BTNVIS] = GINT_TO_POINTER(TRUE);
+		if (sym_is_choice(sym))
+			break;
+	case S_TRISTATE:
+		val = sym_get_tristate_value(sym);
+		switch (val) {
+		case no:
+			row[COL_NO] = g_strdup("N");
+			row[COL_VALUE] = g_strdup("N");
+			row[COL_BTNACT] = GINT_TO_POINTER(FALSE);
+			row[COL_BTNINC] = GINT_TO_POINTER(FALSE);
+			break;
+		case mod:
+			row[COL_MOD] = g_strdup("M");
+			row[COL_VALUE] = g_strdup("M");
+			row[COL_BTNINC] = GINT_TO_POINTER(TRUE);
+			break;
+		case yes:
+			row[COL_YES] = g_strdup("Y");
+			row[COL_VALUE] = g_strdup("Y");
+			row[COL_BTNACT] = GINT_TO_POINTER(TRUE);
+			row[COL_BTNINC] = GINT_TO_POINTER(FALSE);
+			break;
+		}
+
+		if (val != no && sym_tristate_within_range(sym, no))
+			row[COL_NO] = g_strdup("_");
+		if (val != mod && sym_tristate_within_range(sym, mod))
+			row[COL_MOD] = g_strdup("_");
+		if (val != yes && sym_tristate_within_range(sym, yes))
+			row[COL_YES] = g_strdup("_");
+		break;
+	case S_INT:
+	case S_HEX:
+	case S_STRING:
+		def = sym_get_string_value(sym);
+		row[COL_VALUE] = g_strdup(def);
+		row[COL_EDIT] = GINT_TO_POINTER(TRUE);
+		row[COL_BTNVIS] = GINT_TO_POINTER(FALSE);
+		break;
+	}
+
+	return row;
+}
+
+
+/* Set the node content with a row of strings */
+static void set_node(GtkTreeIter * node, struct menu *menu, gchar ** row)
+{
+	GdkColor color;
+	gboolean success;
+	GdkPixbuf *pix;
+
+	pix = gdk_pixbuf_new_from_xpm_data((const char **)
+					   row[COL_PIXBUF]);
+
+	gdk_color_parse(row[COL_COLOR], &color);
+	gdk_colormap_alloc_colors(gdk_colormap_get_system(), &color, 1,
+				  FALSE, FALSE, &success);
+
+	gtk_tree_store_set(tree, node,
+			   COL_OPTION, row[COL_OPTION],
+			   COL_NAME, row[COL_NAME],
+			   COL_NO, row[COL_NO],
+			   COL_MOD, row[COL_MOD],
+			   COL_YES, row[COL_YES],
+			   COL_VALUE, row[COL_VALUE],
+			   COL_MENU, (gpointer) menu,
+			   COL_COLOR, &color,
+			   COL_EDIT, GPOINTER_TO_INT(row[COL_EDIT]),
+			   COL_PIXBUF, pix,
+			   COL_PIXVIS, GPOINTER_TO_INT(row[COL_PIXVIS]),
+			   COL_BTNVIS, GPOINTER_TO_INT(row[COL_BTNVIS]),
+			   COL_BTNACT, GPOINTER_TO_INT(row[COL_BTNACT]),
+			   COL_BTNINC, GPOINTER_TO_INT(row[COL_BTNINC]),
+			   COL_BTNRAD, GPOINTER_TO_INT(row[COL_BTNRAD]),
+			   -1);
+
+	g_object_unref(pix);
+}
+
+
+/* Add a node to the tree */
+static void place_node(struct menu *menu, char **row)
+{
+	GtkTreeIter *parent = parents[indent - 1];
+	GtkTreeIter *node = parents[indent];
+
+	gtk_tree_store_append(tree, node, parent);
+	set_node(node, menu, row);
+}
+
+
+/* Find a node in the GTK+ tree */
+static GtkTreeIter found;
+
+/*
+ * Find a menu in the GtkTree starting at parent.
+ */
+GtkTreeIter *gtktree_iter_find_node(GtkTreeIter * parent,
+				    struct menu *tofind)
+{
+	GtkTreeIter iter;
+	GtkTreeIter *child = &iter;
+	gboolean valid;
+	GtkTreeIter *ret;
+
+	valid = gtk_tree_model_iter_children(model2, child, parent);
+	while (valid) {
+		struct menu *menu;
+
+		gtk_tree_model_get(model2, child, 6, &menu, -1);
+
+		if (menu == tofind) {
+			memcpy(&found, child, sizeof(GtkTreeIter));
+			return &found;
+		}
+
+		ret = gtktree_iter_find_node(child, tofind);
+		if (ret)
+			return ret;
+
+		valid = gtk_tree_model_iter_next(model2, child);
+	}
+
+	return NULL;
+}
+
+
+/*
+ * Update the tree by adding/removing entries
+ * Does not change other nodes
+ */
+static void update_tree(struct menu *src, GtkTreeIter * dst)
+{
+	struct menu *child1;
+	GtkTreeIter iter, tmp;
+	GtkTreeIter *child2 = &iter;
+	gboolean valid;
+	GtkTreeIter *sibling;
+	struct symbol *sym;
+	struct property *prop;
+	struct menu *menu1, *menu2;
+
+	if (src == &rootmenu)
+		indent = 1;
+
+	valid = gtk_tree_model_iter_children(model2, child2, dst);
+	for (child1 = src->list; child1; child1 = child1->next) {
+
+		prop = child1->prompt;
+		sym = child1->sym;
+
+	      reparse:
+		menu1 = child1;
+		if (valid)
+			gtk_tree_model_get(model2, child2, COL_MENU,
+					   &menu2, -1);
+		else
+			menu2 = NULL;	// force adding of a first child
+
+#ifdef DEBUG
+		printf("%*c%s | %s\n", indent, ' ',
+		       menu1 ? menu_get_prompt(menu1) : "nil",
+		       menu2 ? menu_get_prompt(menu2) : "nil");
+#endif
+
+		if (!menu_is_visible(child1) && !show_all) {	// remove node
+			if (gtktree_iter_find_node(dst, menu1) != NULL) {
+				memcpy(&tmp, child2, sizeof(GtkTreeIter));
+				valid = gtk_tree_model_iter_next(model2,
+								 child2);
+				gtk_tree_store_remove(tree2, &tmp);
+				if (!valid)
+					return;	// next parent
+				else
+					goto reparse;	// next child
+			} else
+				continue;
+		}
+
+		if (menu1 != menu2) {
+			if (gtktree_iter_find_node(dst, menu1) == NULL) {	// add node
+				if (!valid && !menu2)
+					sibling = NULL;
+				else
+					sibling = child2;
+				gtk_tree_store_insert_before(tree2,
+							     child2,
+							     dst, sibling);
+				set_node(child2, menu1, fill_row(menu1));
+				if (menu2 == NULL)
+					valid = TRUE;
+			} else {	// remove node
+				memcpy(&tmp, child2, sizeof(GtkTreeIter));
+				valid = gtk_tree_model_iter_next(model2,
+								 child2);
+				gtk_tree_store_remove(tree2, &tmp);
+				if (!valid)
+					return;	// next parent
+				else
+					goto reparse;	// next child
+			}
+		} else if (sym && (sym->flags & SYMBOL_CHANGED)) {
+			set_node(child2, menu1, fill_row(menu1));
+		}
+
+		indent++;
+		update_tree(child1, child2);
+		indent--;
+
+		valid = gtk_tree_model_iter_next(model2, child2);
+	}
+}
+
+
+/* Display the whole tree (single/split/full view) */
+static void display_tree(struct menu *menu)
+{
+	struct symbol *sym;
+	struct property *prop;
+	struct menu *child;
+	enum prop_type ptype;
+
+	if (menu == &rootmenu) {
+		indent = 1;
+		current = &rootmenu;
+	}
+
+	for (child = menu->list; child; child = child->next) {
+		prop = child->prompt;
+		sym = child->sym;
+		ptype = prop ? prop->type : P_UNKNOWN;
+
+		if (sym)
+			sym->flags &= ~SYMBOL_CHANGED;
+
+		if ((view_mode == SPLIT_VIEW)
+		    && !(child->flags & MENU_ROOT) && (tree == tree1))
+			continue;
+
+		if ((view_mode == SPLIT_VIEW) && (child->flags & MENU_ROOT)
+		    && (tree == tree2))
+			continue;
+
+		if (menu_is_visible(child) || show_all)
+			place_node(child, fill_row(child));
+#ifdef DEBUG
+		printf("%*c%s: ", indent, ' ', menu_get_prompt(child));
+		printf("%s", child->flags & MENU_ROOT ? "rootmenu | " : "");
+		dbg_print_ptype(ptype);
+		printf(" | ");
+		if (sym) {
+			dbg_print_stype(sym->type);
+			printf(" | ");
+			dbg_print_flags(sym->flags);
+			printf("\n");
+		} else
+			printf("\n");
+#endif
+		if ((view_mode != FULL_VIEW) && (ptype == P_MENU)
+		    && (tree == tree2))
+			continue;
+/*
+                if (((menu != &rootmenu) && !(menu->flags & MENU_ROOT))
+		    || (view_mode == FULL_VIEW)
+		    || (view_mode == SPLIT_VIEW))*/
+		if (((view_mode == SINGLE_VIEW) && (menu->flags & MENU_ROOT))
+		    || (view_mode == FULL_VIEW)
+		    || (view_mode == SPLIT_VIEW)) {
+			indent++;
+			display_tree(child);
+			indent--;
+		}
+	}
+}
+
+/* Display a part of the tree starting at current node (single/split view) */
+static void display_tree_part(void)
+{
+	if (tree2)
+		gtk_tree_store_clear(tree2);
+	if (view_mode == SINGLE_VIEW)
+		display_tree(current);
+	else if (view_mode == SPLIT_VIEW)
+		display_tree(browsed);
+	gtk_tree_view_expand_all(GTK_TREE_VIEW(tree2_w));
+}
+
+/* Display the list in the left frame (split view) */
+static void display_list(void)
+{
+	if (tree1)
+		gtk_tree_store_clear(tree1);
+
+	tree = tree1;
+	display_tree(&rootmenu);
+	gtk_tree_view_expand_all(GTK_TREE_VIEW(tree1_w));
+	tree = tree2;
+}
+
+void fixup_rootmenu(struct menu *menu)
+{
+	struct menu *child;
+	static int menu_cnt = 0;
+
+	menu->flags |= MENU_ROOT;
+	for (child = menu->list; child; child = child->next) {
+		if (child->prompt && child->prompt->type == P_MENU) {
+			menu_cnt++;
+			fixup_rootmenu(child);
+			menu_cnt--;
+		} else if (!menu_cnt)
+			fixup_rootmenu(child);
+	}
+}
+
+
+/* Main */
+int main(int ac, char *av[])
+{
+	const char *name;
+	char *env;
+	gchar *glade_file;
+
+#ifndef LKC_DIRECT_LINK
+	kconfig_load();
+#endif
+
+	bindtextdomain(PACKAGE, LOCALEDIR);
+	bind_textdomain_codeset(PACKAGE, "UTF-8");
+	textdomain(PACKAGE);
+
+	/* GTK stuffs */
+	gtk_set_locale();
+	gtk_init(&ac, &av);
+	glade_init();
+
+	//add_pixmap_directory (PACKAGE_DATA_DIR "/" PACKAGE "/pixmaps");
+	//add_pixmap_directory (PACKAGE_SOURCE_DIR "/pixmaps");
+
+	/* Determine GUI path */
+	env = getenv(SRCTREE);
+	if (env)
+		glade_file = g_strconcat(env, "/util/kconfig/gconf.glade", NULL);
+	else if (av[0][0] == '/')
+		glade_file = g_strconcat(av[0], ".glade", NULL);
+	else
+		glade_file = g_strconcat(g_get_current_dir(), "/", av[0], ".glade", NULL);
+
+	/* Load the interface and connect signals */
+	init_main_window(glade_file);
+	init_tree_model();
+	init_left_tree();
+	init_right_tree();
+
+	/* Conf stuffs */
+	if (ac > 1 && av[1][0] == '-') {
+		switch (av[1][1]) {
+		case 'a':
+			//showAll = 1;
+			break;
+		case 'h':
+		case '?':
+			printf("%s <config>\n", av[0]);
+			exit(0);
+		}
+		name = av[2];
+	} else
+		name = av[1];
+
+	conf_parse(name);
+	fixup_rootmenu(&rootmenu);
+	conf_read(NULL);
+
+	switch (view_mode) {
+	case SINGLE_VIEW:
+		display_tree_part();
+		break;
+	case SPLIT_VIEW:
+		display_list();
+		break;
+	case FULL_VIEW:
+		display_tree(&rootmenu);
+		break;
+	}
+
+	gtk_main();
+
+	return 0;
+}
+
+static void conf_changed(void)
+{
+	bool changed = conf_get_changed();
+	gtk_widget_set_sensitive(save_btn, changed);
+	gtk_widget_set_sensitive(save_menu_item, changed);
+}

Added: trunk/coreboot-v2/util/kconfig/gconf.glade
===================================================================
--- trunk/coreboot-v2/util/kconfig/gconf.glade	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/gconf.glade	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,648 @@
+<?xml version="1.0" standalone="no"?> <!--*- mode: xml -*-->
+<!DOCTYPE glade-interface SYSTEM "http://glade.gnome.org/glade-2.0.dtd">
+
+<glade-interface>
+
+<widget class="GtkWindow" id="window1">
+  <property name="visible">True</property>
+  <property name="title" translatable="yes">Gtk coreboot Configurator</property>
+  <property name="type">GTK_WINDOW_TOPLEVEL</property>
+  <property name="window_position">GTK_WIN_POS_NONE</property>
+  <property name="modal">False</property>
+  <property name="default_width">640</property>
+  <property name="default_height">480</property>
+  <property name="resizable">True</property>
+  <property name="destroy_with_parent">False</property>
+  <property name="decorated">True</property>
+  <property name="skip_taskbar_hint">False</property>
+  <property name="skip_pager_hint">False</property>
+  <property name="type_hint">GDK_WINDOW_TYPE_HINT_NORMAL</property>
+  <property name="gravity">GDK_GRAVITY_NORTH_WEST</property>
+  <signal name="destroy" handler="on_window1_destroy" object="window1"/>
+  <signal name="size_request" handler="on_window1_size_request" object="vpaned1" last_modification_time="Fri, 11 Jan 2002 16:17:11 GMT"/>
+  <signal name="delete_event" handler="on_window1_delete_event" object="window1" last_modification_time="Sun, 09 Mar 2003 19:42:46 GMT"/>
+
+  <child>
+    <widget class="GtkVBox" id="vbox1">
+      <property name="visible">True</property>
+      <property name="homogeneous">False</property>
+      <property name="spacing">0</property>
+
+      <child>
+	<widget class="GtkMenuBar" id="menubar1">
+	  <property name="visible">True</property>
+
+	  <child>
+	    <widget class="GtkMenuItem" id="file1">
+	      <property name="visible">True</property>
+	      <property name="label" translatable="yes">_File</property>
+	      <property name="use_underline">True</property>
+
+	      <child>
+		<widget class="GtkMenu" id="file1_menu">
+
+		  <child>
+		    <widget class="GtkImageMenuItem" id="load1">
+		      <property name="visible">True</property>
+		      <property name="tooltip" translatable="yes">Load a config file</property>
+		      <property name="label" translatable="yes">_Load</property>
+		      <property name="use_underline">True</property>
+		      <signal name="activate" handler="on_load1_activate"/>
+		      <accelerator key="L" modifiers="GDK_CONTROL_MASK" signal="activate"/>
+
+		      <child internal-child="image">
+			<widget class="GtkImage" id="image39">
+			  <property name="visible">True</property>
+			  <property name="stock">gtk-open</property>
+			  <property name="icon_size">1</property>
+			  <property name="xalign">0.5</property>
+			  <property name="yalign">0.5</property>
+			  <property name="xpad">0</property>
+			  <property name="ypad">0</property>
+			</widget>
+		      </child>
+		    </widget>
+		  </child>
+
+		  <child>
+		    <widget class="GtkImageMenuItem" id="save1">
+		      <property name="visible">True</property>
+		      <property name="tooltip" translatable="yes">Save the config in .config</property>
+		      <property name="label" translatable="yes">_Save</property>
+		      <property name="use_underline">True</property>
+		      <signal name="activate" handler="on_save_activate"/>
+		      <accelerator key="S" modifiers="GDK_CONTROL_MASK" signal="activate"/>
+
+		      <child internal-child="image">
+			<widget class="GtkImage" id="image40">
+			  <property name="visible">True</property>
+			  <property name="stock">gtk-save</property>
+			  <property name="icon_size">1</property>
+			  <property name="xalign">0.5</property>
+			  <property name="yalign">0.5</property>
+			  <property name="xpad">0</property>
+			  <property name="ypad">0</property>
+			</widget>
+		      </child>
+		    </widget>
+		  </child>
+
+		  <child>
+		    <widget class="GtkImageMenuItem" id="save_as1">
+		      <property name="visible">True</property>
+		      <property name="tooltip" translatable="yes">Save the config in a file</property>
+		      <property name="label" translatable="yes">Save _as</property>
+		      <property name="use_underline">True</property>
+		      <signal name="activate" handler="on_save_as1_activate"/>
+
+		      <child internal-child="image">
+			<widget class="GtkImage" id="image41">
+			  <property name="visible">True</property>
+			  <property name="stock">gtk-save-as</property>
+			  <property name="icon_size">1</property>
+			  <property name="xalign">0.5</property>
+			  <property name="yalign">0.5</property>
+			  <property name="xpad">0</property>
+			  <property name="ypad">0</property>
+			</widget>
+		      </child>
+		    </widget>
+		  </child>
+
+		  <child>
+		    <widget class="GtkSeparatorMenuItem" id="separator1">
+		      <property name="visible">True</property>
+		    </widget>
+		  </child>
+
+		  <child>
+		    <widget class="GtkImageMenuItem" id="quit1">
+		      <property name="visible">True</property>
+		      <property name="label" translatable="yes">_Quit</property>
+		      <property name="use_underline">True</property>
+		      <signal name="activate" handler="on_quit1_activate"/>
+		      <accelerator key="Q" modifiers="GDK_CONTROL_MASK" signal="activate"/>
+
+		      <child internal-child="image">
+			<widget class="GtkImage" id="image42">
+			  <property name="visible">True</property>
+			  <property name="stock">gtk-quit</property>
+			  <property name="icon_size">1</property>
+			  <property name="xalign">0.5</property>
+			  <property name="yalign">0.5</property>
+			  <property name="xpad">0</property>
+			  <property name="ypad">0</property>
+			</widget>
+		      </child>
+		    </widget>
+		  </child>
+		</widget>
+	      </child>
+	    </widget>
+	  </child>
+
+	  <child>
+	    <widget class="GtkMenuItem" id="options1">
+	      <property name="visible">True</property>
+	      <property name="label" translatable="yes">_Options</property>
+	      <property name="use_underline">True</property>
+
+	      <child>
+		<widget class="GtkMenu" id="options1_menu">
+
+		  <child>
+		    <widget class="GtkCheckMenuItem" id="show_name1">
+		      <property name="visible">True</property>
+		      <property name="tooltip" translatable="yes">Show name</property>
+		      <property name="label" translatable="yes">Show _name</property>
+		      <property name="use_underline">True</property>
+		      <property name="active">False</property>
+		      <signal name="activate" handler="on_show_name1_activate"/>
+		    </widget>
+		  </child>
+
+		  <child>
+		    <widget class="GtkCheckMenuItem" id="show_range1">
+		      <property name="visible">True</property>
+		      <property name="tooltip" translatable="yes">Show range (Y/M/N)</property>
+		      <property name="label" translatable="yes">Show _range</property>
+		      <property name="use_underline">True</property>
+		      <property name="active">False</property>
+		      <signal name="activate" handler="on_show_range1_activate"/>
+		    </widget>
+		  </child>
+
+		  <child>
+		    <widget class="GtkCheckMenuItem" id="show_data1">
+		      <property name="visible">True</property>
+		      <property name="tooltip" translatable="yes">Show value of the option</property>
+		      <property name="label" translatable="yes">Show _data</property>
+		      <property name="use_underline">True</property>
+		      <property name="active">False</property>
+		      <signal name="activate" handler="on_show_data1_activate"/>
+		    </widget>
+		  </child>
+
+		  <child>
+		    <widget class="GtkSeparatorMenuItem" id="separator2">
+		      <property name="visible">True</property>
+		    </widget>
+		  </child>
+
+		  <child>
+		    <widget class="GtkCheckMenuItem" id="show_all_options1">
+		      <property name="visible">True</property>
+		      <property name="tooltip" translatable="yes">Show all options</property>
+		      <property name="label" translatable="yes">Show all _options</property>
+		      <property name="use_underline">True</property>
+		      <property name="active">False</property>
+		      <signal name="activate" handler="on_show_all_options1_activate"/>
+		    </widget>
+		  </child>
+
+		  <child>
+		    <widget class="GtkCheckMenuItem" id="show_debug_info1">
+		      <property name="visible">True</property>
+		      <property name="tooltip" translatable="yes">Show masked options</property>
+		      <property name="label" translatable="yes">Show _debug info</property>
+		      <property name="use_underline">True</property>
+		      <property name="active">False</property>
+		      <signal name="activate" handler="on_show_debug_info1_activate"/>
+		    </widget>
+		  </child>
+		</widget>
+	      </child>
+	    </widget>
+	  </child>
+
+	  <child>
+	    <widget class="GtkMenuItem" id="help1">
+	      <property name="visible">True</property>
+	      <property name="label" translatable="yes">_Help</property>
+	      <property name="use_underline">True</property>
+
+	      <child>
+		<widget class="GtkMenu" id="help1_menu">
+
+		  <child>
+		    <widget class="GtkImageMenuItem" id="introduction1">
+		      <property name="visible">True</property>
+		      <property name="label" translatable="yes">_Introduction</property>
+		      <property name="use_underline">True</property>
+		      <signal name="activate" handler="on_introduction1_activate" last_modification_time="Fri, 15 Nov 2002 20:26:30 GMT"/>
+		      <accelerator key="I" modifiers="GDK_CONTROL_MASK" signal="activate"/>
+
+		      <child internal-child="image">
+			<widget class="GtkImage" id="image43">
+			  <property name="visible">True</property>
+			  <property name="stock">gtk-dialog-question</property>
+			  <property name="icon_size">1</property>
+			  <property name="xalign">0.5</property>
+			  <property name="yalign">0.5</property>
+			  <property name="xpad">0</property>
+			  <property name="ypad">0</property>
+			</widget>
+		      </child>
+		    </widget>
+		  </child>
+
+		  <child>
+		    <widget class="GtkImageMenuItem" id="about1">
+		      <property name="visible">True</property>
+		      <property name="label" translatable="yes">_About</property>
+		      <property name="use_underline">True</property>
+		      <signal name="activate" handler="on_about1_activate" last_modification_time="Fri, 15 Nov 2002 20:26:30 GMT"/>
+		      <accelerator key="A" modifiers="GDK_CONTROL_MASK" signal="activate"/>
+
+		      <child internal-child="image">
+			<widget class="GtkImage" id="image44">
+			  <property name="visible">True</property>
+			  <property name="stock">gtk-properties</property>
+			  <property name="icon_size">1</property>
+			  <property name="xalign">0.5</property>
+			  <property name="yalign">0.5</property>
+			  <property name="xpad">0</property>
+			  <property name="ypad">0</property>
+			</widget>
+		      </child>
+		    </widget>
+		  </child>
+
+		  <child>
+		    <widget class="GtkImageMenuItem" id="license1">
+		      <property name="visible">True</property>
+		      <property name="label" translatable="yes">_License</property>
+		      <property name="use_underline">True</property>
+		      <signal name="activate" handler="on_license1_activate" last_modification_time="Fri, 15 Nov 2002 20:26:30 GMT"/>
+
+		      <child internal-child="image">
+			<widget class="GtkImage" id="image45">
+			  <property name="visible">True</property>
+			  <property name="stock">gtk-justify-fill</property>
+			  <property name="icon_size">1</property>
+			  <property name="xalign">0.5</property>
+			  <property name="yalign">0.5</property>
+			  <property name="xpad">0</property>
+			  <property name="ypad">0</property>
+			</widget>
+		      </child>
+		    </widget>
+		  </child>
+		</widget>
+	      </child>
+	    </widget>
+	  </child>
+	</widget>
+	<packing>
+	  <property name="padding">0</property>
+	  <property name="expand">False</property>
+	  <property name="fill">False</property>
+	</packing>
+      </child>
+
+      <child>
+	<widget class="GtkHandleBox" id="handlebox1">
+	  <property name="visible">True</property>
+	  <property name="shadow_type">GTK_SHADOW_OUT</property>
+	  <property name="handle_position">GTK_POS_LEFT</property>
+	  <property name="snap_edge">GTK_POS_TOP</property>
+
+	  <child>
+	    <widget class="GtkToolbar" id="toolbar1">
+	      <property name="visible">True</property>
+	      <property name="orientation">GTK_ORIENTATION_HORIZONTAL</property>
+	      <property name="toolbar_style">GTK_TOOLBAR_BOTH</property>
+	      <property name="tooltips">True</property>
+	      <property name="show_arrow">True</property>
+
+	      <child>
+		<widget class="GtkToolButton" id="button1">
+		  <property name="visible">True</property>
+		  <property name="tooltip" translatable="yes">Goes up of one level (single view)</property>
+		  <property name="label" translatable="yes">Back</property>
+		  <property name="use_underline">True</property>
+		  <property name="stock_id">gtk-undo</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_back_clicked"/>
+		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
+	      </child>
+
+	      <child>
+		<widget class="GtkToolItem" id="toolitem1">
+		  <property name="visible">True</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+
+		  <child>
+		    <widget class="GtkVSeparator" id="vseparator1">
+		      <property name="visible">True</property>
+		    </widget>
+		  </child>
+		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">False</property>
+		</packing>
+	      </child>
+
+	      <child>
+		<widget class="GtkToolButton" id="button2">
+		  <property name="visible">True</property>
+		  <property name="tooltip" translatable="yes">Load a config file</property>
+		  <property name="label" translatable="yes">Load</property>
+		  <property name="use_underline">True</property>
+		  <property name="stock_id">gtk-open</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_load_clicked"/>
+		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
+	      </child>
+
+	      <child>
+		<widget class="GtkToolButton" id="button3">
+		  <property name="visible">True</property>
+		  <property name="tooltip" translatable="yes">Save a config file</property>
+		  <property name="label" translatable="yes">Save</property>
+		  <property name="use_underline">True</property>
+		  <property name="stock_id">gtk-save</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_save_activate"/>
+		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
+	      </child>
+
+	      <child>
+		<widget class="GtkToolItem" id="toolitem2">
+		  <property name="visible">True</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+
+		  <child>
+		    <widget class="GtkVSeparator" id="vseparator2">
+		      <property name="visible">True</property>
+		    </widget>
+		  </child>
+		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">False</property>
+		</packing>
+	      </child>
+
+	      <child>
+		<widget class="GtkToolButton" id="button4">
+		  <property name="visible">True</property>
+		  <property name="tooltip" translatable="yes">Single view</property>
+		  <property name="label" translatable="yes">Single</property>
+		  <property name="use_underline">True</property>
+		  <property name="stock_id">gtk-missing-image</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_single_clicked" last_modification_time="Sun, 12 Jan 2003 14:28:39 GMT"/>
+		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
+	      </child>
+
+	      <child>
+		<widget class="GtkToolButton" id="button5">
+		  <property name="visible">True</property>
+		  <property name="tooltip" translatable="yes">Split view</property>
+		  <property name="label" translatable="yes">Split</property>
+		  <property name="use_underline">True</property>
+		  <property name="stock_id">gtk-missing-image</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_split_clicked" last_modification_time="Sun, 12 Jan 2003 14:28:45 GMT"/>
+		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
+	      </child>
+
+	      <child>
+		<widget class="GtkToolButton" id="button6">
+		  <property name="visible">True</property>
+		  <property name="tooltip" translatable="yes">Full view</property>
+		  <property name="label" translatable="yes">Full</property>
+		  <property name="use_underline">True</property>
+		  <property name="stock_id">gtk-missing-image</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_full_clicked" last_modification_time="Sun, 12 Jan 2003 14:28:50 GMT"/>
+		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
+	      </child>
+
+	      <child>
+		<widget class="GtkToolItem" id="toolitem3">
+		  <property name="visible">True</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+
+		  <child>
+		    <widget class="GtkVSeparator" id="vseparator3">
+		      <property name="visible">True</property>
+		    </widget>
+		  </child>
+		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">False</property>
+		</packing>
+	      </child>
+
+	      <child>
+		<widget class="GtkToolButton" id="button7">
+		  <property name="visible">True</property>
+		  <property name="tooltip" translatable="yes">Collapse the whole tree in the right frame</property>
+		  <property name="label" translatable="yes">Collapse</property>
+		  <property name="use_underline">True</property>
+		  <property name="stock_id">gtk-remove</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_collapse_clicked"/>
+		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
+	      </child>
+
+	      <child>
+		<widget class="GtkToolButton" id="button8">
+		  <property name="visible">True</property>
+		  <property name="tooltip" translatable="yes">Expand the whole tree in the right frame</property>
+		  <property name="label" translatable="yes">Expand</property>
+		  <property name="use_underline">True</property>
+		  <property name="stock_id">gtk-add</property>
+		  <property name="visible_horizontal">True</property>
+		  <property name="visible_vertical">True</property>
+		  <property name="is_important">False</property>
+		  <signal name="clicked" handler="on_expand_clicked"/>
+		</widget>
+		<packing>
+		  <property name="expand">False</property>
+		  <property name="homogeneous">True</property>
+		</packing>
+	      </child>
+	    </widget>
+	  </child>
+	</widget>
+	<packing>
+	  <property name="padding">0</property>
+	  <property name="expand">False</property>
+	  <property name="fill">False</property>
+	</packing>
+      </child>
+
+      <child>
+	<widget class="GtkHPaned" id="hpaned1">
+	  <property name="width_request">1</property>
+	  <property name="visible">True</property>
+	  <property name="can_focus">True</property>
+	  <property name="position">0</property>
+
+	  <child>
+	    <widget class="GtkScrolledWindow" id="scrolledwindow1">
+	      <property name="visible">True</property>
+	      <property name="hscrollbar_policy">GTK_POLICY_AUTOMATIC</property>
+	      <property name="vscrollbar_policy">GTK_POLICY_AUTOMATIC</property>
+	      <property name="shadow_type">GTK_SHADOW_IN</property>
+	      <property name="window_placement">GTK_CORNER_TOP_LEFT</property>
+
+	      <child>
+		<widget class="GtkTreeView" id="treeview1">
+		  <property name="visible">True</property>
+		  <property name="can_focus">True</property>
+		  <property name="headers_visible">True</property>
+		  <property name="rules_hint">False</property>
+		  <property name="reorderable">False</property>
+		  <property name="enable_search">True</property>
+		  <signal name="cursor_changed" handler="on_treeview2_cursor_changed" last_modification_time="Sun, 12 Jan 2003 15:58:22 GMT"/>
+		  <signal name="button_press_event" handler="on_treeview1_button_press_event" last_modification_time="Sun, 12 Jan 2003 16:03:52 GMT"/>
+		  <signal name="key_press_event" handler="on_treeview2_key_press_event" last_modification_time="Sun, 12 Jan 2003 16:11:44 GMT"/>
+		</widget>
+	      </child>
+	    </widget>
+	    <packing>
+	      <property name="shrink">True</property>
+	      <property name="resize">False</property>
+	    </packing>
+	  </child>
+
+	  <child>
+	    <widget class="GtkVPaned" id="vpaned1">
+	      <property name="visible">True</property>
+	      <property name="can_focus">True</property>
+	      <property name="position">0</property>
+
+	      <child>
+		<widget class="GtkScrolledWindow" id="scrolledwindow2">
+		  <property name="visible">True</property>
+		  <property name="hscrollbar_policy">GTK_POLICY_AUTOMATIC</property>
+		  <property name="vscrollbar_policy">GTK_POLICY_AUTOMATIC</property>
+		  <property name="shadow_type">GTK_SHADOW_IN</property>
+		  <property name="window_placement">GTK_CORNER_TOP_LEFT</property>
+
+		  <child>
+		    <widget class="GtkTreeView" id="treeview2">
+		      <property name="visible">True</property>
+		      <property name="can_focus">True</property>
+		      <property name="has_focus">True</property>
+		      <property name="headers_visible">True</property>
+		      <property name="rules_hint">False</property>
+		      <property name="reorderable">False</property>
+		      <property name="enable_search">True</property>
+		      <signal name="cursor_changed" handler="on_treeview2_cursor_changed" last_modification_time="Sun, 12 Jan 2003 15:57:55 GMT"/>
+		      <signal name="button_press_event" handler="on_treeview2_button_press_event" last_modification_time="Sun, 12 Jan 2003 15:57:58 GMT"/>
+		      <signal name="key_press_event" handler="on_treeview2_key_press_event" last_modification_time="Sun, 12 Jan 2003 15:58:01 GMT"/>
+		    </widget>
+		  </child>
+		</widget>
+		<packing>
+		  <property name="shrink">True</property>
+		  <property name="resize">False</property>
+		</packing>
+	      </child>
+
+	      <child>
+		<widget class="GtkScrolledWindow" id="scrolledwindow3">
+		  <property name="visible">True</property>
+		  <property name="hscrollbar_policy">GTK_POLICY_NEVER</property>
+		  <property name="vscrollbar_policy">GTK_POLICY_AUTOMATIC</property>
+		  <property name="shadow_type">GTK_SHADOW_IN</property>
+		  <property name="window_placement">GTK_CORNER_TOP_LEFT</property>
+
+		  <child>
+		    <widget class="GtkTextView" id="textview3">
+		      <property name="visible">True</property>
+		      <property name="can_focus">True</property>
+		      <property name="editable">False</property>
+		      <property name="overwrite">False</property>
+		      <property name="accepts_tab">True</property>
+		      <property name="justification">GTK_JUSTIFY_LEFT</property>
+		      <property name="wrap_mode">GTK_WRAP_WORD</property>
+		      <property name="cursor_visible">True</property>
+		      <property name="pixels_above_lines">0</property>
+		      <property name="pixels_below_lines">0</property>
+		      <property name="pixels_inside_wrap">0</property>
+		      <property name="left_margin">0</property>
+		      <property name="right_margin">0</property>
+		      <property name="indent">0</property>
+		      <property name="text" translatable="yes">Sorry, no help available for this option yet.</property>
+		    </widget>
+		  </child>
+		</widget>
+		<packing>
+		  <property name="shrink">True</property>
+		  <property name="resize">True</property>
+		</packing>
+	      </child>
+	    </widget>
+	    <packing>
+	      <property name="shrink">True</property>
+	      <property name="resize">True</property>
+	    </packing>
+	  </child>
+	</widget>
+	<packing>
+	  <property name="padding">0</property>
+	  <property name="expand">True</property>
+	  <property name="fill">True</property>
+	</packing>
+      </child>
+    </widget>
+  </child>
+</widget>
+
+</glade-interface>

Added: trunk/coreboot-v2/util/kconfig/images.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/images.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/images.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,326 @@
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel at linux-m68k.org>
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+static const char *xpm_load[] = {
+"22 22 5 1",
+". c None",
+"# c #000000",
+"c c #838100",
+"a c #ffff00",
+"b c #ffffff",
+"......................",
+"......................",
+"......................",
+"............####....#.",
+"...........#....##.##.",
+"..................###.",
+".................####.",
+".####...........#####.",
+"#abab##########.......",
+"#babababababab#.......",
+"#ababababababa#.......",
+"#babababababab#.......",
+"#ababab###############",
+"#babab##cccccccccccc##",
+"#abab##cccccccccccc##.",
+"#bab##cccccccccccc##..",
+"#ab##cccccccccccc##...",
+"#b##cccccccccccc##....",
+"###cccccccccccc##.....",
+"##cccccccccccc##......",
+"###############.......",
+"......................"};
+
+static const char *xpm_save[] = {
+"22 22 5 1",
+". c None",
+"# c #000000",
+"a c #838100",
+"b c #c5c2c5",
+"c c #cdb6d5",
+"......................",
+".####################.",
+".#aa#bbbbbbbbbbbb#bb#.",
+".#aa#bbbbbbbbbbbb#bb#.",
+".#aa#bbbbbbbbbcbb####.",
+".#aa#bbbccbbbbbbb#aa#.",
+".#aa#bbbccbbbbbbb#aa#.",
+".#aa#bbbbbbbbbbbb#aa#.",
+".#aa#bbbbbbbbbbbb#aa#.",
+".#aa#bbbbbbbbbbbb#aa#.",
+".#aa#bbbbbbbbbbbb#aa#.",
+".#aaa############aaa#.",
+".#aaaaaaaaaaaaaaaaaa#.",
+".#aaaaaaaaaaaaaaaaaa#.",
+".#aaa#############aa#.",
+".#aaa#########bbb#aa#.",
+".#aaa#########bbb#aa#.",
+".#aaa#########bbb#aa#.",
+".#aaa#########bbb#aa#.",
+".#aaa#########bbb#aa#.",
+"..##################..",
+"......................"};
+
+static const char *xpm_back[] = {
+"22 22 3 1",
+". c None",
+"# c #000083",
+"a c #838183",
+"......................",
+"......................",
+"......................",
+"......................",
+"......................",
+"...........######a....",
+"..#......##########...",
+"..##...####......##a..",
+"..###.###.........##..",
+"..######..........##..",
+"..#####...........##..",
+"..######..........##..",
+"..#######.........##..",
+"..########.......##a..",
+"...............a###...",
+"...............###....",
+"......................",
+"......................",
+"......................",
+"......................",
+"......................",
+"......................"};
+
+static const char *xpm_tree_view[] = {
+"22 22 2 1",
+". c None",
+"# c #000000",
+"......................",
+"......................",
+"......#...............",
+"......#...............",
+"......#...............",
+"......#...............",
+"......#...............",
+"......########........",
+"......#...............",
+"......#...............",
+"......#...............",
+"......#...............",
+"......#...............",
+"......########........",
+"......#...............",
+"......#...............",
+"......#...............",
+"......#...............",
+"......#...............",
+"......########........",
+"......................",
+"......................"};
+
+static const char *xpm_single_view[] = {
+"22 22 2 1",
+". c None",
+"# c #000000",
+"......................",
+"......................",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"..........#...........",
+"......................",
+"......................"};
+
+static const char *xpm_split_view[] = {
+"22 22 2 1",
+". c None",
+"# c #000000",
+"......................",
+"......................",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......#......#........",
+"......................",
+"......................"};
+
+static const char *xpm_symbol_no[] = {
+"12 12 2 1",
+"  c white",
+". c black",
+"            ",
+" .......... ",
+" .        . ",
+" .        . ",
+" .        . ",
+" .        . ",
+" .        . ",
+" .        . ",
+" .        . ",
+" .        . ",
+" .......... ",
+"            "};
+
+static const char *xpm_symbol_mod[] = {
+"12 12 2 1",
+"  c white",
+". c black",
+"            ",
+" .......... ",
+" .        . ",
+" .        . ",
+" .   ..   . ",
+" .  ....  . ",
+" .  ....  . ",
+" .   ..   . ",
+" .        . ",
+" .        . ",
+" .......... ",
+"            "};
+
+static const char *xpm_symbol_yes[] = {
+"12 12 2 1",
+"  c white",
+". c black",
+"            ",
+" .......... ",
+" .        . ",
+" .        . ",
+" .      . . ",
+" .     .. . ",
+" . .  ..  . ",
+" . ....   . ",
+" .  ..    . ",
+" .        . ",
+" .......... ",
+"            "};
+
+static const char *xpm_choice_no[] = {
+"12 12 2 1",
+"  c white",
+". c black",
+"            ",
+"    ....    ",
+"  ..    ..  ",
+"  .      .  ",
+" .        . ",
+" .        . ",
+" .        . ",
+" .        . ",
+"  .      .  ",
+"  ..    ..  ",
+"    ....    ",
+"            "};
+
+static const char *xpm_choice_yes[] = {
+"12 12 2 1",
+"  c white",
+". c black",
+"            ",
+"    ....    ",
+"  ..    ..  ",
+"  .      .  ",
+" .   ..   . ",
+" .  ....  . ",
+" .  ....  . ",
+" .   ..   . ",
+"  .      .  ",
+"  ..    ..  ",
+"    ....    ",
+"            "};
+
+static const char *xpm_menu[] = {
+"12 12 2 1",
+"  c white",
+". c black",
+"            ",
+" .......... ",
+" .        . ",
+" . ..     . ",
+" . ....   . ",
+" . ...... . ",
+" . ...... . ",
+" . ....   . ",
+" . ..     . ",
+" .        . ",
+" .......... ",
+"            "};
+
+static const char *xpm_menu_inv[] = {
+"12 12 2 1",
+"  c white",
+". c black",
+"            ",
+" .......... ",
+" .......... ",
+" ..  ...... ",
+" ..    .... ",
+" ..      .. ",
+" ..      .. ",
+" ..    .... ",
+" ..  ...... ",
+" .......... ",
+" .......... ",
+"            "};
+
+static const char *xpm_menuback[] = {
+"12 12 2 1",
+"  c white",
+". c black",
+"            ",
+" .......... ",
+" .        . ",
+" .     .. . ",
+" .   .... . ",
+" . ...... . ",
+" . ...... . ",
+" .   .... . ",
+" .     .. . ",
+" .        . ",
+" .......... ",
+"            "};
+
+static const char *xpm_void[] = {
+"12 12 2 1",
+"  c white",
+". c black",
+"            ",
+"            ",
+"            ",
+"            ",
+"            ",
+"            ",
+"            ",
+"            ",
+"            ",
+"            ",
+"            ",
+"            "};

Added: trunk/coreboot-v2/util/kconfig/kconfig_load.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/kconfig_load.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/kconfig_load.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,35 @@
+#include <dlfcn.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "lkc.h"
+
+#define P(name,type,arg)	type (*name ## _p) arg
+#include "lkc_proto.h"
+#undef P
+
+void kconfig_load(void)
+{
+	void *handle;
+	char *error;
+
+	handle = dlopen("./libkconfig.so", RTLD_LAZY);
+	if (!handle) {
+		handle = dlopen("./util/kconfig/libkconfig.so", RTLD_LAZY);
+		if (!handle) {
+			fprintf(stderr, "%s\n", dlerror());
+			exit(1);
+		}
+	}
+
+#define P(name,type,arg)			\
+{						\
+	name ## _p = dlsym(handle, #name);	\
+        if ((error = dlerror()))  {		\
+                fprintf(stderr, "%s\n", error);	\
+		exit(1);			\
+	}					\
+}
+#include "lkc_proto.h"
+#undef P
+}

Added: trunk/coreboot-v2/util/kconfig/kxgettext.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/kxgettext.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/kxgettext.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,229 @@
+/*
+ * Arnaldo Carvalho de Melo <acme at conectiva.com.br>, 2005
+ *
+ * Released under the terms of the GNU GPL v2.0
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+#define LKC_DIRECT_LINK
+#include "lkc.h"
+
+static char *escape(const char* text, char *bf, int len)
+{
+	char *bfp = bf;
+	int multiline = strchr(text, '\n') != NULL;
+	int eol = 0;
+	int textlen = strlen(text);
+
+	if ((textlen > 0) && (text[textlen-1] == '\n'))
+		eol = 1;
+
+	*bfp++ = '"';
+	--len;
+
+	if (multiline) {
+		*bfp++ = '"';
+		*bfp++ = '\n';
+		*bfp++ = '"';
+		len -= 3;
+	}
+
+	while (*text != '\0' && len > 1) {
+		if (*text == '"')
+			*bfp++ = '\\';
+		else if (*text == '\n') {
+			*bfp++ = '\\';
+			*bfp++ = 'n';
+			*bfp++ = '"';
+			*bfp++ = '\n';
+			*bfp++ = '"';
+			len -= 5;
+			++text;
+			goto next;
+		}
+		*bfp++ = *text++;
+next:
+		--len;
+	}
+
+	if (multiline && eol)
+		bfp -= 3;
+
+	*bfp++ = '"';
+	*bfp = '\0';
+
+	return bf;
+}
+
+struct file_line {
+	struct file_line *next;
+	char*		 file;
+	int		 lineno;
+};
+
+static struct file_line *file_line__new(char *file, int lineno)
+{
+	struct file_line *self = malloc(sizeof(*self));
+
+	if (self == NULL)
+		goto out;
+
+	self->file   = file;
+	self->lineno = lineno;
+	self->next   = NULL;
+out:
+	return self;
+}
+
+struct message {
+	const char	 *msg;
+	const char	 *option;
+	struct message	 *next;
+	struct file_line *files;
+};
+
+static struct message *message__list;
+
+static struct message *message__new(const char *msg, char *option, char *file, int lineno)
+{
+	struct message *self = malloc(sizeof(*self));
+
+	if (self == NULL)
+		goto out;
+
+	self->files = file_line__new(file, lineno);
+	if (self->files == NULL)
+		goto out_fail;
+
+	self->msg = strdup(msg);
+	if (self->msg == NULL)
+		goto out_fail_msg;
+
+	self->option = option;
+	self->next = NULL;
+out:
+	return self;
+out_fail_msg:
+	free(self->files);
+out_fail:
+	free(self);
+	self = NULL;
+	goto out;
+}
+
+static struct message *mesage__find(const char *msg)
+{
+	struct message *m = message__list;
+
+	while (m != NULL) {
+		if (strcmp(m->msg, msg) == 0)
+			break;
+		m = m->next;
+	}
+
+	return m;
+}
+
+static int message__add_file_line(struct message *self, char *file, int lineno)
+{
+	int rc = -1;
+	struct file_line *fl = file_line__new(file, lineno);
+
+	if (fl == NULL)
+		goto out;
+
+	fl->next    = self->files;
+	self->files = fl;
+	rc = 0;
+out:
+	return rc;
+}
+
+static int message__add(const char *msg, char *option, char *file, int lineno)
+{
+	int rc = 0;
+	char bf[16384];
+	char *escaped = escape(msg, bf, sizeof(bf));
+	struct message *m = mesage__find(escaped);
+
+	if (m != NULL)
+		rc = message__add_file_line(m, file, lineno);
+	else {
+		m = message__new(escaped, option, file, lineno);
+
+		if (m != NULL) {
+			m->next	      = message__list;
+			message__list = m;
+		} else
+			rc = -1;
+	}
+	return rc;
+}
+
+void menu_build_message_list(struct menu *menu)
+{
+	struct menu *child;
+
+	message__add(menu_get_prompt(menu), NULL,
+		     menu->file == NULL ? "Root Menu" : menu->file->name,
+		     menu->lineno);
+
+	if (menu->sym != NULL && menu_has_help(menu))
+		message__add(menu_get_help(menu), menu->sym->name,
+			     menu->file == NULL ? "Root Menu" : menu->file->name,
+			     menu->lineno);
+
+	for (child = menu->list; child != NULL; child = child->next)
+		if (child->prompt != NULL)
+			menu_build_message_list(child);
+}
+
+static void message__print_file_lineno(struct message *self)
+{
+	struct file_line *fl = self->files;
+
+	putchar('\n');
+	if (self->option != NULL)
+		printf("# %s:00000\n", self->option);
+
+	printf("#: %s:%d", fl->file, fl->lineno);
+	fl = fl->next;
+
+	while (fl != NULL) {
+		printf(", %s:%d", fl->file, fl->lineno);
+		fl = fl->next;
+	}
+
+	putchar('\n');
+}
+
+static void message__print_gettext_msgid_msgstr(struct message *self)
+{
+	message__print_file_lineno(self);
+
+	printf("msgid %s\n"
+	       "msgstr \"\"\n", self->msg);
+}
+
+void menu__xgettext(void)
+{
+	struct message *m = message__list;
+
+	while (m != NULL) {
+		/* skip empty lines ("") */
+		if (strlen(m->msg) > sizeof("\"\""))
+			message__print_gettext_msgid_msgstr(m);
+		m = m->next;
+	}
+}
+
+int main(int ac, char **av)
+{
+	conf_parse(av[1]);
+
+	menu_build_message_list(menu_get_root_menu(NULL));
+	menu__xgettext();
+	return 0;
+}

Added: trunk/coreboot-v2/util/kconfig/lex.zconf.c_shipped
===================================================================
--- trunk/coreboot-v2/util/kconfig/lex.zconf.c_shipped	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/lex.zconf.c_shipped	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,2374 @@
+
+#line 3 "util/kconfig/lex.zconf.c"
+
+#define  YY_INT_ALIGNED short int
+
+/* A lexical scanner generated by flex */
+
+#define yy_create_buffer zconf_create_buffer
+#define yy_delete_buffer zconf_delete_buffer
+#define yy_flex_debug zconf_flex_debug
+#define yy_init_buffer zconf_init_buffer
+#define yy_flush_buffer zconf_flush_buffer
+#define yy_load_buffer_state zconf_load_buffer_state
+#define yy_switch_to_buffer zconf_switch_to_buffer
+#define yyin zconfin
+#define yyleng zconfleng
+#define yylex zconflex
+#define yylineno zconflineno
+#define yyout zconfout
+#define yyrestart zconfrestart
+#define yytext zconftext
+#define yywrap zconfwrap
+#define yyalloc zconfalloc
+#define yyrealloc zconfrealloc
+#define yyfree zconffree
+
+#define FLEX_SCANNER
+#define YY_FLEX_MAJOR_VERSION 2
+#define YY_FLEX_MINOR_VERSION 5
+#define YY_FLEX_SUBMINOR_VERSION 33
+#if YY_FLEX_SUBMINOR_VERSION > 0
+#define FLEX_BETA
+#endif
+
+/* First, we deal with  platform-specific or compiler-specific issues. */
+
+/* begin standard C headers. */
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <stdlib.h>
+
+/* end standard C headers. */
+
+/* flex integer type definitions */
+
+#ifndef FLEXINT_H
+#define FLEXINT_H
+
+/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
+
+#if __STDC_VERSION__ >= 199901L
+
+/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
+ * if you want the limit (max/min) macros for int types. 
+ */
+#ifndef __STDC_LIMIT_MACROS
+#define __STDC_LIMIT_MACROS 1
+#endif
+
+#include <inttypes.h>
+typedef int8_t flex_int8_t;
+typedef uint8_t flex_uint8_t;
+typedef int16_t flex_int16_t;
+typedef uint16_t flex_uint16_t;
+typedef int32_t flex_int32_t;
+typedef uint32_t flex_uint32_t;
+#else
+typedef signed char flex_int8_t;
+typedef short int flex_int16_t;
+typedef int flex_int32_t;
+typedef unsigned char flex_uint8_t; 
+typedef unsigned short int flex_uint16_t;
+typedef unsigned int flex_uint32_t;
+#endif /* ! C99 */
+
+/* Limits of integral types. */
+#ifndef INT8_MIN
+#define INT8_MIN               (-128)
+#endif
+#ifndef INT16_MIN
+#define INT16_MIN              (-32767-1)
+#endif
+#ifndef INT32_MIN
+#define INT32_MIN              (-2147483647-1)
+#endif
+#ifndef INT8_MAX
+#define INT8_MAX               (127)
+#endif
+#ifndef INT16_MAX
+#define INT16_MAX              (32767)
+#endif
+#ifndef INT32_MAX
+#define INT32_MAX              (2147483647)
+#endif
+#ifndef UINT8_MAX
+#define UINT8_MAX              (255U)
+#endif
+#ifndef UINT16_MAX
+#define UINT16_MAX             (65535U)
+#endif
+#ifndef UINT32_MAX
+#define UINT32_MAX             (4294967295U)
+#endif
+
+#endif /* ! FLEXINT_H */
+
+#ifdef __cplusplus
+
+/* The "const" storage-class-modifier is valid. */
+#define YY_USE_CONST
+
+#else	/* ! __cplusplus */
+
+#if __STDC__
+
+#define YY_USE_CONST
+
+#endif	/* __STDC__ */
+#endif	/* ! __cplusplus */
+
+#ifdef YY_USE_CONST
+#define yyconst const
+#else
+#define yyconst
+#endif
+
+/* Returned upon end-of-file. */
+#define YY_NULL 0
+
+/* Promotes a possibly negative, possibly signed char to an unsigned
+ * integer for use as an array index.  If the signed char is negative,
+ * we want to instead treat it as an 8-bit unsigned char, hence the
+ * double cast.
+ */
+#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
+
+/* Enter a start condition.  This macro really ought to take a parameter,
+ * but we do it the disgusting crufty way forced on us by the ()-less
+ * definition of BEGIN.
+ */
+#define BEGIN (yy_start) = 1 + 2 *
+
+/* Translate the current start state into a value that can be later handed
+ * to BEGIN to return to the state.  The YYSTATE alias is for lex
+ * compatibility.
+ */
+#define YY_START (((yy_start) - 1) / 2)
+#define YYSTATE YY_START
+
+/* Action number for EOF rule of a given start state. */
+#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
+
+/* Special action meaning "start processing a new file". */
+#define YY_NEW_FILE zconfrestart(zconfin  )
+
+#define YY_END_OF_BUFFER_CHAR 0
+
+/* Size of default input buffer. */
+#ifndef YY_BUF_SIZE
+#define YY_BUF_SIZE 16384
+#endif
+
+/* The state buf must be large enough to hold one state per character in the main buffer.
+ */
+#define YY_STATE_BUF_SIZE   ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
+
+#ifndef YY_TYPEDEF_YY_BUFFER_STATE
+#define YY_TYPEDEF_YY_BUFFER_STATE
+typedef struct yy_buffer_state *YY_BUFFER_STATE;
+#endif
+
+extern int zconfleng;
+
+extern FILE *zconfin, *zconfout;
+
+#define EOB_ACT_CONTINUE_SCAN 0
+#define EOB_ACT_END_OF_FILE 1
+#define EOB_ACT_LAST_MATCH 2
+
+    #define YY_LESS_LINENO(n)
+    
+/* Return all but the first "n" matched characters back to the input stream. */
+#define yyless(n) \
+	do \
+		{ \
+		/* Undo effects of setting up zconftext. */ \
+        int yyless_macro_arg = (n); \
+        YY_LESS_LINENO(yyless_macro_arg);\
+		*yy_cp = (yy_hold_char); \
+		YY_RESTORE_YY_MORE_OFFSET \
+		(yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \
+		YY_DO_BEFORE_ACTION; /* set up zconftext again */ \
+		} \
+	while ( 0 )
+
+#define unput(c) yyunput( c, (yytext_ptr)  )
+
+/* The following is because we cannot portably get our hands on size_t
+ * (without autoconf's help, which isn't available because we want
+ * flex-generated scanners to compile on their own).
+ */
+
+#ifndef YY_TYPEDEF_YY_SIZE_T
+#define YY_TYPEDEF_YY_SIZE_T
+typedef unsigned int yy_size_t;
+#endif
+
+#ifndef YY_STRUCT_YY_BUFFER_STATE
+#define YY_STRUCT_YY_BUFFER_STATE
+struct yy_buffer_state
+	{
+	FILE *yy_input_file;
+
+	char *yy_ch_buf;		/* input buffer */
+	char *yy_buf_pos;		/* current position in input buffer */
+
+	/* Size of input buffer in bytes, not including room for EOB
+	 * characters.
+	 */
+	yy_size_t yy_buf_size;
+
+	/* Number of characters read into yy_ch_buf, not including EOB
+	 * characters.
+	 */
+	int yy_n_chars;
+
+	/* Whether we "own" the buffer - i.e., we know we created it,
+	 * and can realloc() it to grow it, and should free() it to
+	 * delete it.
+	 */
+	int yy_is_our_buffer;
+
+	/* Whether this is an "interactive" input source; if so, and
+	 * if we're using stdio for input, then we want to use getc()
+	 * instead of fread(), to make sure we stop fetching input after
+	 * each newline.
+	 */
+	int yy_is_interactive;
+
+	/* Whether we're considered to be at the beginning of a line.
+	 * If so, '^' rules will be active on the next match, otherwise
+	 * not.
+	 */
+	int yy_at_bol;
+
+    int yy_bs_lineno; /**< The line count. */
+    int yy_bs_column; /**< The column count. */
+    
+	/* Whether to try to fill the input buffer when we reach the
+	 * end of it.
+	 */
+	int yy_fill_buffer;
+
+	int yy_buffer_status;
+
+#define YY_BUFFER_NEW 0
+#define YY_BUFFER_NORMAL 1
+	/* When an EOF's been seen but there's still some text to process
+	 * then we mark the buffer as YY_EOF_PENDING, to indicate that we
+	 * shouldn't try reading from the input source any more.  We might
+	 * still have a bunch of tokens to match, though, because of
+	 * possible backing-up.
+	 *
+	 * When we actually see the EOF, we change the status to "new"
+	 * (via zconfrestart()), so that the user can continue scanning by
+	 * just pointing zconfin at a new input file.
+	 */
+#define YY_BUFFER_EOF_PENDING 2
+
+	};
+#endif /* !YY_STRUCT_YY_BUFFER_STATE */
+
+/* Stack of input buffers. */
+static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */
+static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */
+static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */
+
+/* We provide macros for accessing buffer states in case in the
+ * future we want to put the buffer states in a more general
+ * "scanner state".
+ *
+ * Returns the top of the stack, or NULL.
+ */
+#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
+                          ? (yy_buffer_stack)[(yy_buffer_stack_top)] \
+                          : NULL)
+
+/* Same as previous macro, but useful when we know that the buffer stack is not
+ * NULL or when we need an lvalue. For internal use only.
+ */
+#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]
+
+/* yy_hold_char holds the character lost when zconftext is formed. */
+static char yy_hold_char;
+static int yy_n_chars;		/* number of characters read into yy_ch_buf */
+int zconfleng;
+
+/* Points to current character in buffer. */
+static char *yy_c_buf_p = (char *) 0;
+static int yy_init = 0;		/* whether we need to initialize */
+static int yy_start = 0;	/* start state number */
+
+/* Flag which is used to allow zconfwrap()'s to do buffer switches
+ * instead of setting up a fresh zconfin.  A bit of a hack ...
+ */
+static int yy_did_buffer_switch_on_eof;
+
+void zconfrestart (FILE *input_file  );
+void zconf_switch_to_buffer (YY_BUFFER_STATE new_buffer  );
+YY_BUFFER_STATE zconf_create_buffer (FILE *file,int size  );
+void zconf_delete_buffer (YY_BUFFER_STATE b  );
+void zconf_flush_buffer (YY_BUFFER_STATE b  );
+void zconfpush_buffer_state (YY_BUFFER_STATE new_buffer  );
+void zconfpop_buffer_state (void );
+
+static void zconfensure_buffer_stack (void );
+static void zconf_load_buffer_state (void );
+static void zconf_init_buffer (YY_BUFFER_STATE b,FILE *file  );
+
+#define YY_FLUSH_BUFFER zconf_flush_buffer(YY_CURRENT_BUFFER )
+
+YY_BUFFER_STATE zconf_scan_buffer (char *base,yy_size_t size  );
+YY_BUFFER_STATE zconf_scan_string (yyconst char *yy_str  );
+YY_BUFFER_STATE zconf_scan_bytes (yyconst char *bytes,int len  );
+
+void *zconfalloc (yy_size_t  );
+void *zconfrealloc (void *,yy_size_t  );
+void zconffree (void *  );
+
+#define yy_new_buffer zconf_create_buffer
+
+#define yy_set_interactive(is_interactive) \
+	{ \
+	if ( ! YY_CURRENT_BUFFER ){ \
+        zconfensure_buffer_stack (); \
+		YY_CURRENT_BUFFER_LVALUE =    \
+            zconf_create_buffer(zconfin,YY_BUF_SIZE ); \
+	} \
+	YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
+	}
+
+#define yy_set_bol(at_bol) \
+	{ \
+	if ( ! YY_CURRENT_BUFFER ){\
+        zconfensure_buffer_stack (); \
+		YY_CURRENT_BUFFER_LVALUE =    \
+            zconf_create_buffer(zconfin,YY_BUF_SIZE ); \
+	} \
+	YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
+	}
+
+#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
+
+/* Begin user sect3 */
+
+#define zconfwrap(n) 1
+#define YY_SKIP_YYWRAP
+
+typedef unsigned char YY_CHAR;
+
+FILE *zconfin = (FILE *) 0, *zconfout = (FILE *) 0;
+
+typedef int yy_state_type;
+
+extern int zconflineno;
+
+int zconflineno = 1;
+
+extern char *zconftext;
+#define yytext_ptr zconftext
+static yyconst flex_int16_t yy_nxt[][17] =
+    {
+    {
+        0,    0,    0,    0,    0,    0,    0,    0,    0,    0,
+        0,    0,    0,    0,    0,    0,    0
+    },
+
+    {
+       11,   12,   13,   14,   12,   12,   15,   12,   12,   12,
+       12,   12,   12,   12,   12,   12,   12
+    },
+
+    {
+       11,   12,   13,   14,   12,   12,   15,   12,   12,   12,
+       12,   12,   12,   12,   12,   12,   12
+    },
+
+    {
+       11,   16,   16,   17,   16,   16,   16,   16,   16,   16,
+       16,   16,   16,   18,   16,   16,   16
+    },
+
+    {
+       11,   16,   16,   17,   16,   16,   16,   16,   16,   16,
+       16,   16,   16,   18,   16,   16,   16
+
+    },
+
+    {
+       11,   19,   20,   21,   19,   19,   19,   19,   19,   19,
+       19,   19,   19,   19,   19,   19,   19
+    },
+
+    {
+       11,   19,   20,   21,   19,   19,   19,   19,   19,   19,
+       19,   19,   19,   19,   19,   19,   19
+    },
+
+    {
+       11,   22,   22,   23,   22,   24,   22,   22,   24,   22,
+       22,   22,   22,   22,   22,   25,   22
+    },
+
+    {
+       11,   22,   22,   23,   22,   24,   22,   22,   24,   22,
+       22,   22,   22,   22,   22,   25,   22
+    },
+
+    {
+       11,   26,   26,   27,   28,   29,   30,   31,   29,   32,
+       33,   34,   35,   35,   36,   37,   38
+
+    },
+
+    {
+       11,   26,   26,   27,   28,   29,   30,   31,   29,   32,
+       33,   34,   35,   35,   36,   37,   38
+    },
+
+    {
+      -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,  -11,
+      -11,  -11,  -11,  -11,  -11,  -11,  -11
+    },
+
+    {
+       11,  -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,  -12,
+      -12,  -12,  -12,  -12,  -12,  -12,  -12
+    },
+
+    {
+       11,  -13,   39,   40,  -13,  -13,   41,  -13,  -13,  -13,
+      -13,  -13,  -13,  -13,  -13,  -13,  -13
+    },
+
+    {
+       11,  -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,  -14,
+      -14,  -14,  -14,  -14,  -14,  -14,  -14
+
+    },
+
+    {
+       11,   42,   42,   43,   42,   42,   42,   42,   42,   42,
+       42,   42,   42,   42,   42,   42,   42
+    },
+
+    {
+       11,  -16,  -16,  -16,  -16,  -16,  -16,  -16,  -16,  -16,
+      -16,  -16,  -16,  -16,  -16,  -16,  -16
+    },
+
+    {
+       11,  -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,  -17,
+      -17,  -17,  -17,  -17,  -17,  -17,  -17
+    },
+
+    {
+       11,  -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,  -18,
+      -18,  -18,  -18,   44,  -18,  -18,  -18
+    },
+
+    {
+       11,   45,   45,  -19,   45,   45,   45,   45,   45,   45,
+       45,   45,   45,   45,   45,   45,   45
+
+    },
+
+    {
+       11,  -20,   46,   47,  -20,  -20,  -20,  -20,  -20,  -20,
+      -20,  -20,  -20,  -20,  -20,  -20,  -20
+    },
+
+    {
+       11,   48,  -21,  -21,   48,   48,   48,   48,   48,   48,
+       48,   48,   48,   48,   48,   48,   48
+    },
+
+    {
+       11,   49,   49,   50,   49,  -22,   49,   49,  -22,   49,
+       49,   49,   49,   49,   49,  -22,   49
+    },
+
+    {
+       11,  -23,  -23,  -23,  -23,  -23,  -23,  -23,  -23,  -23,
+      -23,  -23,  -23,  -23,  -23,  -23,  -23
+    },
+
+    {
+       11,  -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,  -24,
+      -24,  -24,  -24,  -24,  -24,  -24,  -24
+
+    },
+
+    {
+       11,   51,   51,   52,   51,   51,   51,   51,   51,   51,
+       51,   51,   51,   51,   51,   51,   51
+    },
+
+    {
+       11,  -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,  -26,
+      -26,  -26,  -26,  -26,  -26,  -26,  -26
+    },
+
+    {
+       11,  -27,  -27,  -27,  -27,  -27,  -27,  -27,  -27,  -27,
+      -27,  -27,  -27,  -27,  -27,  -27,  -27
+    },
+
+    {
+       11,  -28,  -28,  -28,  -28,  -28,  -28,  -28,  -28,  -28,
+      -28,  -28,  -28,  -28,   53,  -28,  -28
+    },
+
+    {
+       11,  -29,  -29,  -29,  -29,  -29,  -29,  -29,  -29,  -29,
+      -29,  -29,  -29,  -29,  -29,  -29,  -29
+
+    },
+
+    {
+       11,   54,   54,  -30,   54,   54,   54,   54,   54,   54,
+       54,   54,   54,   54,   54,   54,   54
+    },
+
+    {
+       11,  -31,  -31,  -31,  -31,  -31,  -31,   55,  -31,  -31,
+      -31,  -31,  -31,  -31,  -31,  -31,  -31
+    },
+
+    {
+       11,  -32,  -32,  -32,  -32,  -32,  -32,  -32,  -32,  -32,
+      -32,  -32,  -32,  -32,  -32,  -32,  -32
+    },
+
+    {
+       11,  -33,  -33,  -33,  -33,  -33,  -33,  -33,  -33,  -33,
+      -33,  -33,  -33,  -33,  -33,  -33,  -33
+    },
+
+    {
+       11,  -34,  -34,  -34,  -34,  -34,  -34,  -34,  -34,  -34,
+      -34,   56,   57,   57,  -34,  -34,  -34
+
+    },
+
+    {
+       11,  -35,  -35,  -35,  -35,  -35,  -35,  -35,  -35,  -35,
+      -35,   57,   57,   57,  -35,  -35,  -35
+    },
+
+    {
+       11,  -36,  -36,  -36,  -36,  -36,  -36,  -36,  -36,  -36,
+      -36,  -36,  -36,  -36,  -36,  -36,  -36
+    },
+
+    {
+       11,  -37,  -37,   58,  -37,  -37,  -37,  -37,  -37,  -37,
+      -37,  -37,  -37,  -37,  -37,  -37,  -37
+    },
+
+    {
+       11,  -38,  -38,  -38,  -38,  -38,  -38,  -38,  -38,  -38,
+      -38,  -38,  -38,  -38,  -38,  -38,   59
+    },
+
+    {
+       11,  -39,   39,   40,  -39,  -39,   41,  -39,  -39,  -39,
+      -39,  -39,  -39,  -39,  -39,  -39,  -39
+
+    },
+
+    {
+       11,  -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,  -40,
+      -40,  -40,  -40,  -40,  -40,  -40,  -40
+    },
+
+    {
+       11,   42,   42,   43,   42,   42,   42,   42,   42,   42,
+       42,   42,   42,   42,   42,   42,   42
+    },
+
+    {
+       11,   42,   42,   43,   42,   42,   42,   42,   42,   42,
+       42,   42,   42,   42,   42,   42,   42
+    },
+
+    {
+       11,  -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,  -43,
+      -43,  -43,  -43,  -43,  -43,  -43,  -43
+    },
+
+    {
+       11,  -44,  -44,  -44,  -44,  -44,  -44,  -44,  -44,  -44,
+      -44,  -44,  -44,   44,  -44,  -44,  -44
+
+    },
+
+    {
+       11,   45,   45,  -45,   45,   45,   45,   45,   45,   45,
+       45,   45,   45,   45,   45,   45,   45
+    },
+
+    {
+       11,  -46,   46,   47,  -46,  -46,  -46,  -46,  -46,  -46,
+      -46,  -46,  -46,  -46,  -46,  -46,  -46
+    },
+
+    {
+       11,   48,  -47,  -47,   48,   48,   48,   48,   48,   48,
+       48,   48,   48,   48,   48,   48,   48
+    },
+
+    {
+       11,  -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,  -48,
+      -48,  -48,  -48,  -48,  -48,  -48,  -48
+    },
+
+    {
+       11,   49,   49,   50,   49,  -49,   49,   49,  -49,   49,
+       49,   49,   49,   49,   49,  -49,   49
+
+    },
+
+    {
+       11,  -50,  -50,  -50,  -50,  -50,  -50,  -50,  -50,  -50,
+      -50,  -50,  -50,  -50,  -50,  -50,  -50
+    },
+
+    {
+       11,  -51,  -51,   52,  -51,  -51,  -51,  -51,  -51,  -51,
+      -51,  -51,  -51,  -51,  -51,  -51,  -51
+    },
+
+    {
+       11,  -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,  -52,
+      -52,  -52,  -52,  -52,  -52,  -52,  -52
+    },
+
+    {
+       11,  -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,  -53,
+      -53,  -53,  -53,  -53,  -53,  -53,  -53
+    },
+
+    {
+       11,   54,   54,  -54,   54,   54,   54,   54,   54,   54,
+       54,   54,   54,   54,   54,   54,   54
+
+    },
+
+    {
+       11,  -55,  -55,  -55,  -55,  -55,  -55,  -55,  -55,  -55,
+      -55,  -55,  -55,  -55,  -55,  -55,  -55
+    },
+
+    {
+       11,  -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,  -56,
+      -56,   60,   57,   57,  -56,  -56,  -56
+    },
+
+    {
+       11,  -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,  -57,
+      -57,   57,   57,   57,  -57,  -57,  -57
+    },
+
+    {
+       11,  -58,  -58,  -58,  -58,  -58,  -58,  -58,  -58,  -58,
+      -58,  -58,  -58,  -58,  -58,  -58,  -58
+    },
+
+    {
+       11,  -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,  -59,
+      -59,  -59,  -59,  -59,  -59,  -59,  -59
+
+    },
+
+    {
+       11,  -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,  -60,
+      -60,   57,   57,   57,  -60,  -60,  -60
+    },
+
+    } ;
+
+static yy_state_type yy_get_previous_state (void );
+static yy_state_type yy_try_NUL_trans (yy_state_type current_state  );
+static int yy_get_next_buffer (void );
+static void yy_fatal_error (yyconst char msg[]  );
+
+/* Done after the current pattern has been matched and before the
+ * corresponding action - sets up zconftext.
+ */
+#define YY_DO_BEFORE_ACTION \
+	(yytext_ptr) = yy_bp; \
+	zconfleng = (size_t) (yy_cp - yy_bp); \
+	(yy_hold_char) = *yy_cp; \
+	*yy_cp = '\0'; \
+	(yy_c_buf_p) = yy_cp;
+
+#define YY_NUM_RULES 33
+#define YY_END_OF_BUFFER 34
+/* This struct is not used in this scanner,
+   but its presence is necessary. */
+struct yy_trans_info
+	{
+	flex_int32_t yy_verify;
+	flex_int32_t yy_nxt;
+	};
+static yyconst flex_int16_t yy_accept[61] =
+    {   0,
+        0,    0,    0,    0,    0,    0,    0,    0,    0,    0,
+       34,    5,    4,    2,    3,    7,    8,    6,   32,   29,
+       31,   24,   28,   27,   26,   22,   17,   13,   16,   20,
+       22,   11,   12,   19,   19,   14,   22,   22,    4,    2,
+        3,    3,    1,    6,   32,   29,   31,   30,   24,   23,
+       26,   25,   15,   20,    9,   19,   19,   21,   10,   18
+    } ;
+
+static yyconst flex_int32_t yy_ec[256] =
+    {   0,
+        1,    1,    1,    1,    1,    1,    1,    1,    2,    3,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    2,    4,    5,    6,    1,    1,    7,    8,    9,
+       10,    1,    1,    1,   11,   12,   12,   13,   13,   13,
+       13,   13,   13,   13,   13,   13,   13,    1,    1,    1,
+       14,    1,    1,    1,   13,   13,   13,   13,   13,   13,
+       13,   13,   13,   13,   13,   13,   13,   13,   13,   13,
+       13,   13,   13,   13,   13,   13,   13,   13,   13,   13,
+        1,   15,    1,    1,   13,    1,   13,   13,   13,   13,
+
+       13,   13,   13,   13,   13,   13,   13,   13,   13,   13,
+       13,   13,   13,   13,   13,   13,   13,   13,   13,   13,
+       13,   13,    1,   16,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1,    1,    1,    1,    1,    1,
+        1,    1,    1,    1,    1
+    } ;
+
+extern int zconf_flex_debug;
+int zconf_flex_debug = 0;
+
+/* The intent behind this definition is that it'll catch
+ * any uses of REJECT which flex missed.
+ */
+#define REJECT reject_used_but_not_detected
+#define yymore() yymore_used_but_not_detected
+#define YY_MORE_ADJ 0
+#define YY_RESTORE_YY_MORE_OFFSET
+char *zconftext;
+
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel at linux-m68k.org>
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#include <limits.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#define LKC_DIRECT_LINK
+#include "lkc.h"
+
+#define START_STRSIZE	16
+
+static struct {
+	struct file *file;
+	int lineno;
+} current_pos;
+
+static char *text;
+static int text_size, text_asize;
+
+struct buffer {
+        struct buffer *parent;
+        YY_BUFFER_STATE state;
+};
+
+struct buffer *current_buf;
+
+static int last_ts, first_ts;
+
+static void zconf_endhelp(void);
+static void zconf_endfile(void);
+
+void new_string(void)
+{
+	text = malloc(START_STRSIZE);
+	text_asize = START_STRSIZE;
+	text_size = 0;
+	*text = 0;
+}
+
+void append_string(const char *str, int size)
+{
+	int new_size = text_size + size + 1;
+	if (new_size > text_asize) {
+		new_size += START_STRSIZE - 1;
+		new_size &= -START_STRSIZE;
+		text = realloc(text, new_size);
+		text_asize = new_size;
+	}
+	memcpy(text + text_size, str, size);
+	text_size += size;
+	text[text_size] = 0;
+}
+
+void alloc_string(const char *str, int size)
+{
+	text = malloc(size + 1);
+	memcpy(text, str, size);
+	text[size] = 0;
+}
+
+#define INITIAL 0
+#define COMMAND 1
+#define HELP 2
+#define STRING 3
+#define PARAM 4
+
+#ifndef YY_NO_UNISTD_H
+/* Special case for "unistd.h", since it is non-ANSI. We include it way
+ * down here because we want the user's section 1 to have been scanned first.
+ * The user has a chance to override it with an option.
+ */
+#include <unistd.h>
+#endif
+
+#ifndef YY_EXTRA_TYPE
+#define YY_EXTRA_TYPE void *
+#endif
+
+static int yy_init_globals (void );
+
+/* Macros after this point can all be overridden by user definitions in
+ * section 1.
+ */
+
+#ifndef YY_SKIP_YYWRAP
+#ifdef __cplusplus
+extern "C" int zconfwrap (void );
+#else
+extern int zconfwrap (void );
+#endif
+#endif
+
+    static void yyunput (int c,char *buf_ptr  );
+    
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char *,yyconst char *,int );
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * );
+#endif
+
+#ifndef YY_NO_INPUT
+
+#ifdef __cplusplus
+static int yyinput (void );
+#else
+static int input (void );
+#endif
+
+#endif
+
+/* Amount of stuff to slurp up with each read. */
+#ifndef YY_READ_BUF_SIZE
+#define YY_READ_BUF_SIZE 8192
+#endif
+
+/* Copy whatever the last rule matched to the standard output. */
+#ifndef ECHO
+/* This used to be an fputs(), but since the string might contain NUL's,
+ * we now use fwrite().
+ */
+#define ECHO (void) fwrite( zconftext, zconfleng, 1, zconfout )
+#endif
+
+/* Gets input and stuffs it into "buf".  number of characters read, or YY_NULL,
+ * is returned in "result".
+ */
+#ifndef YY_INPUT
+#define YY_INPUT(buf,result,max_size) \
+	errno=0; \
+	while ( (result = read( fileno(zconfin), (char *) buf, max_size )) < 0 ) \
+	{ \
+		if( errno != EINTR) \
+		{ \
+			YY_FATAL_ERROR( "input in flex scanner failed" ); \
+			break; \
+		} \
+		errno=0; \
+		clearerr(zconfin); \
+	}\
+\
+
+#endif
+
+/* No semi-colon after return; correct usage is to write "yyterminate();" -
+ * we don't want an extra ';' after the "return" because that will cause
+ * some compilers to complain about unreachable statements.
+ */
+#ifndef yyterminate
+#define yyterminate() return YY_NULL
+#endif
+
+/* Number of entries by which start-condition stack grows. */
+#ifndef YY_START_STACK_INCR
+#define YY_START_STACK_INCR 25
+#endif
+
+/* Report a fatal error. */
+#ifndef YY_FATAL_ERROR
+#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
+#endif
+
+/* end tables serialization structures and prototypes */
+
+/* Default declaration of generated scanner - a define so the user can
+ * easily add parameters.
+ */
+#ifndef YY_DECL
+#define YY_DECL_IS_OURS 1
+
+extern int zconflex (void);
+
+#define YY_DECL int zconflex (void)
+#endif /* !YY_DECL */
+
+/* Code executed at the beginning of each rule, after zconftext and zconfleng
+ * have been set up.
+ */
+#ifndef YY_USER_ACTION
+#define YY_USER_ACTION
+#endif
+
+/* Code executed at the end of each rule. */
+#ifndef YY_BREAK
+#define YY_BREAK break;
+#endif
+
+#define YY_RULE_SETUP \
+	YY_USER_ACTION
+
+/** The main scanner function which does all the work.
+ */
+YY_DECL
+{
+	register yy_state_type yy_current_state;
+	register char *yy_cp, *yy_bp;
+	register int yy_act;
+    
+	int str = 0;
+	int ts, i;
+
+	if ( !(yy_init) )
+		{
+		(yy_init) = 1;
+
+#ifdef YY_USER_INIT
+		YY_USER_INIT;
+#endif
+
+		if ( ! (yy_start) )
+			(yy_start) = 1;	/* first start state */
+
+		if ( ! zconfin )
+			zconfin = stdin;
+
+		if ( ! zconfout )
+			zconfout = stdout;
+
+		if ( ! YY_CURRENT_BUFFER ) {
+			zconfensure_buffer_stack ();
+			YY_CURRENT_BUFFER_LVALUE =
+				zconf_create_buffer(zconfin,YY_BUF_SIZE );
+		}
+
+		zconf_load_buffer_state( );
+		}
+
+	while ( 1 )		/* loops until end-of-file is reached */
+		{
+		yy_cp = (yy_c_buf_p);
+
+		/* Support of zconftext. */
+		*yy_cp = (yy_hold_char);
+
+		/* yy_bp points to the position in yy_ch_buf of the start of
+		 * the current run.
+		 */
+		yy_bp = yy_cp;
+
+		yy_current_state = (yy_start);
+yy_match:
+		while ( (yy_current_state = yy_nxt[yy_current_state][ yy_ec[YY_SC_TO_UI(*yy_cp)]  ]) > 0 )
+			++yy_cp;
+
+		yy_current_state = -yy_current_state;
+
+yy_find_action:
+		yy_act = yy_accept[yy_current_state];
+
+		YY_DO_BEFORE_ACTION;
+
+do_action:	/* This label is used only to access EOF actions. */
+
+		switch ( yy_act )
+	{ /* beginning of action switch */
+case 1:
+/* rule 1 can match eol */
+case 2:
+/* rule 2 can match eol */
+YY_RULE_SETUP
+{
+	current_file->lineno++;
+	return T_EOL;
+}
+	YY_BREAK
+case 3:
+YY_RULE_SETUP
+
+	YY_BREAK
+case 4:
+YY_RULE_SETUP
+{
+	BEGIN(COMMAND);
+}
+	YY_BREAK
+case 5:
+YY_RULE_SETUP
+{
+	unput(zconftext[0]);
+	BEGIN(COMMAND);
+}
+	YY_BREAK
+
+case 6:
+YY_RULE_SETUP
+{
+		struct kconf_id *id = kconf_id_lookup(zconftext, zconfleng);
+		BEGIN(PARAM);
+		current_pos.file = current_file;
+		current_pos.lineno = current_file->lineno;
+		if (id && id->flags & TF_COMMAND) {
+			zconflval.id = id;
+			return id->token;
+		}
+		alloc_string(zconftext, zconfleng);
+		zconflval.string = text;
+		return T_WORD;
+	}
+	YY_BREAK
+case 7:
+YY_RULE_SETUP
+
+	YY_BREAK
+case 8:
+/* rule 8 can match eol */
+YY_RULE_SETUP
+{
+		BEGIN(INITIAL);
+		current_file->lineno++;
+		return T_EOL;
+	}
+	YY_BREAK
+
+case 9:
+YY_RULE_SETUP
+return T_AND;
+	YY_BREAK
+case 10:
+YY_RULE_SETUP
+return T_OR;
+	YY_BREAK
+case 11:
+YY_RULE_SETUP
+return T_OPEN_PAREN;
+	YY_BREAK
+case 12:
+YY_RULE_SETUP
+return T_CLOSE_PAREN;
+	YY_BREAK
+case 13:
+YY_RULE_SETUP
+return T_NOT;
+	YY_BREAK
+case 14:
+YY_RULE_SETUP
+return T_EQUAL;
+	YY_BREAK
+case 15:
+YY_RULE_SETUP
+return T_UNEQUAL;
+	YY_BREAK
+case 16:
+YY_RULE_SETUP
+{
+		str = zconftext[0];
+		new_string();
+		BEGIN(STRING);
+	}
+	YY_BREAK
+case 17:
+/* rule 17 can match eol */
+YY_RULE_SETUP
+BEGIN(INITIAL); current_file->lineno++; return T_EOL;
+	YY_BREAK
+case 18:
+YY_RULE_SETUP
+/* ignore */
+	YY_BREAK
+case 19:
+YY_RULE_SETUP
+{
+		struct kconf_id *id = kconf_id_lookup(zconftext, zconfleng);
+		if (id && id->flags & TF_PARAM) {
+			zconflval.id = id;
+			return id->token;
+		}
+		alloc_string(zconftext, zconfleng);
+		zconflval.string = text;
+		return T_WORD;
+	}
+	YY_BREAK
+case 20:
+YY_RULE_SETUP
+/* comment */
+	YY_BREAK
+case 21:
+/* rule 21 can match eol */
+YY_RULE_SETUP
+current_file->lineno++;
+	YY_BREAK
+case 22:
+YY_RULE_SETUP
+
+	YY_BREAK
+case YY_STATE_EOF(PARAM):
+{
+		BEGIN(INITIAL);
+	}
+	YY_BREAK
+
+case 23:
+/* rule 23 can match eol */
+*yy_cp = (yy_hold_char); /* undo effects of setting up zconftext */
+(yy_c_buf_p) = yy_cp -= 1;
+YY_DO_BEFORE_ACTION; /* set up zconftext again */
+YY_RULE_SETUP
+{
+		append_string(zconftext, zconfleng);
+		zconflval.string = text;
+		return T_WORD_QUOTE;
+	}
+	YY_BREAK
+case 24:
+YY_RULE_SETUP
+{
+		append_string(zconftext, zconfleng);
+	}
+	YY_BREAK
+case 25:
+/* rule 25 can match eol */
+*yy_cp = (yy_hold_char); /* undo effects of setting up zconftext */
+(yy_c_buf_p) = yy_cp -= 1;
+YY_DO_BEFORE_ACTION; /* set up zconftext again */
+YY_RULE_SETUP
+{
+		append_string(zconftext + 1, zconfleng - 1);
+		zconflval.string = text;
+		return T_WORD_QUOTE;
+	}
+	YY_BREAK
+case 26:
+YY_RULE_SETUP
+{
+		append_string(zconftext + 1, zconfleng - 1);
+	}
+	YY_BREAK
+case 27:
+YY_RULE_SETUP
+{
+		if (str == zconftext[0]) {
+			BEGIN(PARAM);
+			zconflval.string = text;
+			return T_WORD_QUOTE;
+		} else
+			append_string(zconftext, 1);
+	}
+	YY_BREAK
+case 28:
+/* rule 28 can match eol */
+YY_RULE_SETUP
+{
+		printf("%s:%d:warning: multi-line strings not supported\n", zconf_curname(), zconf_lineno());
+		current_file->lineno++;
+		BEGIN(INITIAL);
+		return T_EOL;
+	}
+	YY_BREAK
+case YY_STATE_EOF(STRING):
+{
+		BEGIN(INITIAL);
+	}
+	YY_BREAK
+
+case 29:
+YY_RULE_SETUP
+{
+		ts = 0;
+		for (i = 0; i < zconfleng; i++) {
+			if (zconftext[i] == '\t')
+				ts = (ts & ~7) + 8;
+			else
+				ts++;
+		}
+		last_ts = ts;
+		if (first_ts) {
+			if (ts < first_ts) {
+				zconf_endhelp();
+				return T_HELPTEXT;
+			}
+			ts -= first_ts;
+			while (ts > 8) {
+				append_string("        ", 8);
+				ts -= 8;
+			}
+			append_string("        ", ts);
+		}
+	}
+	YY_BREAK
+case 30:
+/* rule 30 can match eol */
+*yy_cp = (yy_hold_char); /* undo effects of setting up zconftext */
+(yy_c_buf_p) = yy_cp -= 1;
+YY_DO_BEFORE_ACTION; /* set up zconftext again */
+YY_RULE_SETUP
+{
+		current_file->lineno++;
+		zconf_endhelp();
+		return T_HELPTEXT;
+	}
+	YY_BREAK
+case 31:
+/* rule 31 can match eol */
+YY_RULE_SETUP
+{
+		current_file->lineno++;
+		append_string("\n", 1);
+	}
+	YY_BREAK
+case 32:
+YY_RULE_SETUP
+{
+		while (zconfleng) {
+			if ((zconftext[zconfleng-1] != ' ') && (zconftext[zconfleng-1] != '\t'))
+				break;
+			zconfleng--;
+		}
+		append_string(zconftext, zconfleng);
+		if (!first_ts)
+			first_ts = last_ts;
+	}
+	YY_BREAK
+case YY_STATE_EOF(HELP):
+{
+		zconf_endhelp();
+		return T_HELPTEXT;
+	}
+	YY_BREAK
+
+case YY_STATE_EOF(INITIAL):
+case YY_STATE_EOF(COMMAND):
+{
+	if (current_file) {
+		zconf_endfile();
+		return T_EOL;
+	}
+	fclose(zconfin);
+	yyterminate();
+}
+	YY_BREAK
+case 33:
+YY_RULE_SETUP
+YY_FATAL_ERROR( "flex scanner jammed" );
+	YY_BREAK
+
+	case YY_END_OF_BUFFER:
+		{
+		/* Amount of text matched not including the EOB char. */
+		int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;
+
+		/* Undo the effects of YY_DO_BEFORE_ACTION. */
+		*yy_cp = (yy_hold_char);
+		YY_RESTORE_YY_MORE_OFFSET
+
+		if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
+			{
+			/* We're scanning a new file or input source.  It's
+			 * possible that this happened because the user
+			 * just pointed zconfin at a new source and called
+			 * zconflex().  If so, then we have to assure
+			 * consistency between YY_CURRENT_BUFFER and our
+			 * globals.  Here is the right place to do so, because
+			 * this is the first action (other than possibly a
+			 * back-up) that will match for the new input source.
+			 */
+			(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+			YY_CURRENT_BUFFER_LVALUE->yy_input_file = zconfin;
+			YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
+			}
+
+		/* Note that here we test for yy_c_buf_p "<=" to the position
+		 * of the first EOB in the buffer, since yy_c_buf_p will
+		 * already have been incremented past the NUL character
+		 * (since all states make transitions on EOB to the
+		 * end-of-buffer state).  Contrast this with the test
+		 * in input().
+		 */
+		if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+			{ /* This was really a NUL. */
+			yy_state_type yy_next_state;
+
+			(yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;
+
+			yy_current_state = yy_get_previous_state(  );
+
+			/* Okay, we're now positioned to make the NUL
+			 * transition.  We couldn't have
+			 * yy_get_previous_state() go ahead and do it
+			 * for us because it doesn't know how to deal
+			 * with the possibility of jamming (and we don't
+			 * want to build jamming into it because then it
+			 * will run more slowly).
+			 */
+
+			yy_next_state = yy_try_NUL_trans( yy_current_state );
+
+			yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+
+			if ( yy_next_state )
+				{
+				/* Consume the NUL. */
+				yy_cp = ++(yy_c_buf_p);
+				yy_current_state = yy_next_state;
+				goto yy_match;
+				}
+
+			else
+				{
+				yy_cp = (yy_c_buf_p);
+				goto yy_find_action;
+				}
+			}
+
+		else switch ( yy_get_next_buffer(  ) )
+			{
+			case EOB_ACT_END_OF_FILE:
+				{
+				(yy_did_buffer_switch_on_eof) = 0;
+
+				if ( zconfwrap( ) )
+					{
+					/* Note: because we've taken care in
+					 * yy_get_next_buffer() to have set up
+					 * zconftext, we can now set up
+					 * yy_c_buf_p so that if some total
+					 * hoser (like flex itself) wants to
+					 * call the scanner after we return the
+					 * YY_NULL, it'll still work - another
+					 * YY_NULL will get returned.
+					 */
+					(yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;
+
+					yy_act = YY_STATE_EOF(YY_START);
+					goto do_action;
+					}
+
+				else
+					{
+					if ( ! (yy_did_buffer_switch_on_eof) )
+						YY_NEW_FILE;
+					}
+				break;
+				}
+
+			case EOB_ACT_CONTINUE_SCAN:
+				(yy_c_buf_p) =
+					(yytext_ptr) + yy_amount_of_matched_text;
+
+				yy_current_state = yy_get_previous_state(  );
+
+				yy_cp = (yy_c_buf_p);
+				yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+				goto yy_match;
+
+			case EOB_ACT_LAST_MATCH:
+				(yy_c_buf_p) =
+				&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];
+
+				yy_current_state = yy_get_previous_state(  );
+
+				yy_cp = (yy_c_buf_p);
+				yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+				goto yy_find_action;
+			}
+		break;
+		}
+
+	default:
+		YY_FATAL_ERROR(
+			"fatal flex scanner internal error--no action found" );
+	} /* end of action switch */
+		} /* end of scanning one token */
+} /* end of zconflex */
+
+/* yy_get_next_buffer - try to read in a new buffer
+ *
+ * Returns a code representing an action:
+ *	EOB_ACT_LAST_MATCH -
+ *	EOB_ACT_CONTINUE_SCAN - continue scanning from current position
+ *	EOB_ACT_END_OF_FILE - end of file
+ */
+static int yy_get_next_buffer (void)
+{
+    	register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
+	register char *source = (yytext_ptr);
+	register int number_to_move, i;
+	int ret_val;
+
+	if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
+		YY_FATAL_ERROR(
+		"fatal flex scanner internal error--end of buffer missed" );
+
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
+		{ /* Don't try to fill the buffer, so this is an EOF. */
+		if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )
+			{
+			/* We matched a single character, the EOB, so
+			 * treat this as a final EOF.
+			 */
+			return EOB_ACT_END_OF_FILE;
+			}
+
+		else
+			{
+			/* We matched some text prior to the EOB, first
+			 * process it.
+			 */
+			return EOB_ACT_LAST_MATCH;
+			}
+		}
+
+	/* Try to read more data. */
+
+	/* First move last chars to start of buffer. */
+	number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
+
+	for ( i = 0; i < number_to_move; ++i )
+		*(dest++) = *(source++);
+
+	if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
+		/* don't do the read, it's not guaranteed to return an EOF,
+		 * just force an EOF
+		 */
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;
+
+	else
+		{
+			int num_to_read =
+			YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
+
+		while ( num_to_read <= 0 )
+			{ /* Not enough room in the buffer - grow it. */
+
+			/* just a shorter name for the current buffer */
+			YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
+
+			int yy_c_buf_p_offset =
+				(int) ((yy_c_buf_p) - b->yy_ch_buf);
+
+			if ( b->yy_is_our_buffer )
+				{
+				int new_size = b->yy_buf_size * 2;
+
+				if ( new_size <= 0 )
+					b->yy_buf_size += b->yy_buf_size / 8;
+				else
+					b->yy_buf_size *= 2;
+
+				b->yy_ch_buf = (char *)
+					/* Include room in for 2 EOB chars. */
+					zconfrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2  );
+				}
+			else
+				/* Can't grow it, we don't own it. */
+				b->yy_ch_buf = 0;
+
+			if ( ! b->yy_ch_buf )
+				YY_FATAL_ERROR(
+				"fatal error - scanner input buffer overflow" );
+
+			(yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];
+
+			num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
+						number_to_move - 1;
+
+			}
+
+		if ( num_to_read > YY_READ_BUF_SIZE )
+			num_to_read = YY_READ_BUF_SIZE;
+
+		/* Read in more data. */
+		YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
+			(yy_n_chars), num_to_read );
+
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	if ( (yy_n_chars) == 0 )
+		{
+		if ( number_to_move == YY_MORE_ADJ )
+			{
+			ret_val = EOB_ACT_END_OF_FILE;
+			zconfrestart(zconfin  );
+			}
+
+		else
+			{
+			ret_val = EOB_ACT_LAST_MATCH;
+			YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
+				YY_BUFFER_EOF_PENDING;
+			}
+		}
+
+	else
+		ret_val = EOB_ACT_CONTINUE_SCAN;
+
+	(yy_n_chars) += number_to_move;
+	YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;
+	YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;
+
+	(yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
+
+	return ret_val;
+}
+
+/* yy_get_previous_state - get the state just before the EOB char was reached */
+
+    static yy_state_type yy_get_previous_state (void)
+{
+	register yy_state_type yy_current_state;
+	register char *yy_cp;
+    
+	yy_current_state = (yy_start);
+
+	for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
+		{
+		yy_current_state = yy_nxt[yy_current_state][(*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1)];
+		}
+
+	return yy_current_state;
+}
+
+/* yy_try_NUL_trans - try to make a transition on the NUL character
+ *
+ * synopsis
+ *	next_state = yy_try_NUL_trans( current_state );
+ */
+    static yy_state_type yy_try_NUL_trans  (yy_state_type yy_current_state )
+{
+	register int yy_is_jam;
+    
+	yy_current_state = yy_nxt[yy_current_state][1];
+	yy_is_jam = (yy_current_state <= 0);
+
+	return yy_is_jam ? 0 : yy_current_state;
+}
+
+    static void yyunput (int c, register char * yy_bp )
+{
+	register char *yy_cp;
+    
+    yy_cp = (yy_c_buf_p);
+
+	/* undo effects of setting up zconftext */
+	*yy_cp = (yy_hold_char);
+
+	if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+		{ /* need to shift things up to make room */
+		/* +2 for EOB chars. */
+		register int number_to_move = (yy_n_chars) + 2;
+		register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[
+					YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];
+		register char *source =
+				&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];
+
+		while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+			*--dest = *--source;
+
+		yy_cp += (int) (dest - source);
+		yy_bp += (int) (dest - source);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars =
+			(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size;
+
+		if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+			YY_FATAL_ERROR( "flex scanner push-back overflow" );
+		}
+
+	*--yy_cp = (char) c;
+
+	(yytext_ptr) = yy_bp;
+	(yy_hold_char) = *yy_cp;
+	(yy_c_buf_p) = yy_cp;
+}
+
+#ifndef YY_NO_INPUT
+#ifdef __cplusplus
+    static int yyinput (void)
+#else
+    static int input  (void)
+#endif
+
+{
+	int c;
+    
+	*(yy_c_buf_p) = (yy_hold_char);
+
+	if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )
+		{
+		/* yy_c_buf_p now points to the character we want to return.
+		 * If this occurs *before* the EOB characters, then it's a
+		 * valid NUL; if not, then we've hit the end of the buffer.
+		 */
+		if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+			/* This was really a NUL. */
+			*(yy_c_buf_p) = '\0';
+
+		else
+			{ /* need more input */
+			int offset = (yy_c_buf_p) - (yytext_ptr);
+			++(yy_c_buf_p);
+
+			switch ( yy_get_next_buffer(  ) )
+				{
+				case EOB_ACT_LAST_MATCH:
+					/* This happens because yy_g_n_b()
+					 * sees that we've accumulated a
+					 * token and flags that we need to
+					 * try matching the token before
+					 * proceeding.  But for input(),
+					 * there's no matching to consider.
+					 * So convert the EOB_ACT_LAST_MATCH
+					 * to EOB_ACT_END_OF_FILE.
+					 */
+
+					/* Reset buffer status. */
+					zconfrestart(zconfin );
+
+					/*FALLTHROUGH*/
+
+				case EOB_ACT_END_OF_FILE:
+					{
+					if ( zconfwrap( ) )
+						return EOF;
+
+					if ( ! (yy_did_buffer_switch_on_eof) )
+						YY_NEW_FILE;
+#ifdef __cplusplus
+					return yyinput();
+#else
+					return input();
+#endif
+					}
+
+				case EOB_ACT_CONTINUE_SCAN:
+					(yy_c_buf_p) = (yytext_ptr) + offset;
+					break;
+				}
+			}
+		}
+
+	c = *(unsigned char *) (yy_c_buf_p);	/* cast for 8-bit char's */
+	*(yy_c_buf_p) = '\0';	/* preserve zconftext */
+	(yy_hold_char) = *++(yy_c_buf_p);
+
+	return c;
+}
+#endif	/* ifndef YY_NO_INPUT */
+
+/** Immediately switch to a different input stream.
+ * @param input_file A readable stream.
+ * 
+ * @note This function does not reset the start condition to @c INITIAL .
+ */
+    void zconfrestart  (FILE * input_file )
+{
+    
+	if ( ! YY_CURRENT_BUFFER ){
+        zconfensure_buffer_stack ();
+		YY_CURRENT_BUFFER_LVALUE =
+            zconf_create_buffer(zconfin,YY_BUF_SIZE );
+	}
+
+	zconf_init_buffer(YY_CURRENT_BUFFER,input_file );
+	zconf_load_buffer_state( );
+}
+
+/** Switch to a different input buffer.
+ * @param new_buffer The new input buffer.
+ * 
+ */
+    void zconf_switch_to_buffer  (YY_BUFFER_STATE  new_buffer )
+{
+    
+	/* TODO. We should be able to replace this entire function body
+	 * with
+	 *		zconfpop_buffer_state();
+	 *		zconfpush_buffer_state(new_buffer);
+     */
+	zconfensure_buffer_stack ();
+	if ( YY_CURRENT_BUFFER == new_buffer )
+		return;
+
+	if ( YY_CURRENT_BUFFER )
+		{
+		/* Flush out information for old buffer. */
+		*(yy_c_buf_p) = (yy_hold_char);
+		YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	YY_CURRENT_BUFFER_LVALUE = new_buffer;
+	zconf_load_buffer_state( );
+
+	/* We don't actually know whether we did this switch during
+	 * EOF (zconfwrap()) processing, but the only time this flag
+	 * is looked at is after zconfwrap() is called, so it's safe
+	 * to go ahead and always set it.
+	 */
+	(yy_did_buffer_switch_on_eof) = 1;
+}
+
+static void zconf_load_buffer_state  (void)
+{
+    	(yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+	(yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
+	zconfin = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
+	(yy_hold_char) = *(yy_c_buf_p);
+}
+
+/** Allocate and initialize an input buffer state.
+ * @param file A readable stream.
+ * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
+ * 
+ * @return the allocated buffer state.
+ */
+    YY_BUFFER_STATE zconf_create_buffer  (FILE * file, int  size )
+{
+	YY_BUFFER_STATE b;
+    
+	b = (YY_BUFFER_STATE) zconfalloc(sizeof( struct yy_buffer_state )  );
+	if ( ! b )
+		YY_FATAL_ERROR( "out of dynamic memory in zconf_create_buffer()" );
+
+	b->yy_buf_size = size;
+
+	/* yy_ch_buf has to be 2 characters longer than the size given because
+	 * we need to put in 2 end-of-buffer characters.
+	 */
+	b->yy_ch_buf = (char *) zconfalloc(b->yy_buf_size + 2  );
+	if ( ! b->yy_ch_buf )
+		YY_FATAL_ERROR( "out of dynamic memory in zconf_create_buffer()" );
+
+	b->yy_is_our_buffer = 1;
+
+	zconf_init_buffer(b,file );
+
+	return b;
+}
+
+/** Destroy the buffer.
+ * @param b a buffer created with zconf_create_buffer()
+ * 
+ */
+    void zconf_delete_buffer (YY_BUFFER_STATE  b )
+{
+    
+	if ( ! b )
+		return;
+
+	if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
+		YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
+
+	if ( b->yy_is_our_buffer )
+		zconffree((void *) b->yy_ch_buf  );
+
+	zconffree((void *) b  );
+}
+
+/* Initializes or reinitializes a buffer.
+ * This function is sometimes called more than once on the same buffer,
+ * such as during a zconfrestart() or at EOF.
+ */
+    static void zconf_init_buffer  (YY_BUFFER_STATE  b, FILE * file )
+
+{
+	int oerrno = errno;
+    
+	zconf_flush_buffer(b );
+
+	b->yy_input_file = file;
+	b->yy_fill_buffer = 1;
+
+    /* If b is the current buffer, then zconf_init_buffer was _probably_
+     * called from zconfrestart() or through yy_get_next_buffer.
+     * In that case, we don't want to reset the lineno or column.
+     */
+    if (b != YY_CURRENT_BUFFER){
+        b->yy_bs_lineno = 1;
+        b->yy_bs_column = 0;
+    }
+
+        b->yy_is_interactive = 0;
+    
+	errno = oerrno;
+}
+
+/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
+ * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
+ * 
+ */
+    void zconf_flush_buffer (YY_BUFFER_STATE  b )
+{
+    	if ( ! b )
+		return;
+
+	b->yy_n_chars = 0;
+
+	/* We always need two end-of-buffer characters.  The first causes
+	 * a transition to the end-of-buffer state.  The second causes
+	 * a jam in that state.
+	 */
+	b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
+	b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
+
+	b->yy_buf_pos = &b->yy_ch_buf[0];
+
+	b->yy_at_bol = 1;
+	b->yy_buffer_status = YY_BUFFER_NEW;
+
+	if ( b == YY_CURRENT_BUFFER )
+		zconf_load_buffer_state( );
+}
+
+/** Pushes the new state onto the stack. The new state becomes
+ *  the current state. This function will allocate the stack
+ *  if necessary.
+ *  @param new_buffer The new state.
+ *  
+ */
+void zconfpush_buffer_state (YY_BUFFER_STATE new_buffer )
+{
+    	if (new_buffer == NULL)
+		return;
+
+	zconfensure_buffer_stack();
+
+	/* This block is copied from zconf_switch_to_buffer. */
+	if ( YY_CURRENT_BUFFER )
+		{
+		/* Flush out information for old buffer. */
+		*(yy_c_buf_p) = (yy_hold_char);
+		YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+		YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+		}
+
+	/* Only push if top exists. Otherwise, replace top. */
+	if (YY_CURRENT_BUFFER)
+		(yy_buffer_stack_top)++;
+	YY_CURRENT_BUFFER_LVALUE = new_buffer;
+
+	/* copied from zconf_switch_to_buffer. */
+	zconf_load_buffer_state( );
+	(yy_did_buffer_switch_on_eof) = 1;
+}
+
+/** Removes and deletes the top of the stack, if present.
+ *  The next element becomes the new top.
+ *  
+ */
+void zconfpop_buffer_state (void)
+{
+    	if (!YY_CURRENT_BUFFER)
+		return;
+
+	zconf_delete_buffer(YY_CURRENT_BUFFER );
+	YY_CURRENT_BUFFER_LVALUE = NULL;
+	if ((yy_buffer_stack_top) > 0)
+		--(yy_buffer_stack_top);
+
+	if (YY_CURRENT_BUFFER) {
+		zconf_load_buffer_state( );
+		(yy_did_buffer_switch_on_eof) = 1;
+	}
+}
+
+/* Allocates the stack if it does not exist.
+ *  Guarantees space for at least one push.
+ */
+static void zconfensure_buffer_stack (void)
+{
+	int num_to_alloc;
+    
+	if (!(yy_buffer_stack)) {
+
+		/* First allocation is just for 2 elements, since we don't know if this
+		 * scanner will even need a stack. We use 2 instead of 1 to avoid an
+		 * immediate realloc on the next call.
+         */
+		num_to_alloc = 1;
+		(yy_buffer_stack) = (struct yy_buffer_state**)zconfalloc
+								(num_to_alloc * sizeof(struct yy_buffer_state*)
+								);
+		
+		memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));
+				
+		(yy_buffer_stack_max) = num_to_alloc;
+		(yy_buffer_stack_top) = 0;
+		return;
+	}
+
+	if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
+
+		/* Increase the buffer to prepare for a possible push. */
+		int grow_size = 8 /* arbitrary grow size */;
+
+		num_to_alloc = (yy_buffer_stack_max) + grow_size;
+		(yy_buffer_stack) = (struct yy_buffer_state**)zconfrealloc
+								((yy_buffer_stack),
+								num_to_alloc * sizeof(struct yy_buffer_state*)
+								);
+
+		/* zero only the new slots.*/
+		memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));
+		(yy_buffer_stack_max) = num_to_alloc;
+	}
+}
+
+/** Setup the input buffer state to scan directly from a user-specified character buffer.
+ * @param base the character buffer
+ * @param size the size in bytes of the character buffer
+ * 
+ * @return the newly allocated buffer state object. 
+ */
+YY_BUFFER_STATE zconf_scan_buffer  (char * base, yy_size_t  size )
+{
+	YY_BUFFER_STATE b;
+    
+	if ( size < 2 ||
+	     base[size-2] != YY_END_OF_BUFFER_CHAR ||
+	     base[size-1] != YY_END_OF_BUFFER_CHAR )
+		/* They forgot to leave room for the EOB's. */
+		return 0;
+
+	b = (YY_BUFFER_STATE) zconfalloc(sizeof( struct yy_buffer_state )  );
+	if ( ! b )
+		YY_FATAL_ERROR( "out of dynamic memory in zconf_scan_buffer()" );
+
+	b->yy_buf_size = size - 2;	/* "- 2" to take care of EOB's */
+	b->yy_buf_pos = b->yy_ch_buf = base;
+	b->yy_is_our_buffer = 0;
+	b->yy_input_file = 0;
+	b->yy_n_chars = b->yy_buf_size;
+	b->yy_is_interactive = 0;
+	b->yy_at_bol = 1;
+	b->yy_fill_buffer = 0;
+	b->yy_buffer_status = YY_BUFFER_NEW;
+
+	zconf_switch_to_buffer(b  );
+
+	return b;
+}
+
+/** Setup the input buffer state to scan a string. The next call to zconflex() will
+ * scan from a @e copy of @a str.
+ * @param str a NUL-terminated string to scan
+ * 
+ * @return the newly allocated buffer state object.
+ * @note If you want to scan bytes that may contain NUL values, then use
+ *       zconf_scan_bytes() instead.
+ */
+YY_BUFFER_STATE zconf_scan_string (yyconst char * yystr )
+{
+    
+	return zconf_scan_bytes(yystr,strlen(yystr) );
+}
+
+/** Setup the input buffer state to scan the given bytes. The next call to zconflex() will
+ * scan from a @e copy of @a bytes.
+ * @param bytes the byte buffer to scan
+ * @param len the number of bytes in the buffer pointed to by @a bytes.
+ * 
+ * @return the newly allocated buffer state object.
+ */
+YY_BUFFER_STATE zconf_scan_bytes  (yyconst char * yybytes, int  _yybytes_len )
+{
+	YY_BUFFER_STATE b;
+	char *buf;
+	yy_size_t n;
+	int i;
+    
+	/* Get memory for full buffer, including space for trailing EOB's. */
+	n = _yybytes_len + 2;
+	buf = (char *) zconfalloc(n  );
+	if ( ! buf )
+		YY_FATAL_ERROR( "out of dynamic memory in zconf_scan_bytes()" );
+
+	for ( i = 0; i < _yybytes_len; ++i )
+		buf[i] = yybytes[i];
+
+	buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
+
+	b = zconf_scan_buffer(buf,n );
+	if ( ! b )
+		YY_FATAL_ERROR( "bad buffer in zconf_scan_bytes()" );
+
+	/* It's okay to grow etc. this buffer, and we should throw it
+	 * away when we're done.
+	 */
+	b->yy_is_our_buffer = 1;
+
+	return b;
+}
+
+#ifndef YY_EXIT_FAILURE
+#define YY_EXIT_FAILURE 2
+#endif
+
+static void yy_fatal_error (yyconst char* msg )
+{
+    	(void) fprintf( stderr, "%s\n", msg );
+	exit( YY_EXIT_FAILURE );
+}
+
+/* Redefine yyless() so it works in section 3 code. */
+
+#undef yyless
+#define yyless(n) \
+	do \
+		{ \
+		/* Undo effects of setting up zconftext. */ \
+        int yyless_macro_arg = (n); \
+        YY_LESS_LINENO(yyless_macro_arg);\
+		zconftext[zconfleng] = (yy_hold_char); \
+		(yy_c_buf_p) = zconftext + yyless_macro_arg; \
+		(yy_hold_char) = *(yy_c_buf_p); \
+		*(yy_c_buf_p) = '\0'; \
+		zconfleng = yyless_macro_arg; \
+		} \
+	while ( 0 )
+
+/* Accessor  methods (get/set functions) to struct members. */
+
+/** Get the current line number.
+ * 
+ */
+int zconfget_lineno  (void)
+{
+        
+    return zconflineno;
+}
+
+/** Get the input stream.
+ * 
+ */
+FILE *zconfget_in  (void)
+{
+        return zconfin;
+}
+
+/** Get the output stream.
+ * 
+ */
+FILE *zconfget_out  (void)
+{
+        return zconfout;
+}
+
+/** Get the length of the current token.
+ * 
+ */
+int zconfget_leng  (void)
+{
+        return zconfleng;
+}
+
+/** Get the current token.
+ * 
+ */
+
+char *zconfget_text  (void)
+{
+        return zconftext;
+}
+
+/** Set the current line number.
+ * @param line_number
+ * 
+ */
+void zconfset_lineno (int  line_number )
+{
+    
+    zconflineno = line_number;
+}
+
+/** Set the input stream. This does not discard the current
+ * input buffer.
+ * @param in_str A readable stream.
+ * 
+ * @see zconf_switch_to_buffer
+ */
+void zconfset_in (FILE *  in_str )
+{
+        zconfin = in_str ;
+}
+
+void zconfset_out (FILE *  out_str )
+{
+        zconfout = out_str ;
+}
+
+int zconfget_debug  (void)
+{
+        return zconf_flex_debug;
+}
+
+void zconfset_debug (int  bdebug )
+{
+        zconf_flex_debug = bdebug ;
+}
+
+static int yy_init_globals (void)
+{
+        /* Initialization is the same as for the non-reentrant scanner.
+     * This function is called from zconflex_destroy(), so don't allocate here.
+     */
+
+    (yy_buffer_stack) = 0;
+    (yy_buffer_stack_top) = 0;
+    (yy_buffer_stack_max) = 0;
+    (yy_c_buf_p) = (char *) 0;
+    (yy_init) = 0;
+    (yy_start) = 0;
+
+/* Defined in main.c */
+#ifdef YY_STDINIT
+    zconfin = stdin;
+    zconfout = stdout;
+#else
+    zconfin = (FILE *) 0;
+    zconfout = (FILE *) 0;
+#endif
+
+    /* For future reference: Set errno on error, since we are called by
+     * zconflex_init()
+     */
+    return 0;
+}
+
+/* zconflex_destroy is for both reentrant and non-reentrant scanners. */
+int zconflex_destroy  (void)
+{
+    
+    /* Pop the buffer stack, destroying each element. */
+	while(YY_CURRENT_BUFFER){
+		zconf_delete_buffer(YY_CURRENT_BUFFER  );
+		YY_CURRENT_BUFFER_LVALUE = NULL;
+		zconfpop_buffer_state();
+	}
+
+	/* Destroy the stack itself. */
+	zconffree((yy_buffer_stack) );
+	(yy_buffer_stack) = NULL;
+
+    /* Reset the globals. This is important in a non-reentrant scanner so the next time
+     * zconflex() is called, initialization will occur. */
+    yy_init_globals( );
+
+    return 0;
+}
+
+/*
+ * Internal utility routines.
+ */
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
+{
+	register int i;
+	for ( i = 0; i < n; ++i )
+		s1[i] = s2[i];
+}
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * s )
+{
+	register int n;
+	for ( n = 0; s[n]; ++n )
+		;
+
+	return n;
+}
+#endif
+
+void *zconfalloc (yy_size_t  size )
+{
+	return (void *) malloc( size );
+}
+
+void *zconfrealloc  (void * ptr, yy_size_t  size )
+{
+	/* The cast to (char *) in the following accommodates both
+	 * implementations that use char* generic pointers, and those
+	 * that use void* generic pointers.  It works with the latter
+	 * because both ANSI C and C++ allow castless assignment from
+	 * any pointer type to void*, and deal with argument conversions
+	 * as though doing an assignment.
+	 */
+	return (void *) realloc( (char *) ptr, size );
+}
+
+void zconffree (void * ptr )
+{
+	free( (char *) ptr );	/* see zconfrealloc() for (char *) cast */
+}
+
+#define YYTABLES_NAME "yytables"
+
+void zconf_starthelp(void)
+{
+	new_string();
+	last_ts = first_ts = 0;
+	BEGIN(HELP);
+}
+
+static void zconf_endhelp(void)
+{
+	zconflval.string = text;
+	BEGIN(INITIAL);
+}
+
+/*
+ * Try to open specified file with following names:
+ * ./name
+ * $(srctree)/name
+ * The latter is used when srctree is separate from objtree
+ * when compiling the kernel.
+ * Return NULL if file is not found.
+ */
+FILE *zconf_fopen(const char *name)
+{
+	char *env, fullname[PATH_MAX+1];
+	FILE *f;
+
+	f = fopen(name, "r");
+	if (!f && name != NULL && name[0] != '/') {
+		env = getenv(SRCTREE);
+		if (env) {
+			sprintf(fullname, "%s/%s", env, name);
+			f = fopen(fullname, "r");
+		}
+	}
+	return f;
+}
+
+void zconf_initscan(const char *name)
+{
+	zconfin = zconf_fopen(name);
+	if (!zconfin) {
+		printf("can't find file %s\n", name);
+		exit(1);
+	}
+
+	current_buf = malloc(sizeof(*current_buf));
+	memset(current_buf, 0, sizeof(*current_buf));
+
+	current_file = file_lookup(name);
+	current_file->lineno = 1;
+	current_file->flags = FILE_BUSY;
+}
+
+void zconf_nextfile(const char *name)
+{
+	struct file *file = file_lookup(name);
+	struct buffer *buf = malloc(sizeof(*buf));
+	memset(buf, 0, sizeof(*buf));
+
+	current_buf->state = YY_CURRENT_BUFFER;
+	zconfin = zconf_fopen(name);
+	if (!zconfin) {
+		printf("%s:%d: can't open file \"%s\"\n", zconf_curname(), zconf_lineno(), name);
+		exit(1);
+	}
+	zconf_switch_to_buffer(zconf_create_buffer(zconfin,YY_BUF_SIZE));
+	buf->parent = current_buf;
+	current_buf = buf;
+
+	if (file->flags & FILE_BUSY) {
+		printf("recursive scan (%s)?\n", name);
+		exit(1);
+	}
+	if (file->flags & FILE_SCANNED) {
+		printf("file %s already scanned?\n", name);
+		exit(1);
+	}
+	file->flags |= FILE_BUSY;
+	file->lineno = 1;
+	file->parent = current_file;
+	current_file = file;
+}
+
+static void zconf_endfile(void)
+{
+	struct buffer *parent;
+
+	current_file->flags |= FILE_SCANNED;
+	current_file->flags &= ~FILE_BUSY;
+	current_file = current_file->parent;
+
+	parent = current_buf->parent;
+	if (parent) {
+		fclose(zconfin);
+		zconf_delete_buffer(YY_CURRENT_BUFFER);
+		zconf_switch_to_buffer(parent->state);
+	}
+	free(current_buf);
+	current_buf = parent;
+}
+
+int zconf_lineno(void)
+{
+	return current_pos.lineno;
+}
+
+char *zconf_curname(void)
+{
+	return current_pos.file ? current_pos.file->name : "<none>";
+}
+

Added: trunk/coreboot-v2/util/kconfig/lkc.h
===================================================================
--- trunk/coreboot-v2/util/kconfig/lkc.h	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/lkc.h	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel at linux-m68k.org>
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#ifndef LKC_H
+#define LKC_H
+
+#include "expr.h"
+
+#ifndef KBUILD_NO_NLS
+# include <libintl.h>
+#else
+# define gettext(Msgid) ((const char *) (Msgid))
+# define textdomain(Domainname) ((const char *) (Domainname))
+# define bindtextdomain(Domainname, Dirname) ((const char *) (Dirname))
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef LKC_DIRECT_LINK
+#define P(name,type,arg)	extern type name arg
+#else
+#include "lkc_defs.h"
+#define P(name,type,arg)	extern type (*name ## _p) arg
+#endif
+#include "lkc_proto.h"
+#undef P
+
+#define SRCTREE "src"
+
+#define PACKAGE "coreboot"
+#define LOCALEDIR "/usr/share/locale"
+
+#define _(text) gettext(text)
+#define N_(text) (text)
+
+
+#define TF_COMMAND	0x0001
+#define TF_PARAM	0x0002
+#define TF_OPTION	0x0004
+
+#define T_OPT_MODULES		1
+#define T_OPT_DEFCONFIG_LIST	2
+#define T_OPT_ENV		3
+
+struct kconf_id {
+	int name;
+	int token;
+	unsigned int flags;
+	enum symbol_type stype;
+};
+
+int zconfparse(void);
+void zconfdump(FILE *out);
+
+extern int zconfdebug;
+void zconf_starthelp(void);
+FILE *zconf_fopen(const char *name);
+void zconf_initscan(const char *name);
+void zconf_nextfile(const char *name);
+int zconf_lineno(void);
+char *zconf_curname(void);
+
+/* confdata.c */
+const char *conf_get_configname(void);
+char *conf_get_default_confname(void);
+void sym_set_change_count(int count);
+void sym_add_change_count(int count);
+
+/* kconfig_load.c */
+void kconfig_load(void);
+
+/* menu.c */
+void menu_init(void);
+void menu_warn(struct menu *menu, const char *fmt, ...);
+struct menu *menu_add_menu(void);
+void menu_end_menu(void);
+void menu_add_entry(struct symbol *sym);
+void menu_end_entry(void);
+void menu_add_dep(struct expr *dep);
+struct property *menu_add_prop(enum prop_type type, char *prompt, struct expr *expr, struct expr *dep);
+struct property *menu_add_prompt(enum prop_type type, char *prompt, struct expr *dep);
+void menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep);
+void menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep);
+void menu_add_option(int token, char *arg);
+void menu_finalize(struct menu *parent);
+void menu_set_type(int type);
+
+/* util.c */
+struct file *file_lookup(const char *name);
+int file_write_dep(const char *name);
+
+struct gstr {
+	size_t len;
+	char  *s;
+};
+struct gstr str_new(void);
+struct gstr str_assign(const char *s);
+void str_free(struct gstr *gs);
+void str_append(struct gstr *gs, const char *s);
+void str_printf(struct gstr *gs, const char *fmt, ...);
+const char *str_get(struct gstr *gs);
+
+/* symbol.c */
+extern struct expr *sym_env_list;
+
+void sym_init(void);
+void sym_clear_all_valid(void);
+void sym_set_all_changed(void);
+void sym_set_changed(struct symbol *sym);
+struct symbol *sym_check_deps(struct symbol *sym);
+struct property *prop_alloc(enum prop_type type, struct symbol *sym);
+struct symbol *prop_get_symbol(struct property *prop);
+struct property *sym_get_env_prop(struct symbol *sym);
+
+static inline tristate sym_get_tristate_value(struct symbol *sym)
+{
+	return sym->curr.tri;
+}
+
+
+static inline struct symbol *sym_get_choice_value(struct symbol *sym)
+{
+	return (struct symbol *)sym->curr.val;
+}
+
+static inline bool sym_set_choice_value(struct symbol *ch, struct symbol *chval)
+{
+	return sym_set_tristate_value(chval, yes);
+}
+
+static inline bool sym_is_choice(struct symbol *sym)
+{
+	return sym->flags & SYMBOL_CHOICE ? true : false;
+}
+
+static inline bool sym_is_choice_value(struct symbol *sym)
+{
+	return sym->flags & SYMBOL_CHOICEVAL ? true : false;
+}
+
+static inline bool sym_is_optional(struct symbol *sym)
+{
+	return sym->flags & SYMBOL_OPTIONAL ? true : false;
+}
+
+static inline bool sym_has_value(struct symbol *sym)
+{
+	return sym->flags & SYMBOL_DEF_USER ? true : false;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LKC_H */

Added: trunk/coreboot-v2/util/kconfig/lkc_proto.h
===================================================================
--- trunk/coreboot-v2/util/kconfig/lkc_proto.h	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/lkc_proto.h	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,45 @@
+
+/* confdata.c */
+P(conf_parse,void,(const char *name));
+P(conf_read,int,(const char *name));
+P(conf_read_simple,int,(const char *name, int));
+P(conf_write,int,(const char *name));
+P(conf_write_autoconf,int,(void));
+P(conf_get_changed,bool,(void));
+P(conf_set_changed_callback, void,(void (*fn)(void)));
+
+/* menu.c */
+P(rootmenu,struct menu,);
+
+P(menu_is_visible,bool,(struct menu *menu));
+P(menu_get_prompt,const char *,(struct menu *menu));
+P(menu_get_root_menu,struct menu *,(struct menu *menu));
+P(menu_get_parent_menu,struct menu *,(struct menu *menu));
+P(menu_has_help,bool,(struct menu *menu));
+P(menu_get_help,const char *,(struct menu *menu));
+
+/* symbol.c */
+P(symbol_hash,struct symbol *,[SYMBOL_HASHSIZE]);
+
+P(sym_lookup,struct symbol *,(const char *name, int isconst));
+P(sym_find,struct symbol *,(const char *name));
+P(sym_re_search,struct symbol **,(const char *pattern));
+P(sym_type_name,const char *,(enum symbol_type type));
+P(sym_calc_value,void,(struct symbol *sym));
+P(sym_get_type,enum symbol_type,(struct symbol *sym));
+P(sym_tristate_within_range,bool,(struct symbol *sym,tristate tri));
+P(sym_set_tristate_value,bool,(struct symbol *sym,tristate tri));
+P(sym_toggle_tristate_value,tristate,(struct symbol *sym));
+P(sym_string_valid,bool,(struct symbol *sym, const char *newval));
+P(sym_string_within_range,bool,(struct symbol *sym, const char *str));
+P(sym_set_string_value,bool,(struct symbol *sym, const char *newval));
+P(sym_is_changable,bool,(struct symbol *sym));
+P(sym_get_choice_prop,struct property *,(struct symbol *sym));
+P(sym_get_default_prop,struct property *,(struct symbol *sym));
+P(sym_get_string_value,const char *,(struct symbol *sym));
+
+P(prop_get_type_name,const char *,(enum prop_type type));
+
+/* expr.c */
+P(expr_compare_type,int,(enum expr_type t1, enum expr_type t2));
+P(expr_print,void,(struct expr *e, void (*fn)(void *, struct symbol *, const char *), void *data, int prevtoken));

Added: trunk/coreboot-v2/util/kconfig/lxdialog/BIG.FAT.WARNING
===================================================================
--- trunk/coreboot-v2/util/kconfig/lxdialog/BIG.FAT.WARNING	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/lxdialog/BIG.FAT.WARNING	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,4 @@
+This is NOT the official version of dialog.  This version has been
+significantly modified from the original.  It is for use by the Linux
+kernel configuration script.  Please do not bother Savio Lam with 
+questions about this program.

Added: trunk/coreboot-v2/util/kconfig/lxdialog/check-lxdialog.sh
===================================================================
--- trunk/coreboot-v2/util/kconfig/lxdialog/check-lxdialog.sh	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/lxdialog/check-lxdialog.sh	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,80 @@
+#!/bin/sh
+# Check ncurses compatibility
+
+# What library to link
+ldflags()
+{
+	for ext in so a dylib ; do
+		for lib in ncursesw ncurses curses ; do
+			$cc -print-file-name=lib${lib}.${ext} | grep / >/dev/null
+			if [ $? -eq 0 ]; then
+				echo "-l${lib}"
+				exit
+			fi
+		done
+	done
+	exit 1
+}
+
+# Where is ncurses.h?
+ccflags()
+{
+	if [ -f /usr/include/ncurses/ncurses.h ]; then
+		echo '-I/usr/include/ncurses -DCURSES_LOC="<ncurses.h>"'
+	elif [ -f /usr/include/ncurses/curses.h ]; then
+		echo '-I/usr/include/ncurses -DCURSES_LOC="<ncurses/curses.h>"'
+	elif [ -f /usr/include/ncurses.h ]; then
+		echo '-DCURSES_LOC="<ncurses.h>"'
+	else
+		echo '-DCURSES_LOC="<curses.h>"'
+	fi
+}
+
+# Temp file, try to clean up after us
+tmp=.lxdialog.tmp
+trap "rm -f $tmp" 0 1 2 3 15
+
+# Check if we can link to ncurses
+check() {
+	echo -e " #include CURSES_LOC \n main() {}" |
+	    $cc -xc - -o $tmp 2> /dev/null
+	if [ $? != 0 ]; then
+	    echo " *** Unable to find the ncurses libraries or the"       1>&2
+	    echo " *** required header files."                            1>&2
+	    echo " *** 'make menuconfig' requires the ncurses libraries." 1>&2
+	    echo " *** "                                                  1>&2
+	    echo " *** Install ncurses (ncurses-devel) and try again."    1>&2
+	    echo " *** "                                                  1>&2
+	    exit 1
+	fi
+}
+
+usage() {
+	printf "Usage: $0 [-check compiler options|-header|-library]\n"
+}
+
+if [ $# -eq 0 ]; then
+	usage
+	exit 1
+fi
+
+cc=""
+case "$1" in
+	"-check")
+		shift
+		cc="$@"
+		check
+		;;
+	"-ccflags")
+		ccflags
+		;;
+	"-ldflags")
+		shift
+		cc="$@"
+		ldflags
+		;;
+	"*")
+		usage
+		exit 1
+		;;
+esac

Added: trunk/coreboot-v2/util/kconfig/lxdialog/checklist.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/lxdialog/checklist.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/lxdialog/checklist.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,327 @@
+/*
+ *  checklist.c -- implements the checklist box
+ *
+ *  ORIGINAL AUTHOR: Savio Lam (lam836 at cs.cuhk.hk)
+ *     Stuart Herbert - S.Herbert at sheffield.ac.uk: radiolist extension
+ *     Alessandro Rubini - rubini at ipvvis.unipv.it: merged the two
+ *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap at cfw.com)
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version 2
+ *  of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include "dialog.h"
+
+static int list_width, check_x, item_x;
+
+/*
+ * Print list item
+ */
+static void print_item(WINDOW * win, int choice, int selected)
+{
+	int i;
+
+	/* Clear 'residue' of last item */
+	wattrset(win, dlg.menubox.atr);
+	wmove(win, choice, 0);
+	for (i = 0; i < list_width; i++)
+		waddch(win, ' ');
+
+	wmove(win, choice, check_x);
+	wattrset(win, selected ? dlg.check_selected.atr
+		 : dlg.check.atr);
+	wprintw(win, "(%c)", item_is_tag('X') ? 'X' : ' ');
+
+	wattrset(win, selected ? dlg.tag_selected.atr : dlg.tag.atr);
+	mvwaddch(win, choice, item_x, item_str()[0]);
+	wattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr);
+	waddstr(win, (char *)item_str() + 1);
+	if (selected) {
+		wmove(win, choice, check_x + 1);
+		wrefresh(win);
+	}
+}
+
+/*
+ * Print the scroll indicators.
+ */
+static void print_arrows(WINDOW * win, int choice, int item_no, int scroll,
+	     int y, int x, int height)
+{
+	wmove(win, y, x);
+
+	if (scroll > 0) {
+		wattrset(win, dlg.uarrow.atr);
+		waddch(win, ACS_UARROW);
+		waddstr(win, "(-)");
+	} else {
+		wattrset(win, dlg.menubox.atr);
+		waddch(win, ACS_HLINE);
+		waddch(win, ACS_HLINE);
+		waddch(win, ACS_HLINE);
+		waddch(win, ACS_HLINE);
+	}
+
+	y = y + height + 1;
+	wmove(win, y, x);
+
+	if ((height < item_no) && (scroll + choice < item_no - 1)) {
+		wattrset(win, dlg.darrow.atr);
+		waddch(win, ACS_DARROW);
+		waddstr(win, "(+)");
+	} else {
+		wattrset(win, dlg.menubox_border.atr);
+		waddch(win, ACS_HLINE);
+		waddch(win, ACS_HLINE);
+		waddch(win, ACS_HLINE);
+		waddch(win, ACS_HLINE);
+	}
+}
+
+/*
+ *  Display the termination buttons
+ */
+static void print_buttons(WINDOW * dialog, int height, int width, int selected)
+{
+	int x = width / 2 - 11;
+	int y = height - 2;
+
+	print_button(dialog, gettext("Select"), y, x, selected == 0);
+	print_button(dialog, gettext(" Help "), y, x + 14, selected == 1);
+
+	wmove(dialog, y, x + 1 + 14 * selected);
+	wrefresh(dialog);
+}
+
+/*
+ * Display a dialog box with a list of options that can be turned on or off
+ * in the style of radiolist (only one option turned on at a time).
+ */
+int dialog_checklist(const char *title, const char *prompt, int height,
+		     int width, int list_height)
+{
+	int i, x, y, box_x, box_y;
+	int key = 0, button = 0, choice = 0, scroll = 0, max_choice;
+	WINDOW *dialog, *list;
+
+	/* which item to highlight */
+	item_foreach() {
+		if (item_is_tag('X'))
+			choice = item_n();
+		if (item_is_selected()) {
+			choice = item_n();
+			break;
+		}
+	}
+
+do_resize:
+	if (getmaxy(stdscr) < (height + 6))
+		return -ERRDISPLAYTOOSMALL;
+	if (getmaxx(stdscr) < (width + 6))
+		return -ERRDISPLAYTOOSMALL;
+
+	max_choice = MIN(list_height, item_count());
+
+	/* center dialog box on screen */
+	x = (COLS - width) / 2;
+	y = (LINES - height) / 2;
+
+	draw_shadow(stdscr, y, x, height, width);
+
+	dialog = newwin(height, width, y, x);
+	keypad(dialog, TRUE);
+
+	draw_box(dialog, 0, 0, height, width,
+		 dlg.dialog.atr, dlg.border.atr);
+	wattrset(dialog, dlg.border.atr);
+	mvwaddch(dialog, height - 3, 0, ACS_LTEE);
+	for (i = 0; i < width - 2; i++)
+		waddch(dialog, ACS_HLINE);
+	wattrset(dialog, dlg.dialog.atr);
+	waddch(dialog, ACS_RTEE);
+
+	print_title(dialog, title, width);
+
+	wattrset(dialog, dlg.dialog.atr);
+	print_autowrap(dialog, prompt, width - 2, 1, 3);
+
+	list_width = width - 6;
+	box_y = height - list_height - 5;
+	box_x = (width - list_width) / 2 - 1;
+
+	/* create new window for the list */
+	list = subwin(dialog, list_height, list_width, y + box_y + 1,
+	              x + box_x + 1);
+
+	keypad(list, TRUE);
+
+	/* draw a box around the list items */
+	draw_box(dialog, box_y, box_x, list_height + 2, list_width + 2,
+	         dlg.menubox_border.atr, dlg.menubox.atr);
+
+	/* Find length of longest item in order to center checklist */
+	check_x = 0;
+	item_foreach()
+		check_x = MAX(check_x, strlen(item_str()) + 4);
+
+	check_x = (list_width - check_x) / 2;
+	item_x = check_x + 4;
+
+	if (choice >= list_height) {
+		scroll = choice - list_height + 1;
+		choice -= scroll;
+	}
+
+	/* Print the list */
+	for (i = 0; i < max_choice; i++) {
+		item_set(scroll + i);
+		print_item(list, i, i == choice);
+	}
+
+	print_arrows(dialog, choice, item_count(), scroll,
+		     box_y, box_x + check_x + 5, list_height);
+
+	print_buttons(dialog, height, width, 0);
+
+	wnoutrefresh(dialog);
+	wnoutrefresh(list);
+	doupdate();
+
+	while (key != KEY_ESC) {
+		key = wgetch(dialog);
+
+		for (i = 0; i < max_choice; i++) {
+			item_set(i + scroll);
+			if (toupper(key) == toupper(item_str()[0]))
+				break;
+		}
+
+		if (i < max_choice || key == KEY_UP || key == KEY_DOWN ||
+		    key == '+' || key == '-') {
+			if (key == KEY_UP || key == '-') {
+				if (!choice) {
+					if (!scroll)
+						continue;
+					/* Scroll list down */
+					if (list_height > 1) {
+						/* De-highlight current first item */
+						item_set(scroll);
+						print_item(list, 0, FALSE);
+						scrollok(list, TRUE);
+						wscrl(list, -1);
+						scrollok(list, FALSE);
+					}
+					scroll--;
+					item_set(scroll);
+					print_item(list, 0, TRUE);
+					print_arrows(dialog, choice, item_count(),
+						     scroll, box_y, box_x + check_x + 5, list_height);
+
+					wnoutrefresh(dialog);
+					wrefresh(list);
+
+					continue;	/* wait for another key press */
+				} else
+					i = choice - 1;
+			} else if (key == KEY_DOWN || key == '+') {
+				if (choice == max_choice - 1) {
+					if (scroll + choice >= item_count() - 1)
+						continue;
+					/* Scroll list up */
+					if (list_height > 1) {
+						/* De-highlight current last item before scrolling up */
+						item_set(scroll + max_choice - 1);
+						print_item(list,
+							    max_choice - 1,
+							    FALSE);
+						scrollok(list, TRUE);
+						wscrl(list, 1);
+						scrollok(list, FALSE);
+					}
+					scroll++;
+					item_set(scroll + max_choice - 1);
+					print_item(list, max_choice - 1, TRUE);
+
+					print_arrows(dialog, choice, item_count(),
+						     scroll, box_y, box_x + check_x + 5, list_height);
+
+					wnoutrefresh(dialog);
+					wrefresh(list);
+
+					continue;	/* wait for another key press */
+				} else
+					i = choice + 1;
+			}
+			if (i != choice) {
+				/* De-highlight current item */
+				item_set(scroll + choice);
+				print_item(list, choice, FALSE);
+				/* Highlight new item */
+				choice = i;
+				item_set(scroll + choice);
+				print_item(list, choice, TRUE);
+				wnoutrefresh(dialog);
+				wrefresh(list);
+			}
+			continue;	/* wait for another key press */
+		}
+		switch (key) {
+		case 'H':
+		case 'h':
+		case '?':
+			button = 1;
+			/* fall-through */
+		case 'S':
+		case 's':
+		case ' ':
+		case '\n':
+			item_foreach()
+				item_set_selected(0);
+			item_set(scroll + choice);
+			item_set_selected(1);
+			delwin(list);
+			delwin(dialog);
+			return button;
+		case TAB:
+		case KEY_LEFT:
+		case KEY_RIGHT:
+			button = ((key == KEY_LEFT ? --button : ++button) < 0)
+			    ? 1 : (button > 1 ? 0 : button);
+
+			print_buttons(dialog, height, width, button);
+			wrefresh(dialog);
+			break;
+		case 'X':
+		case 'x':
+			key = KEY_ESC;
+			break;
+		case KEY_ESC:
+			key = on_key_esc(dialog);
+			break;
+#ifdef NCURSES_VERSION
+		case KEY_RESIZE:
+			delwin(list);
+			delwin(dialog);
+			on_key_resize();
+			goto do_resize;
+#endif
+		}
+
+		/* Now, update everything... */
+		doupdate();
+	}
+	delwin(list);
+	delwin(dialog);
+	return key;		/* ESC pressed */
+}

Added: trunk/coreboot-v2/util/kconfig/lxdialog/dialog.h
===================================================================
--- trunk/coreboot-v2/util/kconfig/lxdialog/dialog.h	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/lxdialog/dialog.h	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,230 @@
+/*
+ *  dialog.h -- common declarations for all dialog modules
+ *
+ *  AUTHOR: Savio Lam (lam836 at cs.cuhk.hk)
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version 2
+ *  of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <sys/types.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <ctype.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdbool.h>
+
+#ifndef KBUILD_NO_NLS
+# include <libintl.h>
+#else
+# define gettext(Msgid) ((const char *) (Msgid))
+#endif
+
+#ifdef __sun__
+#define CURS_MACROS
+#endif
+#include CURSES_LOC
+
+/*
+ * Colors in ncurses 1.9.9e do not work properly since foreground and
+ * background colors are OR'd rather than separately masked.  This version
+ * of dialog was hacked to work with ncurses 1.9.9e, making it incompatible
+ * with standard curses.  The simplest fix (to make this work with standard
+ * curses) uses the wbkgdset() function, not used in the original hack.
+ * Turn it off if we're building with 1.9.9e, since it just confuses things.
+ */
+#if defined(NCURSES_VERSION) && defined(_NEED_WRAP) && !defined(GCC_PRINTFLIKE)
+#define OLD_NCURSES 1
+#undef  wbkgdset
+#define wbkgdset(w,p)		/*nothing */
+#else
+#define OLD_NCURSES 0
+#endif
+
+#define TR(params) _tracef params
+
+#define KEY_ESC 27
+#define TAB 9
+#define MAX_LEN 2048
+#define BUF_SIZE (10*1024)
+#define MIN(x,y) (x < y ? x : y)
+#define MAX(x,y) (x > y ? x : y)
+
+#ifndef ACS_ULCORNER
+#define ACS_ULCORNER '+'
+#endif
+#ifndef ACS_LLCORNER
+#define ACS_LLCORNER '+'
+#endif
+#ifndef ACS_URCORNER
+#define ACS_URCORNER '+'
+#endif
+#ifndef ACS_LRCORNER
+#define ACS_LRCORNER '+'
+#endif
+#ifndef ACS_HLINE
+#define ACS_HLINE '-'
+#endif
+#ifndef ACS_VLINE
+#define ACS_VLINE '|'
+#endif
+#ifndef ACS_LTEE
+#define ACS_LTEE '+'
+#endif
+#ifndef ACS_RTEE
+#define ACS_RTEE '+'
+#endif
+#ifndef ACS_UARROW
+#define ACS_UARROW '^'
+#endif
+#ifndef ACS_DARROW
+#define ACS_DARROW 'v'
+#endif
+
+/* error return codes */
+#define ERRDISPLAYTOOSMALL (KEY_MAX + 1)
+
+/*
+ *   Color definitions
+ */
+struct dialog_color {
+	chtype atr;	/* Color attribute */
+	int fg;		/* foreground */
+	int bg;		/* background */
+	int hl;		/* highlight this item */
+};
+
+struct dialog_info {
+	const char *backtitle;
+	struct dialog_color screen;
+	struct dialog_color shadow;
+	struct dialog_color dialog;
+	struct dialog_color title;
+	struct dialog_color border;
+	struct dialog_color button_active;
+	struct dialog_color button_inactive;
+	struct dialog_color button_key_active;
+	struct dialog_color button_key_inactive;
+	struct dialog_color button_label_active;
+	struct dialog_color button_label_inactive;
+	struct dialog_color inputbox;
+	struct dialog_color inputbox_border;
+	struct dialog_color searchbox;
+	struct dialog_color searchbox_title;
+	struct dialog_color searchbox_border;
+	struct dialog_color position_indicator;
+	struct dialog_color menubox;
+	struct dialog_color menubox_border;
+	struct dialog_color item;
+	struct dialog_color item_selected;
+	struct dialog_color tag;
+	struct dialog_color tag_selected;
+	struct dialog_color tag_key;
+	struct dialog_color tag_key_selected;
+	struct dialog_color check;
+	struct dialog_color check_selected;
+	struct dialog_color uarrow;
+	struct dialog_color darrow;
+};
+
+/*
+ * Global variables
+ */
+extern struct dialog_info dlg;
+extern char dialog_input_result[];
+
+/*
+ * Function prototypes
+ */
+
+/* item list as used by checklist and menubox */
+void item_reset(void);
+void item_make(const char *fmt, ...);
+void item_add_str(const char *fmt, ...);
+void item_set_tag(char tag);
+void item_set_data(void *p);
+void item_set_selected(int val);
+int item_activate_selected(void);
+void *item_data(void);
+char item_tag(void);
+
+/* item list manipulation for lxdialog use */
+#define MAXITEMSTR 200
+struct dialog_item {
+	char str[MAXITEMSTR];	/* promtp displayed */
+	char tag;
+	void *data;	/* pointer to menu item - used by menubox+checklist */
+	int selected;	/* Set to 1 by dialog_*() function if selected. */
+};
+
+/* list of lialog_items */
+struct dialog_list {
+	struct dialog_item node;
+	struct dialog_list *next;
+};
+
+extern struct dialog_list *item_cur;
+extern struct dialog_list item_nil;
+extern struct dialog_list *item_head;
+
+int item_count(void);
+void item_set(int n);
+int item_n(void);
+const char *item_str(void);
+int item_is_selected(void);
+int item_is_tag(char tag);
+#define item_foreach() \
+	for (item_cur = item_head ? item_head: item_cur; \
+	     item_cur && (item_cur != &item_nil); item_cur = item_cur->next)
+
+/* generic key handlers */
+int on_key_esc(WINDOW *win);
+int on_key_resize(void);
+
+int init_dialog(const char *backtitle);
+void set_dialog_backtitle(const char *backtitle);
+void end_dialog(int x, int y);
+void attr_clear(WINDOW * win, int height, int width, chtype attr);
+void dialog_clear(void);
+void print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x);
+void print_button(WINDOW * win, const char *label, int y, int x, int selected);
+void print_title(WINDOW *dialog, const char *title, int width);
+void draw_box(WINDOW * win, int y, int x, int height, int width, chtype box,
+	      chtype border);
+void draw_shadow(WINDOW * win, int y, int x, int height, int width);
+
+int first_alpha(const char *string, const char *exempt);
+int dialog_yesno(const char *title, const char *prompt, int height, int width);
+int dialog_msgbox(const char *title, const char *prompt, int height,
+		  int width, int pause);
+int dialog_textbox(const char *title, const char *file, int height, int width);
+int dialog_menu(const char *title, const char *prompt,
+		const void *selected, int *s_scroll);
+int dialog_checklist(const char *title, const char *prompt, int height,
+		     int width, int list_height);
+extern char dialog_input_result[];
+int dialog_inputbox(const char *title, const char *prompt, int height,
+		    int width, const char *init);
+
+/*
+ * This is the base for fictitious keys, which activate
+ * the buttons.
+ *
+ * Mouse-generated keys are the following:
+ *   -- the first 32 are used as numbers, in addition to '0'-'9'
+ *   -- the lowercase are used to signal mouse-enter events (M_EVENT + 'o')
+ *   -- uppercase chars are used to invoke the button (M_EVENT + 'O')
+ */
+#define M_EVENT (KEY_MAX+1)

Added: trunk/coreboot-v2/util/kconfig/lxdialog/inputbox.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/lxdialog/inputbox.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/lxdialog/inputbox.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,240 @@
+/*
+ *  inputbox.c -- implements the input box
+ *
+ *  ORIGINAL AUTHOR: Savio Lam (lam836 at cs.cuhk.hk)
+ *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap at cfw.com)
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version 2
+ *  of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include "dialog.h"
+
+char dialog_input_result[MAX_LEN + 1];
+
+/*
+ *  Print the termination buttons
+ */
+static void print_buttons(WINDOW * dialog, int height, int width, int selected)
+{
+	int x = width / 2 - 11;
+	int y = height - 2;
+
+	print_button(dialog, gettext("  Ok  "), y, x, selected == 0);
+	print_button(dialog, gettext(" Help "), y, x + 14, selected == 1);
+
+	wmove(dialog, y, x + 1 + 14 * selected);
+	wrefresh(dialog);
+}
+
+/*
+ * Display a dialog box for inputing a string
+ */
+int dialog_inputbox(const char *title, const char *prompt, int height, int width,
+                    const char *init)
+{
+	int i, x, y, box_y, box_x, box_width;
+	int input_x = 0, scroll = 0, key = 0, button = -1;
+	char *instr = dialog_input_result;
+	WINDOW *dialog;
+
+	if (!init)
+		instr[0] = '\0';
+	else
+		strcpy(instr, init);
+
+do_resize:
+	if (getmaxy(stdscr) <= (height - 2))
+		return -ERRDISPLAYTOOSMALL;
+	if (getmaxx(stdscr) <= (width - 2))
+		return -ERRDISPLAYTOOSMALL;
+
+	/* center dialog box on screen */
+	x = (COLS - width) / 2;
+	y = (LINES - height) / 2;
+
+	draw_shadow(stdscr, y, x, height, width);
+
+	dialog = newwin(height, width, y, x);
+	keypad(dialog, TRUE);
+
+	draw_box(dialog, 0, 0, height, width,
+		 dlg.dialog.atr, dlg.border.atr);
+	wattrset(dialog, dlg.border.atr);
+	mvwaddch(dialog, height - 3, 0, ACS_LTEE);
+	for (i = 0; i < width - 2; i++)
+		waddch(dialog, ACS_HLINE);
+	wattrset(dialog, dlg.dialog.atr);
+	waddch(dialog, ACS_RTEE);
+
+	print_title(dialog, title, width);
+
+	wattrset(dialog, dlg.dialog.atr);
+	print_autowrap(dialog, prompt, width - 2, 1, 3);
+
+	/* Draw the input field box */
+	box_width = width - 6;
+	getyx(dialog, y, x);
+	box_y = y + 2;
+	box_x = (width - box_width) / 2;
+	draw_box(dialog, y + 1, box_x - 1, 3, box_width + 2,
+		 dlg.border.atr, dlg.dialog.atr);
+
+	print_buttons(dialog, height, width, 0);
+
+	/* Set up the initial value */
+	wmove(dialog, box_y, box_x);
+	wattrset(dialog, dlg.inputbox.atr);
+
+	input_x = strlen(instr);
+
+	if (input_x >= box_width) {
+		scroll = input_x - box_width + 1;
+		input_x = box_width - 1;
+		for (i = 0; i < box_width - 1; i++)
+			waddch(dialog, instr[scroll + i]);
+	} else {
+		waddstr(dialog, instr);
+	}
+
+	wmove(dialog, box_y, box_x + input_x);
+
+	wrefresh(dialog);
+
+	while (key != KEY_ESC) {
+		key = wgetch(dialog);
+
+		if (button == -1) {	/* Input box selected */
+			switch (key) {
+			case TAB:
+			case KEY_UP:
+			case KEY_DOWN:
+				break;
+			case KEY_LEFT:
+				continue;
+			case KEY_RIGHT:
+				continue;
+			case KEY_BACKSPACE:
+			case 127:
+				if (input_x || scroll) {
+					wattrset(dialog, dlg.inputbox.atr);
+					if (!input_x) {
+						scroll = scroll < box_width - 1 ? 0 : scroll - (box_width - 1);
+						wmove(dialog, box_y, box_x);
+						for (i = 0; i < box_width; i++)
+							waddch(dialog,
+							       instr[scroll + input_x + i] ?
+							       instr[scroll + input_x + i] : ' ');
+						input_x = strlen(instr) - scroll;
+					} else
+						input_x--;
+					instr[scroll + input_x] = '\0';
+					mvwaddch(dialog, box_y, input_x + box_x, ' ');
+					wmove(dialog, box_y, input_x + box_x);
+					wrefresh(dialog);
+				}
+				continue;
+			default:
+				if (key < 0x100 && isprint(key)) {
+					if (scroll + input_x < MAX_LEN) {
+						wattrset(dialog, dlg.inputbox.atr);
+						instr[scroll + input_x] = key;
+						instr[scroll + input_x + 1] = '\0';
+						if (input_x == box_width - 1) {
+							scroll++;
+							wmove(dialog, box_y, box_x);
+							for (i = 0; i < box_width - 1; i++)
+								waddch(dialog, instr [scroll + i]);
+						} else {
+							wmove(dialog, box_y, input_x++ + box_x);
+							waddch(dialog, key);
+						}
+						wrefresh(dialog);
+					} else
+						flash();	/* Alarm user about overflow */
+					continue;
+				}
+			}
+		}
+		switch (key) {
+		case 'O':
+		case 'o':
+			delwin(dialog);
+			return 0;
+		case 'H':
+		case 'h':
+			delwin(dialog);
+			return 1;
+		case KEY_UP:
+		case KEY_LEFT:
+			switch (button) {
+			case -1:
+				button = 1;	/* Indicates "Cancel" button is selected */
+				print_buttons(dialog, height, width, 1);
+				break;
+			case 0:
+				button = -1;	/* Indicates input box is selected */
+				print_buttons(dialog, height, width, 0);
+				wmove(dialog, box_y, box_x + input_x);
+				wrefresh(dialog);
+				break;
+			case 1:
+				button = 0;	/* Indicates "OK" button is selected */
+				print_buttons(dialog, height, width, 0);
+				break;
+			}
+			break;
+		case TAB:
+		case KEY_DOWN:
+		case KEY_RIGHT:
+			switch (button) {
+			case -1:
+				button = 0;	/* Indicates "OK" button is selected */
+				print_buttons(dialog, height, width, 0);
+				break;
+			case 0:
+				button = 1;	/* Indicates "Cancel" button is selected */
+				print_buttons(dialog, height, width, 1);
+				break;
+			case 1:
+				button = -1;	/* Indicates input box is selected */
+				print_buttons(dialog, height, width, 0);
+				wmove(dialog, box_y, box_x + input_x);
+				wrefresh(dialog);
+				break;
+			}
+			break;
+		case ' ':
+		case '\n':
+			delwin(dialog);
+			return (button == -1 ? 0 : button);
+		case 'X':
+		case 'x':
+			key = KEY_ESC;
+			break;
+		case KEY_ESC:
+			key = on_key_esc(dialog);
+			break;
+#ifdef NCURSES_VERSION
+		case KEY_RESIZE:
+			delwin(dialog);
+			on_key_resize();
+			goto do_resize;
+#endif
+		}
+	}
+
+	delwin(dialog);
+	return KEY_ESC;		/* ESC pressed */
+}

Added: trunk/coreboot-v2/util/kconfig/lxdialog/menubox.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/lxdialog/menubox.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/lxdialog/menubox.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,436 @@
+/*
+ *  menubox.c -- implements the menu box
+ *
+ *  ORIGINAL AUTHOR: Savio Lam (lam836 at cs.cuhk.hk)
+ *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcapw at cfw.com)
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version 2
+ *  of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ *  Changes by Clifford Wolf (god at clifford.at)
+ *
+ *  [ 1998-06-13 ]
+ *
+ *    *)  A bugfix for the Page-Down problem
+ *
+ *    *)  Formerly when I used Page Down and Page Up, the cursor would be set 
+ *        to the first position in the menu box.  Now lxdialog is a bit
+ *        smarter and works more like other menu systems (just have a look at
+ *        it).
+ *
+ *    *)  Formerly if I selected something my scrolling would be broken because
+ *        lxdialog is re-invoked by the Menuconfig shell script, can't
+ *        remember the last scrolling position, and just sets it so that the
+ *        cursor is at the bottom of the box.  Now it writes the temporary file
+ *        lxdialog.scrltmp which contains this information. The file is
+ *        deleted by lxdialog if the user leaves a submenu or enters a new
+ *        one, but it would be nice if Menuconfig could make another "rm -f"
+ *        just to be sure.  Just try it out - you will recognise a difference!
+ *
+ *  [ 1998-06-14 ]
+ *
+ *    *)  Now lxdialog is crash-safe against broken "lxdialog.scrltmp" files
+ *        and menus change their size on the fly.
+ *
+ *    *)  If for some reason the last scrolling position is not saved by
+ *        lxdialog, it sets the scrolling so that the selected item is in the
+ *        middle of the menu box, not at the bottom.
+ *
+ * 02 January 1999, Michael Elizabeth Chastain (mec at shout.net)
+ * Reset 'scroll' to 0 if the value from lxdialog.scrltmp is bogus.
+ * This fixes a bug in Menuconfig where using ' ' to descend into menus
+ * would leave mis-synchronized lxdialog.scrltmp files lying around,
+ * fscanf would read in 'scroll', and eventually that value would get used.
+ */
+
+#include "dialog.h"
+
+static int menu_width, item_x;
+
+/*
+ * Print menu item
+ */
+static void do_print_item(WINDOW * win, const char *item, int line_y,
+                          int selected, int hotkey)
+{
+	int j;
+	char *menu_item = malloc(menu_width + 1);
+
+	strncpy(menu_item, item, menu_width - item_x);
+	menu_item[menu_width - item_x] = '\0';
+	j = first_alpha(menu_item, "YyNnMmHh");
+
+	/* Clear 'residue' of last item */
+	wattrset(win, dlg.menubox.atr);
+	wmove(win, line_y, 0);
+#if OLD_NCURSES
+	{
+		int i;
+		for (i = 0; i < menu_width; i++)
+			waddch(win, ' ');
+	}
+#else
+	wclrtoeol(win);
+#endif
+	wattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr);
+	mvwaddstr(win, line_y, item_x, menu_item);
+	if (hotkey) {
+		wattrset(win, selected ? dlg.tag_key_selected.atr
+			 : dlg.tag_key.atr);
+		mvwaddch(win, line_y, item_x + j, menu_item[j]);
+	}
+	if (selected) {
+		wmove(win, line_y, item_x + 1);
+	}
+	free(menu_item);
+	wrefresh(win);
+}
+
+#define print_item(index, choice, selected)				\
+do {									\
+	item_set(index);						\
+	do_print_item(menu, item_str(), choice, selected, !item_is_tag(':')); \
+} while (0)
+
+/*
+ * Print the scroll indicators.
+ */
+static void print_arrows(WINDOW * win, int item_no, int scroll, int y, int x,
+			 int height)
+{
+	int cur_y, cur_x;
+
+	getyx(win, cur_y, cur_x);
+
+	wmove(win, y, x);
+
+	if (scroll > 0) {
+		wattrset(win, dlg.uarrow.atr);
+		waddch(win, ACS_UARROW);
+		waddstr(win, "(-)");
+	} else {
+		wattrset(win, dlg.menubox.atr);
+		waddch(win, ACS_HLINE);
+		waddch(win, ACS_HLINE);
+		waddch(win, ACS_HLINE);
+		waddch(win, ACS_HLINE);
+	}
+
+	y = y + height + 1;
+	wmove(win, y, x);
+	wrefresh(win);
+
+	if ((height < item_no) && (scroll + height < item_no)) {
+		wattrset(win, dlg.darrow.atr);
+		waddch(win, ACS_DARROW);
+		waddstr(win, "(+)");
+	} else {
+		wattrset(win, dlg.menubox_border.atr);
+		waddch(win, ACS_HLINE);
+		waddch(win, ACS_HLINE);
+		waddch(win, ACS_HLINE);
+		waddch(win, ACS_HLINE);
+	}
+
+	wmove(win, cur_y, cur_x);
+	wrefresh(win);
+}
+
+/*
+ * Display the termination buttons.
+ */
+static void print_buttons(WINDOW * win, int height, int width, int selected)
+{
+	int x = width / 2 - 16;
+	int y = height - 2;
+
+	print_button(win, gettext("Select"), y, x, selected == 0);
+	print_button(win, gettext(" Exit "), y, x + 12, selected == 1);
+	print_button(win, gettext(" Help "), y, x + 24, selected == 2);
+
+	wmove(win, y, x + 1 + 12 * selected);
+	wrefresh(win);
+}
+
+/* scroll up n lines (n may be negative) */
+static void do_scroll(WINDOW *win, int *scroll, int n)
+{
+	/* Scroll menu up */
+	scrollok(win, TRUE);
+	wscrl(win, n);
+	scrollok(win, FALSE);
+	*scroll = *scroll + n;
+	wrefresh(win);
+}
+
+/*
+ * Display a menu for choosing among a number of options
+ */
+int dialog_menu(const char *title, const char *prompt,
+                const void *selected, int *s_scroll)
+{
+	int i, j, x, y, box_x, box_y;
+	int height, width, menu_height;
+	int key = 0, button = 0, scroll = 0, choice = 0;
+	int first_item =  0, max_choice;
+	WINDOW *dialog, *menu;
+
+do_resize:
+	height = getmaxy(stdscr);
+	width = getmaxx(stdscr);
+	if (height < 15 || width < 65)
+		return -ERRDISPLAYTOOSMALL;
+
+	height -= 4;
+	width  -= 5;
+	menu_height = height - 10;
+
+	max_choice = MIN(menu_height, item_count());
+
+	/* center dialog box on screen */
+	x = (COLS - width) / 2;
+	y = (LINES - height) / 2;
+
+	draw_shadow(stdscr, y, x, height, width);
+
+	dialog = newwin(height, width, y, x);
+	keypad(dialog, TRUE);
+
+	draw_box(dialog, 0, 0, height, width,
+		 dlg.dialog.atr, dlg.border.atr);
+	wattrset(dialog, dlg.border.atr);
+	mvwaddch(dialog, height - 3, 0, ACS_LTEE);
+	for (i = 0; i < width - 2; i++)
+		waddch(dialog, ACS_HLINE);
+	wattrset(dialog, dlg.dialog.atr);
+	wbkgdset(dialog, dlg.dialog.atr & A_COLOR);
+	waddch(dialog, ACS_RTEE);
+
+	print_title(dialog, title, width);
+
+	wattrset(dialog, dlg.dialog.atr);
+	print_autowrap(dialog, prompt, width - 2, 1, 3);
+
+	menu_width = width - 6;
+	box_y = height - menu_height - 5;
+	box_x = (width - menu_width) / 2 - 1;
+
+	/* create new window for the menu */
+	menu = subwin(dialog, menu_height, menu_width,
+		      y + box_y + 1, x + box_x + 1);
+	keypad(menu, TRUE);
+
+	/* draw a box around the menu items */
+	draw_box(dialog, box_y, box_x, menu_height + 2, menu_width + 2,
+		 dlg.menubox_border.atr, dlg.menubox.atr);
+
+	if (menu_width >= 80)
+		item_x = (menu_width - 70) / 2;
+	else
+		item_x = 4;
+
+	/* Set choice to default item */
+	item_foreach()
+		if (selected && (selected == item_data()))
+			choice = item_n();
+	/* get the saved scroll info */
+	scroll = *s_scroll;
+	if ((scroll <= choice) && (scroll + max_choice > choice) &&
+	   (scroll >= 0) && (scroll + max_choice <= item_count())) {
+		first_item = scroll;
+		choice = choice - scroll;
+	} else {
+		scroll = 0;
+	}
+	if ((choice >= max_choice)) {
+		if (choice >= item_count() - max_choice / 2)
+			scroll = first_item = item_count() - max_choice;
+		else
+			scroll = first_item = choice - max_choice / 2;
+		choice = choice - scroll;
+	}
+
+	/* Print the menu */
+	for (i = 0; i < max_choice; i++) {
+		print_item(first_item + i, i, i == choice);
+	}
+
+	wnoutrefresh(menu);
+
+	print_arrows(dialog, item_count(), scroll,
+		     box_y, box_x + item_x + 1, menu_height);
+
+	print_buttons(dialog, height, width, 0);
+	wmove(menu, choice, item_x + 1);
+	wrefresh(menu);
+
+	while (key != KEY_ESC) {
+		key = wgetch(menu);
+
+		if (key < 256 && isalpha(key))
+			key = tolower(key);
+
+		if (strchr("ynmh", key))
+			i = max_choice;
+		else {
+			for (i = choice + 1; i < max_choice; i++) {
+				item_set(scroll + i);
+				j = first_alpha(item_str(), "YyNnMmHh");
+				if (key == tolower(item_str()[j]))
+					break;
+			}
+			if (i == max_choice)
+				for (i = 0; i < max_choice; i++) {
+					item_set(scroll + i);
+					j = first_alpha(item_str(), "YyNnMmHh");
+					if (key == tolower(item_str()[j]))
+						break;
+				}
+		}
+
+		if (i < max_choice ||
+		    key == KEY_UP || key == KEY_DOWN ||
+		    key == '-' || key == '+' ||
+		    key == KEY_PPAGE || key == KEY_NPAGE) {
+			/* Remove highligt of current item */
+			print_item(scroll + choice, choice, FALSE);
+
+			if (key == KEY_UP || key == '-') {
+				if (choice < 2 && scroll) {
+					/* Scroll menu down */
+					do_scroll(menu, &scroll, -1);
+
+					print_item(scroll, 0, FALSE);
+				} else
+					choice = MAX(choice - 1, 0);
+
+			} else if (key == KEY_DOWN || key == '+') {
+				print_item(scroll+choice, choice, FALSE);
+
+				if ((choice > max_choice - 3) &&
+				    (scroll + max_choice < item_count())) {
+					/* Scroll menu up */
+					do_scroll(menu, &scroll, 1);
+
+					print_item(scroll+max_choice - 1,
+						   max_choice - 1, FALSE);
+				} else
+					choice = MIN(choice + 1, max_choice - 1);
+
+			} else if (key == KEY_PPAGE) {
+				scrollok(menu, TRUE);
+				for (i = 0; (i < max_choice); i++) {
+					if (scroll > 0) {
+						do_scroll(menu, &scroll, -1);
+						print_item(scroll, 0, FALSE);
+					} else {
+						if (choice > 0)
+							choice--;
+					}
+				}
+
+			} else if (key == KEY_NPAGE) {
+				for (i = 0; (i < max_choice); i++) {
+					if (scroll + max_choice < item_count()) {
+						do_scroll(menu, &scroll, 1);
+						print_item(scroll+max_choice-1,
+							   max_choice - 1, FALSE);
+					} else {
+						if (choice + 1 < max_choice)
+							choice++;
+					}
+				}
+			} else
+				choice = i;
+
+			print_item(scroll + choice, choice, TRUE);
+
+			print_arrows(dialog, item_count(), scroll,
+				     box_y, box_x + item_x + 1, menu_height);
+
+			wnoutrefresh(dialog);
+			wrefresh(menu);
+
+			continue;	/* wait for another key press */
+		}
+
+		switch (key) {
+		case KEY_LEFT:
+		case TAB:
+		case KEY_RIGHT:
+			button = ((key == KEY_LEFT ? --button : ++button) < 0)
+			    ? 2 : (button > 2 ? 0 : button);
+
+			print_buttons(dialog, height, width, button);
+			wrefresh(menu);
+			break;
+		case ' ':
+		case 's':
+		case 'y':
+		case 'n':
+		case 'm':
+		case '/':
+			/* save scroll info */
+			*s_scroll = scroll;
+			delwin(menu);
+			delwin(dialog);
+			item_set(scroll + choice);
+			item_set_selected(1);
+			switch (key) {
+			case 's':
+				return 3;
+			case 'y':
+				return 3;
+			case 'n':
+				return 4;
+			case 'm':
+				return 5;
+			case ' ':
+				return 6;
+			case '/':
+				return 7;
+			}
+			return 0;
+		case 'h':
+		case '?':
+			button = 2;
+		case '\n':
+			*s_scroll = scroll;
+			delwin(menu);
+			delwin(dialog);
+			item_set(scroll + choice);
+			item_set_selected(1);
+			return button;
+		case 'e':
+		case 'x':
+			key = KEY_ESC;
+			break;
+		case KEY_ESC:
+			key = on_key_esc(menu);
+			break;
+#ifdef NCURSES_VERSION
+		case KEY_RESIZE:
+			on_key_resize();
+			delwin(menu);
+			delwin(dialog);
+			goto do_resize;
+#endif
+		}
+	}
+	delwin(menu);
+	delwin(dialog);
+	return key;		/* ESC pressed */
+}

Added: trunk/coreboot-v2/util/kconfig/lxdialog/textbox.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/lxdialog/textbox.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/lxdialog/textbox.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,393 @@
+/*
+ *  textbox.c -- implements the text box
+ *
+ *  ORIGINAL AUTHOR: Savio Lam (lam836 at cs.cuhk.hk)
+ *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap at cfw.com)
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version 2
+ *  of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include "dialog.h"
+
+static void back_lines(int n);
+static void print_page(WINDOW * win, int height, int width);
+static void print_line(WINDOW * win, int row, int width);
+static char *get_line(void);
+static void print_position(WINDOW * win);
+
+static int hscroll;
+static int begin_reached, end_reached, page_length;
+static const char *buf;
+static const char *page;
+
+/*
+ * refresh window content
+ */
+static void refresh_text_box(WINDOW *dialog, WINDOW *box, int boxh, int boxw,
+							  int cur_y, int cur_x)
+{
+	print_page(box, boxh, boxw);
+	print_position(dialog);
+	wmove(dialog, cur_y, cur_x);	/* Restore cursor position */
+	wrefresh(dialog);
+}
+
+
+/*
+ * Display text from a file in a dialog box.
+ */
+int dialog_textbox(const char *title, const char *tbuf,
+		   int initial_height, int initial_width)
+{
+	int i, x, y, cur_x, cur_y, key = 0;
+	int height, width, boxh, boxw;
+	int passed_end;
+	WINDOW *dialog, *box;
+
+	begin_reached = 1;
+	end_reached = 0;
+	page_length = 0;
+	hscroll = 0;
+	buf = tbuf;
+	page = buf;	/* page is pointer to start of page to be displayed */
+
+do_resize:
+	getmaxyx(stdscr, height, width);
+	if (height < 8 || width < 8)
+		return -ERRDISPLAYTOOSMALL;
+	if (initial_height != 0)
+		height = initial_height;
+	else
+		if (height > 4)
+			height -= 4;
+		else
+			height = 0;
+	if (initial_width != 0)
+		width = initial_width;
+	else
+		if (width > 5)
+			width -= 5;
+		else
+			width = 0;
+
+	/* center dialog box on screen */
+	x = (COLS - width) / 2;
+	y = (LINES - height) / 2;
+
+	draw_shadow(stdscr, y, x, height, width);
+
+	dialog = newwin(height, width, y, x);
+	keypad(dialog, TRUE);
+
+	/* Create window for box region, used for scrolling text */
+	boxh = height - 4;
+	boxw = width - 2;
+	box = subwin(dialog, boxh, boxw, y + 1, x + 1);
+	wattrset(box, dlg.dialog.atr);
+	wbkgdset(box, dlg.dialog.atr & A_COLOR);
+
+	keypad(box, TRUE);
+
+	/* register the new window, along with its borders */
+	draw_box(dialog, 0, 0, height, width,
+		 dlg.dialog.atr, dlg.border.atr);
+
+	wattrset(dialog, dlg.border.atr);
+	mvwaddch(dialog, height - 3, 0, ACS_LTEE);
+	for (i = 0; i < width - 2; i++)
+		waddch(dialog, ACS_HLINE);
+	wattrset(dialog, dlg.dialog.atr);
+	wbkgdset(dialog, dlg.dialog.atr & A_COLOR);
+	waddch(dialog, ACS_RTEE);
+
+	print_title(dialog, title, width);
+
+	print_button(dialog, gettext(" Exit "), height - 2, width / 2 - 4, TRUE);
+	wnoutrefresh(dialog);
+	getyx(dialog, cur_y, cur_x);	/* Save cursor position */
+
+	/* Print first page of text */
+	attr_clear(box, boxh, boxw, dlg.dialog.atr);
+	refresh_text_box(dialog, box, boxh, boxw, cur_y, cur_x);
+
+	while ((key != KEY_ESC) && (key != '\n')) {
+		key = wgetch(dialog);
+		switch (key) {
+		case 'E':	/* Exit */
+		case 'e':
+		case 'X':
+		case 'x':
+			delwin(box);
+			delwin(dialog);
+			return 0;
+		case 'g':	/* First page */
+		case KEY_HOME:
+			if (!begin_reached) {
+				begin_reached = 1;
+				page = buf;
+				refresh_text_box(dialog, box, boxh, boxw,
+						 cur_y, cur_x);
+			}
+			break;
+		case 'G':	/* Last page */
+		case KEY_END:
+
+			end_reached = 1;
+			/* point to last char in buf */
+			page = buf + strlen(buf);
+			back_lines(boxh);
+			refresh_text_box(dialog, box, boxh, boxw,
+					 cur_y, cur_x);
+			break;
+		case 'K':	/* Previous line */
+		case 'k':
+		case KEY_UP:
+			if (!begin_reached) {
+				back_lines(page_length + 1);
+
+				/* We don't call print_page() here but use
+				 * scrolling to ensure faster screen update.
+				 * However, 'end_reached' and 'page_length'
+				 * should still be updated, and 'page' should
+				 * point to start of next page. This is done
+				 * by calling get_line() in the following
+				 * 'for' loop. */
+				scrollok(box, TRUE);
+				wscrl(box, -1);	/* Scroll box region down one line */
+				scrollok(box, FALSE);
+				page_length = 0;
+				passed_end = 0;
+				for (i = 0; i < boxh; i++) {
+					if (!i) {
+						/* print first line of page */
+						print_line(box, 0, boxw);
+						wnoutrefresh(box);
+					} else
+						/* Called to update 'end_reached' and 'page' */
+						get_line();
+					if (!passed_end)
+						page_length++;
+					if (end_reached && !passed_end)
+						passed_end = 1;
+				}
+
+				print_position(dialog);
+				wmove(dialog, cur_y, cur_x);	/* Restore cursor position */
+				wrefresh(dialog);
+			}
+			break;
+		case 'B':	/* Previous page */
+		case 'b':
+		case KEY_PPAGE:
+			if (begin_reached)
+				break;
+			back_lines(page_length + boxh);
+			refresh_text_box(dialog, box, boxh, boxw,
+					 cur_y, cur_x);
+			break;
+		case 'J':	/* Next line */
+		case 'j':
+		case KEY_DOWN:
+			if (!end_reached) {
+				begin_reached = 0;
+				scrollok(box, TRUE);
+				scroll(box);	/* Scroll box region up one line */
+				scrollok(box, FALSE);
+				print_line(box, boxh - 1, boxw);
+				wnoutrefresh(box);
+				print_position(dialog);
+				wmove(dialog, cur_y, cur_x);	/* Restore cursor position */
+				wrefresh(dialog);
+			}
+			break;
+		case KEY_NPAGE:	/* Next page */
+		case ' ':
+			if (end_reached)
+				break;
+
+			begin_reached = 0;
+			refresh_text_box(dialog, box, boxh, boxw,
+					 cur_y, cur_x);
+			break;
+		case '0':	/* Beginning of line */
+		case 'H':	/* Scroll left */
+		case 'h':
+		case KEY_LEFT:
+			if (hscroll <= 0)
+				break;
+
+			if (key == '0')
+				hscroll = 0;
+			else
+				hscroll--;
+			/* Reprint current page to scroll horizontally */
+			back_lines(page_length);
+			refresh_text_box(dialog, box, boxh, boxw,
+					 cur_y, cur_x);
+			break;
+		case 'L':	/* Scroll right */
+		case 'l':
+		case KEY_RIGHT:
+			if (hscroll >= MAX_LEN)
+				break;
+			hscroll++;
+			/* Reprint current page to scroll horizontally */
+			back_lines(page_length);
+			refresh_text_box(dialog, box, boxh, boxw,
+					 cur_y, cur_x);
+			break;
+		case KEY_ESC:
+			key = on_key_esc(dialog);
+			break;
+#ifdef NCURSES_VERSION
+		case KEY_RESIZE:
+			back_lines(height);
+			delwin(box);
+			delwin(dialog);
+			on_key_resize();
+			goto do_resize;
+#endif
+		}
+	}
+	delwin(box);
+	delwin(dialog);
+	return key;		/* ESC pressed */
+}
+
+/*
+ * Go back 'n' lines in text. Called by dialog_textbox().
+ * 'page' will be updated to point to the desired line in 'buf'.
+ */
+static void back_lines(int n)
+{
+	int i;
+
+	begin_reached = 0;
+	/* Go back 'n' lines */
+	for (i = 0; i < n; i++) {
+		if (*page == '\0') {
+			if (end_reached) {
+				end_reached = 0;
+				continue;
+			}
+		}
+		if (page == buf) {
+			begin_reached = 1;
+			return;
+		}
+		page--;
+		do {
+			if (page == buf) {
+				begin_reached = 1;
+				return;
+			}
+			page--;
+		} while (*page != '\n');
+		page++;
+	}
+}
+
+/*
+ * Print a new page of text. Called by dialog_textbox().
+ */
+static void print_page(WINDOW * win, int height, int width)
+{
+	int i, passed_end = 0;
+
+	page_length = 0;
+	for (i = 0; i < height; i++) {
+		print_line(win, i, width);
+		if (!passed_end)
+			page_length++;
+		if (end_reached && !passed_end)
+			passed_end = 1;
+	}
+	wnoutrefresh(win);
+}
+
+/*
+ * Print a new line of text. Called by dialog_textbox() and print_page().
+ */
+static void print_line(WINDOW * win, int row, int width)
+{
+	int y, x;
+	char *line;
+
+	line = get_line();
+	line += MIN(strlen(line), hscroll);	/* Scroll horizontally */
+	wmove(win, row, 0);	/* move cursor to correct line */
+	waddch(win, ' ');
+	waddnstr(win, line, MIN(strlen(line), width - 2));
+
+	getyx(win, y, x);
+	/* Clear 'residue' of previous line */
+#if OLD_NCURSES
+	{
+		int i;
+		for (i = 0; i < width - x; i++)
+			waddch(win, ' ');
+	}
+#else
+	wclrtoeol(win);
+#endif
+}
+
+/*
+ * Return current line of text. Called by dialog_textbox() and print_line().
+ * 'page' should point to start of current line before calling, and will be
+ * updated to point to start of next line.
+ */
+static char *get_line(void)
+{
+	int i = 0;
+	static char line[MAX_LEN + 1];
+
+	end_reached = 0;
+	while (*page != '\n') {
+		if (*page == '\0') {
+			if (!end_reached) {
+				end_reached = 1;
+				break;
+			}
+		} else if (i < MAX_LEN)
+			line[i++] = *(page++);
+		else {
+			/* Truncate lines longer than MAX_LEN characters */
+			if (i == MAX_LEN)
+				line[i++] = '\0';
+			page++;
+		}
+	}
+	if (i <= MAX_LEN)
+		line[i] = '\0';
+	if (!end_reached)
+		page++;		/* move pass '\n' */
+
+	return line;
+}
+
+/*
+ * Print current position
+ */
+static void print_position(WINDOW * win)
+{
+	int percent;
+
+	wattrset(win, dlg.position_indicator.atr);
+	wbkgdset(win, dlg.position_indicator.atr & A_COLOR);
+	percent = (page - buf) * 100 / strlen(buf);
+	wmove(win, getmaxy(win) - 3, getmaxx(win) - 9);
+	wprintw(win, "(%3d%%)", percent);
+}

Added: trunk/coreboot-v2/util/kconfig/lxdialog/util.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/lxdialog/util.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/lxdialog/util.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,658 @@
+/*
+ *  util.c
+ *
+ *  ORIGINAL AUTHOR: Savio Lam (lam836 at cs.cuhk.hk)
+ *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap at cfw.com)
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version 2
+ *  of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include "dialog.h"
+#include <stdarg.h>
+
+struct dialog_info dlg;
+
+static void set_mono_theme(void)
+{
+	dlg.screen.atr = A_NORMAL;
+	dlg.shadow.atr = A_NORMAL;
+	dlg.dialog.atr = A_NORMAL;
+	dlg.title.atr = A_BOLD;
+	dlg.border.atr = A_NORMAL;
+	dlg.button_active.atr = A_REVERSE;
+	dlg.button_inactive.atr = A_DIM;
+	dlg.button_key_active.atr = A_REVERSE;
+	dlg.button_key_inactive.atr = A_BOLD;
+	dlg.button_label_active.atr = A_REVERSE;
+	dlg.button_label_inactive.atr = A_NORMAL;
+	dlg.inputbox.atr = A_NORMAL;
+	dlg.inputbox_border.atr = A_NORMAL;
+	dlg.searchbox.atr = A_NORMAL;
+	dlg.searchbox_title.atr = A_BOLD;
+	dlg.searchbox_border.atr = A_NORMAL;
+	dlg.position_indicator.atr = A_BOLD;
+	dlg.menubox.atr = A_NORMAL;
+	dlg.menubox_border.atr = A_NORMAL;
+	dlg.item.atr = A_NORMAL;
+	dlg.item_selected.atr = A_REVERSE;
+	dlg.tag.atr = A_BOLD;
+	dlg.tag_selected.atr = A_REVERSE;
+	dlg.tag_key.atr = A_BOLD;
+	dlg.tag_key_selected.atr = A_REVERSE;
+	dlg.check.atr = A_BOLD;
+	dlg.check_selected.atr = A_REVERSE;
+	dlg.uarrow.atr = A_BOLD;
+	dlg.darrow.atr = A_BOLD;
+}
+
+#define DLG_COLOR(dialog, f, b, h) \
+do {                               \
+	dlg.dialog.fg = (f);       \
+	dlg.dialog.bg = (b);       \
+	dlg.dialog.hl = (h);       \
+} while (0)
+
+static void set_classic_theme(void)
+{
+	DLG_COLOR(screen,                COLOR_CYAN,   COLOR_BLUE,   true);
+	DLG_COLOR(shadow,                COLOR_BLACK,  COLOR_BLACK,  true);
+	DLG_COLOR(dialog,                COLOR_BLACK,  COLOR_WHITE,  false);
+	DLG_COLOR(title,                 COLOR_YELLOW, COLOR_WHITE,  true);
+	DLG_COLOR(border,                COLOR_WHITE,  COLOR_WHITE,  true);
+	DLG_COLOR(button_active,         COLOR_WHITE,  COLOR_BLUE,   true);
+	DLG_COLOR(button_inactive,       COLOR_BLACK,  COLOR_WHITE,  false);
+	DLG_COLOR(button_key_active,     COLOR_WHITE,  COLOR_BLUE,   true);
+	DLG_COLOR(button_key_inactive,   COLOR_RED,    COLOR_WHITE,  false);
+	DLG_COLOR(button_label_active,   COLOR_YELLOW, COLOR_BLUE,   true);
+	DLG_COLOR(button_label_inactive, COLOR_BLACK,  COLOR_WHITE,  true);
+	DLG_COLOR(inputbox,              COLOR_BLACK,  COLOR_WHITE,  false);
+	DLG_COLOR(inputbox_border,       COLOR_BLACK,  COLOR_WHITE,  false);
+	DLG_COLOR(searchbox,             COLOR_BLACK,  COLOR_WHITE,  false);
+	DLG_COLOR(searchbox_title,       COLOR_YELLOW, COLOR_WHITE,  true);
+	DLG_COLOR(searchbox_border,      COLOR_WHITE,  COLOR_WHITE,  true);
+	DLG_COLOR(position_indicator,    COLOR_YELLOW, COLOR_WHITE,  true);
+	DLG_COLOR(menubox,               COLOR_BLACK,  COLOR_WHITE,  false);
+	DLG_COLOR(menubox_border,        COLOR_WHITE,  COLOR_WHITE,  true);
+	DLG_COLOR(item,                  COLOR_BLACK,  COLOR_WHITE,  false);
+	DLG_COLOR(item_selected,         COLOR_WHITE,  COLOR_BLUE,   true);
+	DLG_COLOR(tag,                   COLOR_YELLOW, COLOR_WHITE,  true);
+	DLG_COLOR(tag_selected,          COLOR_YELLOW, COLOR_BLUE,   true);
+	DLG_COLOR(tag_key,               COLOR_YELLOW, COLOR_WHITE,  true);
+	DLG_COLOR(tag_key_selected,      COLOR_YELLOW, COLOR_BLUE,   true);
+	DLG_COLOR(check,                 COLOR_BLACK,  COLOR_WHITE,  false);
+	DLG_COLOR(check_selected,        COLOR_WHITE,  COLOR_BLUE,   true);
+	DLG_COLOR(uarrow,                COLOR_GREEN,  COLOR_WHITE,  true);
+	DLG_COLOR(darrow,                COLOR_GREEN,  COLOR_WHITE,  true);
+}
+
+static void set_blackbg_theme(void)
+{
+	DLG_COLOR(screen, COLOR_RED,   COLOR_BLACK, true);
+	DLG_COLOR(shadow, COLOR_BLACK, COLOR_BLACK, false);
+	DLG_COLOR(dialog, COLOR_WHITE, COLOR_BLACK, false);
+	DLG_COLOR(title,  COLOR_RED,   COLOR_BLACK, false);
+	DLG_COLOR(border, COLOR_BLACK, COLOR_BLACK, true);
+
+	DLG_COLOR(button_active,         COLOR_YELLOW, COLOR_RED,   false);
+	DLG_COLOR(button_inactive,       COLOR_YELLOW, COLOR_BLACK, false);
+	DLG_COLOR(button_key_active,     COLOR_YELLOW, COLOR_RED,   true);
+	DLG_COLOR(button_key_inactive,   COLOR_RED,    COLOR_BLACK, false);
+	DLG_COLOR(button_label_active,   COLOR_WHITE,  COLOR_RED,   false);
+	DLG_COLOR(button_label_inactive, COLOR_BLACK,  COLOR_BLACK, true);
+
+	DLG_COLOR(inputbox,         COLOR_YELLOW, COLOR_BLACK, false);
+	DLG_COLOR(inputbox_border,  COLOR_YELLOW, COLOR_BLACK, false);
+
+	DLG_COLOR(searchbox,        COLOR_YELLOW, COLOR_BLACK, false);
+	DLG_COLOR(searchbox_title,  COLOR_YELLOW, COLOR_BLACK, true);
+	DLG_COLOR(searchbox_border, COLOR_BLACK,  COLOR_BLACK, true);
+
+	DLG_COLOR(position_indicator, COLOR_RED, COLOR_BLACK,  false);
+
+	DLG_COLOR(menubox,          COLOR_YELLOW, COLOR_BLACK, false);
+	DLG_COLOR(menubox_border,   COLOR_BLACK,  COLOR_BLACK, true);
+
+	DLG_COLOR(item,             COLOR_WHITE, COLOR_BLACK, false);
+	DLG_COLOR(item_selected,    COLOR_WHITE, COLOR_RED,   false);
+
+	DLG_COLOR(tag,              COLOR_RED,    COLOR_BLACK, false);
+	DLG_COLOR(tag_selected,     COLOR_YELLOW, COLOR_RED,   true);
+	DLG_COLOR(tag_key,          COLOR_RED,    COLOR_BLACK, false);
+	DLG_COLOR(tag_key_selected, COLOR_YELLOW, COLOR_RED,   true);
+
+	DLG_COLOR(check,            COLOR_YELLOW, COLOR_BLACK, false);
+	DLG_COLOR(check_selected,   COLOR_YELLOW, COLOR_RED,   true);
+
+	DLG_COLOR(uarrow, COLOR_RED, COLOR_BLACK, false);
+	DLG_COLOR(darrow, COLOR_RED, COLOR_BLACK, false);
+}
+
+static void set_bluetitle_theme(void)
+{
+	set_classic_theme();
+	DLG_COLOR(title,               COLOR_BLUE,   COLOR_WHITE, true);
+	DLG_COLOR(button_key_active,   COLOR_YELLOW, COLOR_BLUE,  true);
+	DLG_COLOR(button_label_active, COLOR_WHITE,  COLOR_BLUE,  true);
+	DLG_COLOR(searchbox_title,     COLOR_BLUE,   COLOR_WHITE, true);
+	DLG_COLOR(position_indicator,  COLOR_BLUE,   COLOR_WHITE, true);
+	DLG_COLOR(tag,                 COLOR_BLUE,   COLOR_WHITE, true);
+	DLG_COLOR(tag_key,             COLOR_BLUE,   COLOR_WHITE, true);
+
+}
+
+/*
+ * Select color theme
+ */
+static int set_theme(const char *theme)
+{
+	int use_color = 1;
+	if (!theme)
+		set_bluetitle_theme();
+	else if (strcmp(theme, "classic") == 0)
+		set_classic_theme();
+	else if (strcmp(theme, "bluetitle") == 0)
+		set_bluetitle_theme();
+	else if (strcmp(theme, "blackbg") == 0)
+		set_blackbg_theme();
+	else if (strcmp(theme, "mono") == 0)
+		use_color = 0;
+
+	return use_color;
+}
+
+static void init_one_color(struct dialog_color *color)
+{
+	static int pair = 0;
+
+	pair++;
+	init_pair(pair, color->fg, color->bg);
+	if (color->hl)
+		color->atr = A_BOLD | COLOR_PAIR(pair);
+	else
+		color->atr = COLOR_PAIR(pair);
+}
+
+static void init_dialog_colors(void)
+{
+	init_one_color(&dlg.screen);
+	init_one_color(&dlg.shadow);
+	init_one_color(&dlg.dialog);
+	init_one_color(&dlg.title);
+	init_one_color(&dlg.border);
+	init_one_color(&dlg.button_active);
+	init_one_color(&dlg.button_inactive);
+	init_one_color(&dlg.button_key_active);
+	init_one_color(&dlg.button_key_inactive);
+	init_one_color(&dlg.button_label_active);
+	init_one_color(&dlg.button_label_inactive);
+	init_one_color(&dlg.inputbox);
+	init_one_color(&dlg.inputbox_border);
+	init_one_color(&dlg.searchbox);
+	init_one_color(&dlg.searchbox_title);
+	init_one_color(&dlg.searchbox_border);
+	init_one_color(&dlg.position_indicator);
+	init_one_color(&dlg.menubox);
+	init_one_color(&dlg.menubox_border);
+	init_one_color(&dlg.item);
+	init_one_color(&dlg.item_selected);
+	init_one_color(&dlg.tag);
+	init_one_color(&dlg.tag_selected);
+	init_one_color(&dlg.tag_key);
+	init_one_color(&dlg.tag_key_selected);
+	init_one_color(&dlg.check);
+	init_one_color(&dlg.check_selected);
+	init_one_color(&dlg.uarrow);
+	init_one_color(&dlg.darrow);
+}
+
+/*
+ * Setup for color display
+ */
+static void color_setup(const char *theme)
+{
+	int use_color;
+
+	use_color = set_theme(theme);
+	if (use_color && has_colors()) {
+		start_color();
+		init_dialog_colors();
+	} else
+		set_mono_theme();
+}
+
+/*
+ * Set window to attribute 'attr'
+ */
+void attr_clear(WINDOW * win, int height, int width, chtype attr)
+{
+	int i, j;
+
+	wattrset(win, attr);
+	for (i = 0; i < height; i++) {
+		wmove(win, i, 0);
+		for (j = 0; j < width; j++)
+			waddch(win, ' ');
+	}
+	touchwin(win);
+}
+
+void dialog_clear(void)
+{
+	attr_clear(stdscr, LINES, COLS, dlg.screen.atr);
+	/* Display background title if it exists ... - SLH */
+	if (dlg.backtitle != NULL) {
+		int i;
+
+		wattrset(stdscr, dlg.screen.atr);
+		mvwaddstr(stdscr, 0, 1, (char *)dlg.backtitle);
+		wmove(stdscr, 1, 1);
+		for (i = 1; i < COLS - 1; i++)
+			waddch(stdscr, ACS_HLINE);
+	}
+	wnoutrefresh(stdscr);
+}
+
+/*
+ * Do some initialization for dialog
+ */
+int init_dialog(const char *backtitle)
+{
+	int height, width;
+
+	initscr();		/* Init curses */
+	getmaxyx(stdscr, height, width);
+	if (height < 19 || width < 80) {
+		endwin();
+		return -ERRDISPLAYTOOSMALL;
+	}
+
+	dlg.backtitle = backtitle;
+	color_setup(getenv("MENUCONFIG_COLOR"));
+
+	keypad(stdscr, TRUE);
+	cbreak();
+	noecho();
+	dialog_clear();
+
+	return 0;
+}
+
+void set_dialog_backtitle(const char *backtitle)
+{
+	dlg.backtitle = backtitle;
+}
+
+/*
+ * End using dialog functions.
+ */
+void end_dialog(int x, int y)
+{
+	/* move cursor back to original position */
+	move(y, x);
+	refresh();
+	endwin();
+}
+
+/* Print the title of the dialog. Center the title and truncate
+ * tile if wider than dialog (- 2 chars).
+ **/
+void print_title(WINDOW *dialog, const char *title, int width)
+{
+	if (title) {
+		int tlen = MIN(width - 2, strlen(title));
+		wattrset(dialog, dlg.title.atr);
+		mvwaddch(dialog, 0, (width - tlen) / 2 - 1, ' ');
+		mvwaddnstr(dialog, 0, (width - tlen)/2, title, tlen);
+		waddch(dialog, ' ');
+	}
+}
+
+/*
+ * Print a string of text in a window, automatically wrap around to the
+ * next line if the string is too long to fit on one line. Newline
+ * characters '\n' are replaced by spaces.  We start on a new line
+ * if there is no room for at least 4 nonblanks following a double-space.
+ */
+void print_autowrap(WINDOW * win, const char *prompt, int width, int y, int x)
+{
+	int newl, cur_x, cur_y;
+	int i, prompt_len, room, wlen;
+	char tempstr[MAX_LEN + 1], *word, *sp, *sp2;
+
+	strcpy(tempstr, prompt);
+
+	prompt_len = strlen(tempstr);
+
+	/*
+	 * Remove newlines
+	 */
+	for (i = 0; i < prompt_len; i++) {
+		if (tempstr[i] == '\n')
+			tempstr[i] = ' ';
+	}
+
+	if (prompt_len <= width - x * 2) {	/* If prompt is short */
+		wmove(win, y, (width - prompt_len) / 2);
+		waddstr(win, tempstr);
+	} else {
+		cur_x = x;
+		cur_y = y;
+		newl = 1;
+		word = tempstr;
+		while (word && *word) {
+			sp = strchr(word, ' ');
+			if (sp)
+				*sp++ = 0;
+
+			/* Wrap to next line if either the word does not fit,
+			   or it is the first word of a new sentence, and it is
+			   short, and the next word does not fit. */
+			room = width - cur_x;
+			wlen = strlen(word);
+			if (wlen > room ||
+			    (newl && wlen < 4 && sp
+			     && wlen + 1 + strlen(sp) > room
+			     && (!(sp2 = strchr(sp, ' '))
+				 || wlen + 1 + (sp2 - sp) > room))) {
+				cur_y++;
+				cur_x = x;
+			}
+			wmove(win, cur_y, cur_x);
+			waddstr(win, word);
+			getyx(win, cur_y, cur_x);
+			cur_x++;
+			if (sp && *sp == ' ') {
+				cur_x++;	/* double space */
+				while (*++sp == ' ') ;
+				newl = 1;
+			} else
+				newl = 0;
+			word = sp;
+		}
+	}
+}
+
+/*
+ * Print a button
+ */
+void print_button(WINDOW * win, const char *label, int y, int x, int selected)
+{
+	int i, temp;
+
+	wmove(win, y, x);
+	wattrset(win, selected ? dlg.button_active.atr
+		 : dlg.button_inactive.atr);
+	waddstr(win, "<");
+	temp = strspn(label, " ");
+	label += temp;
+	wattrset(win, selected ? dlg.button_label_active.atr
+		 : dlg.button_label_inactive.atr);
+	for (i = 0; i < temp; i++)
+		waddch(win, ' ');
+	wattrset(win, selected ? dlg.button_key_active.atr
+		 : dlg.button_key_inactive.atr);
+	waddch(win, label[0]);
+	wattrset(win, selected ? dlg.button_label_active.atr
+		 : dlg.button_label_inactive.atr);
+	waddstr(win, (char *)label + 1);
+	wattrset(win, selected ? dlg.button_active.atr
+		 : dlg.button_inactive.atr);
+	waddstr(win, ">");
+	wmove(win, y, x + temp + 1);
+}
+
+/*
+ * Draw a rectangular box with line drawing characters
+ */
+void
+draw_box(WINDOW * win, int y, int x, int height, int width,
+	 chtype box, chtype border)
+{
+	int i, j;
+
+	wattrset(win, 0);
+	for (i = 0; i < height; i++) {
+		wmove(win, y + i, x);
+		for (j = 0; j < width; j++)
+			if (!i && !j)
+				waddch(win, border | ACS_ULCORNER);
+			else if (i == height - 1 && !j)
+				waddch(win, border | ACS_LLCORNER);
+			else if (!i && j == width - 1)
+				waddch(win, box | ACS_URCORNER);
+			else if (i == height - 1 && j == width - 1)
+				waddch(win, box | ACS_LRCORNER);
+			else if (!i)
+				waddch(win, border | ACS_HLINE);
+			else if (i == height - 1)
+				waddch(win, box | ACS_HLINE);
+			else if (!j)
+				waddch(win, border | ACS_VLINE);
+			else if (j == width - 1)
+				waddch(win, box | ACS_VLINE);
+			else
+				waddch(win, box | ' ');
+	}
+}
+
+/*
+ * Draw shadows along the right and bottom edge to give a more 3D look
+ * to the boxes
+ */
+void draw_shadow(WINDOW * win, int y, int x, int height, int width)
+{
+	int i;
+
+	if (has_colors()) {	/* Whether terminal supports color? */
+		wattrset(win, dlg.shadow.atr);
+		wmove(win, y + height, x + 2);
+		for (i = 0; i < width; i++)
+			waddch(win, winch(win) & A_CHARTEXT);
+		for (i = y + 1; i < y + height + 1; i++) {
+			wmove(win, i, x + width);
+			waddch(win, winch(win) & A_CHARTEXT);
+			waddch(win, winch(win) & A_CHARTEXT);
+		}
+		wnoutrefresh(win);
+	}
+}
+
+/*
+ *  Return the position of the first alphabetic character in a string.
+ */
+int first_alpha(const char *string, const char *exempt)
+{
+	int i, in_paren = 0, c;
+
+	for (i = 0; i < strlen(string); i++) {
+		c = tolower(string[i]);
+
+		if (strchr("<[(", c))
+			++in_paren;
+		if (strchr(">])", c) && in_paren > 0)
+			--in_paren;
+
+		if ((!in_paren) && isalpha(c) && strchr(exempt, c) == 0)
+			return i;
+	}
+
+	return 0;
+}
+
+/*
+ * ncurses uses ESC to detect escaped char sequences. This resutl in
+ * a small timeout before ESC is actually delivered to the application.
+ * lxdialog suggest <ESC> <ESC> which is correctly translated to two
+ * times esc. But then we need to ignore the second esc to avoid stepping
+ * out one menu too much. Filter away all escaped key sequences since
+ * keypad(FALSE) turn off ncurses support for escape sequences - and thats
+ * needed to make notimeout() do as expected.
+ */
+int on_key_esc(WINDOW *win)
+{
+	int key;
+	int key2;
+	int key3;
+
+	nodelay(win, TRUE);
+	keypad(win, FALSE);
+	key = wgetch(win);
+	key2 = wgetch(win);
+	do {
+		key3 = wgetch(win);
+	} while (key3 != ERR);
+	nodelay(win, FALSE);
+	keypad(win, TRUE);
+	if (key == KEY_ESC && key2 == ERR)
+		return KEY_ESC;
+	else if (key != ERR && key != KEY_ESC && key2 == ERR)
+		ungetch(key);
+
+	return -1;
+}
+
+/* redraw screen in new size */
+int on_key_resize(void)
+{
+	dialog_clear();
+#ifdef NCURSES_VERSION
+	return KEY_RESIZE;
+#endif
+}
+
+struct dialog_list *item_cur;
+struct dialog_list item_nil;
+struct dialog_list *item_head;
+
+void item_reset(void)
+{
+	struct dialog_list *p, *next;
+
+	for (p = item_head; p; p = next) {
+		next = p->next;
+		free(p);
+	}
+	item_head = NULL;
+	item_cur = &item_nil;
+}
+
+void item_make(const char *fmt, ...)
+{
+	va_list ap;
+	struct dialog_list *p = malloc(sizeof(*p));
+
+	if (item_head)
+		item_cur->next = p;
+	else
+		item_head = p;
+	item_cur = p;
+	memset(p, 0, sizeof(*p));
+
+	va_start(ap, fmt);
+	vsnprintf(item_cur->node.str, sizeof(item_cur->node.str), fmt, ap);
+	va_end(ap);
+}
+
+void item_add_str(const char *fmt, ...)
+{
+	va_list ap;
+        size_t avail;
+
+	avail = sizeof(item_cur->node.str) - strlen(item_cur->node.str);
+
+	va_start(ap, fmt);
+	vsnprintf(item_cur->node.str + strlen(item_cur->node.str),
+		  avail, fmt, ap);
+	item_cur->node.str[sizeof(item_cur->node.str) - 1] = '\0';
+	va_end(ap);
+}
+
+void item_set_tag(char tag)
+{
+	item_cur->node.tag = tag;
+}
+void item_set_data(void *ptr)
+{
+	item_cur->node.data = ptr;
+}
+
+void item_set_selected(int val)
+{
+	item_cur->node.selected = val;
+}
+
+int item_activate_selected(void)
+{
+	item_foreach()
+		if (item_is_selected())
+			return 1;
+	return 0;
+}
+
+void *item_data(void)
+{
+	return item_cur->node.data;
+}
+
+char item_tag(void)
+{
+	return item_cur->node.tag;
+}
+
+int item_count(void)
+{
+	int n = 0;
+	struct dialog_list *p;
+
+	for (p = item_head; p; p = p->next)
+		n++;
+	return n;
+}
+
+void item_set(int n)
+{
+	int i = 0;
+	item_foreach()
+		if (i++ == n)
+			return;
+}
+
+int item_n(void)
+{
+	int n = 0;
+	struct dialog_list *p;
+
+	for (p = item_head; p; p = p->next) {
+		if (p == item_cur)
+			return n;
+		n++;
+	}
+	return 0;
+}
+
+const char *item_str(void)
+{
+	return item_cur->node.str;
+}
+
+int item_is_selected(void)
+{
+	return (item_cur->node.selected != 0);
+}
+
+int item_is_tag(char tag)
+{
+	return (item_cur->node.tag == tag);
+}

Added: trunk/coreboot-v2/util/kconfig/lxdialog/yesno.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/lxdialog/yesno.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/lxdialog/yesno.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,116 @@
+/*
+ *  yesno.c -- implements the yes/no box
+ *
+ *  ORIGINAL AUTHOR: Savio Lam (lam836 at cs.cuhk.hk)
+ *  MODIFIED FOR LINUX KERNEL CONFIG BY: William Roadcap (roadcap at cfw.com)
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  as published by the Free Software Foundation; either version 2
+ *  of the License, or (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include "dialog.h"
+
+/*
+ * Display termination buttons
+ */
+static void print_buttons(WINDOW * dialog, int height, int width, int selected)
+{
+	int x = width / 2 - 10;
+	int y = height - 2;
+
+	print_button(dialog, gettext(" Yes "), y, x, selected == 0);
+	print_button(dialog, gettext("  No  "), y, x + 13, selected == 1);
+
+	wmove(dialog, y, x + 1 + 13 * selected);
+	wrefresh(dialog);
+}
+
+/*
+ * Display a dialog box with two buttons - Yes and No
+ */
+int dialog_yesno(const char *title, const char *prompt, int height, int width)
+{
+	int i, x, y, key = 0, button = 0;
+	WINDOW *dialog;
+
+do_resize:
+	if (getmaxy(stdscr) < (height + 4))
+		return -ERRDISPLAYTOOSMALL;
+	if (getmaxx(stdscr) < (width + 4))
+		return -ERRDISPLAYTOOSMALL;
+
+	/* center dialog box on screen */
+	x = (COLS - width) / 2;
+	y = (LINES - height) / 2;
+
+	draw_shadow(stdscr, y, x, height, width);
+
+	dialog = newwin(height, width, y, x);
+	keypad(dialog, TRUE);
+
+	draw_box(dialog, 0, 0, height, width,
+		 dlg.dialog.atr, dlg.border.atr);
+	wattrset(dialog, dlg.border.atr);
+	mvwaddch(dialog, height - 3, 0, ACS_LTEE);
+	for (i = 0; i < width - 2; i++)
+		waddch(dialog, ACS_HLINE);
+	wattrset(dialog, dlg.dialog.atr);
+	waddch(dialog, ACS_RTEE);
+
+	print_title(dialog, title, width);
+
+	wattrset(dialog, dlg.dialog.atr);
+	print_autowrap(dialog, prompt, width - 2, 1, 3);
+
+	print_buttons(dialog, height, width, 0);
+
+	while (key != KEY_ESC) {
+		key = wgetch(dialog);
+		switch (key) {
+		case 'Y':
+		case 'y':
+			delwin(dialog);
+			return 0;
+		case 'N':
+		case 'n':
+			delwin(dialog);
+			return 1;
+
+		case TAB:
+		case KEY_LEFT:
+		case KEY_RIGHT:
+			button = ((key == KEY_LEFT ? --button : ++button) < 0) ? 1 : (button > 1 ? 0 : button);
+
+			print_buttons(dialog, height, width, button);
+			wrefresh(dialog);
+			break;
+		case ' ':
+		case '\n':
+			delwin(dialog);
+			return button;
+		case KEY_ESC:
+			key = on_key_esc(dialog);
+			break;
+#ifdef NCURSES_VERSION
+		case KEY_RESIZE:
+			delwin(dialog);
+			on_key_resize();
+			goto do_resize;
+#endif
+		}
+	}
+
+	delwin(dialog);
+	return key;		/* ESC pressed */
+}

Added: trunk/coreboot-v2/util/kconfig/mconf.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/mconf.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/mconf.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,931 @@
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel at linux-m68k.org>
+ * Released under the terms of the GNU GPL v2.0.
+ *
+ * Introduced single menu mode (show all sub-menus in one large tree).
+ * 2002-11-06 Petr Baudis <pasky at ucw.cz>
+ *
+ * i18n, 2005, Arnaldo Carvalho de Melo <acme at conectiva.com.br>
+ */
+
+#include <ctype.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <limits.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+#include <locale.h>
+
+#define LKC_DIRECT_LINK
+#include "lkc.h"
+#include "lxdialog/dialog.h"
+
+static const char mconf_readme[] = N_(
+"Overview\n"
+"--------\n"
+"Some features may be built directly into coreboot.\n"
+"Some may be made into loadable runtime modules.  Some features\n"
+"may be completely removed altogether.  There are also certain\n"
+"parameters which are not really features, but must be\n"
+"entered in as decimal or hexadecimal numbers or possibly text.\n"
+"\n"
+"Menu items beginning with following braces represent features that\n"
+"  [ ] can be built in or removed\n"
+"  < > can be built in, modularized or removed\n"
+"  { } can be built in or modularized (selected by other feature)\n"
+"  - - are selected by other feature,\n"
+"while *, M or whitespace inside braces means to build in, build as\n"
+"a module or to exclude the feature respectively.\n"
+"\n"
+"To change any of these features, highlight it with the cursor\n"
+"keys and press <Y> to build it in, <M> to make it a module or\n"
+"<N> to removed it.  You may also press the <Space Bar> to cycle\n"
+"through the available options (ie. Y->N->M->Y).\n"
+"\n"
+"Some additional keyboard hints:\n"
+"\n"
+"Menus\n"
+"----------\n"
+"o  Use the Up/Down arrow keys (cursor keys) to highlight the item\n"
+"   you wish to change or submenu wish to select and press <Enter>.\n"
+"   Submenus are designated by \"--->\".\n"
+"\n"
+"   Shortcut: Press the option's highlighted letter (hotkey).\n"
+"             Pressing a hotkey more than once will sequence\n"
+"             through all visible items which use that hotkey.\n"
+"\n"
+"   You may also use the <PAGE UP> and <PAGE DOWN> keys to scroll\n"
+"   unseen options into view.\n"
+"\n"
+"o  To exit a menu use the cursor keys to highlight the <Exit> button\n"
+"   and press <ENTER>.\n"
+"\n"
+"   Shortcut: Press <ESC><ESC> or <E> or <X> if there is no hotkey\n"
+"             using those letters.  You may press a single <ESC>, but\n"
+"             there is a delayed response which you may find annoying.\n"
+"\n"
+"   Also, the <TAB> and cursor keys will cycle between <Select>,\n"
+"   <Exit> and <Help>\n"
+"\n"
+"o  To get help with an item, use the cursor keys to highlight <Help>\n"
+"   and Press <ENTER>.\n"
+"\n"
+"   Shortcut: Press <H> or <?>.\n"
+"\n"
+"\n"
+"Radiolists  (Choice lists)\n"
+"-----------\n"
+"o  Use the cursor keys to select the option you wish to set and press\n"
+"   <S> or the <SPACE BAR>.\n"
+"\n"
+"   Shortcut: Press the first letter of the option you wish to set then\n"
+"             press <S> or <SPACE BAR>.\n"
+"\n"
+"o  To see available help for the item, use the cursor keys to highlight\n"
+"   <Help> and Press <ENTER>.\n"
+"\n"
+"   Shortcut: Press <H> or <?>.\n"
+"\n"
+"   Also, the <TAB> and cursor keys will cycle between <Select> and\n"
+"   <Help>\n"
+"\n"
+"\n"
+"Data Entry\n"
+"-----------\n"
+"o  Enter the requested information and press <ENTER>\n"
+"   If you are entering hexadecimal values, it is not necessary to\n"
+"   add the '0x' prefix to the entry.\n"
+"\n"
+"o  For help, use the <TAB> or cursor keys to highlight the help option\n"
+"   and press <ENTER>.  You can try <TAB><H> as well.\n"
+"\n"
+"\n"
+"Text Box    (Help Window)\n"
+"--------\n"
+"o  Use the cursor keys to scroll up/down/left/right.  The VI editor\n"
+"   keys h,j,k,l function here as do <SPACE BAR> and <B> for those\n"
+"   who are familiar with less and lynx.\n"
+"\n"
+"o  Press <E>, <X>, <Enter> or <Esc><Esc> to exit.\n"
+"\n"
+"\n"
+"Alternate Configuration Files\n"
+"-----------------------------\n"
+"Menuconfig supports the use of alternate configuration files for\n"
+"those who, for various reasons, find it necessary to switch\n"
+"between different configurations.\n"
+"\n"
+"At the end of the main menu you will find two options.  One is\n"
+"for saving the current configuration to a file of your choosing.\n"
+"The other option is for loading a previously saved alternate\n"
+"configuration.\n"
+"\n"
+"Even if you don't use alternate configuration files, but you\n"
+"find during a Menuconfig session that you have completely messed\n"
+"up your settings, you may use the \"Load Alternate...\" option to\n"
+"restore your previously saved settings from \".config\" without\n"
+"restarting Menuconfig.\n"
+"\n"
+"Other information\n"
+"-----------------\n"
+"If you use Menuconfig in an XTERM window make sure you have your\n"
+"$TERM variable set to point to a xterm definition which supports color.\n"
+"Otherwise, Menuconfig will look rather bad.  Menuconfig will not\n"
+"display correctly in a RXVT window because rxvt displays only one\n"
+"intensity of color, bright.\n"
+"\n"
+"Menuconfig will display larger menus on screens or xterms which are\n"
+"set to display more than the standard 25 row by 80 column geometry.\n"
+"In order for this to work, the \"stty size\" command must be able to\n"
+"display the screen's current row and column geometry.  I STRONGLY\n"
+"RECOMMEND that you make sure you do NOT have the shell variables\n"
+"LINES and COLUMNS exported into your environment.  Some distributions\n"
+"export those variables via /etc/profile.  Some ncurses programs can\n"
+"become confused when those variables (LINES & COLUMNS) don't reflect\n"
+"the true screen size.\n"
+"\n"
+"Optional personality available\n"
+"------------------------------\n"
+"If you prefer to have all of the options listed in a single\n"
+"menu, rather than the default multimenu hierarchy, run the menuconfig\n"
+"with MENUCONFIG_MODE environment variable set to single_menu. Example:\n"
+"\n"
+"make MENUCONFIG_MODE=single_menu menuconfig\n"
+"\n"
+"<Enter> will then unroll the appropriate category, or enfold it if it\n"
+"is already unrolled.\n"
+"\n"
+"Note that this mode can eventually be a little more CPU expensive\n"
+"(especially with a larger number of unrolled categories) than the\n"
+"default mode.\n"
+"\n"
+"Different color themes available\n"
+"--------------------------------\n"
+"It is possible to select different color themes using the variable\n"
+"MENUCONFIG_COLOR. To select a theme use:\n"
+"\n"
+"make MENUCONFIG_COLOR=<theme> menuconfig\n"
+"\n"
+"Available themes are\n"
+" mono       => selects colors suitable for monochrome displays\n"
+" blackbg    => selects a color scheme with black background\n"
+" classic    => theme with blue background. The classic look\n"
+" bluetitle  => a LCD friendly version of classic. (default)\n"
+"\n"),
+menu_instructions[] = N_(
+	"Arrow keys navigate the menu.  "
+	"<Enter> selects submenus --->.  "
+	"Highlighted letters are hotkeys.  "
+	"Pressing <Y> includes, <N> excludes, <M> modularizes features.  "
+	"Press <Esc><Esc> to exit, <?> for Help, </> for Search.  "
+	"Legend: [*] built-in  [ ] excluded  <M> module  < > module capable"),
+radiolist_instructions[] = N_(
+	"Use the arrow keys to navigate this window or "
+	"press the hotkey of the item you wish to select "
+	"followed by the <SPACE BAR>. "
+	"Press <?> for additional information about this option."),
+inputbox_instructions_int[] = N_(
+	"Please enter a decimal value. "
+	"Fractions will not be accepted.  "
+	"Use the <TAB> key to move from the input field to the buttons below it."),
+inputbox_instructions_hex[] = N_(
+	"Please enter a hexadecimal value. "
+	"Use the <TAB> key to move from the input field to the buttons below it."),
+inputbox_instructions_string[] = N_(
+	"Please enter a string value. "
+	"Use the <TAB> key to move from the input field to the buttons below it."),
+setmod_text[] = N_(
+	"This feature depends on another which has been configured as a module.\n"
+	"As a result, this feature will be built as a module."),
+nohelp_text[] = N_(
+	"There is no help available for this option.\n"),
+load_config_text[] = N_(
+	"Enter the name of the configuration file you wish to load.  "
+	"Accept the name shown to restore the configuration you "
+	"last retrieved.  Leave blank to abort."),
+load_config_help[] = N_(
+	"\n"
+	"For various reasons, one may wish to keep several different\n"
+	"configurations available on a single machine.\n"
+	"\n"
+	"If you have saved a previous configuration in a file other than the\n"
+	"default, entering the name of the file here will allow you\n"
+	"to modify that configuration.\n"
+	"\n"
+	"If you are uncertain, then you have probably never used alternate\n"
+	"configuration files.  You should therefor leave this blank to abort.\n"),
+save_config_text[] = N_(
+	"Enter a filename to which this configuration should be saved "
+	"as an alternate.  Leave blank to abort."),
+save_config_help[] = N_(
+	"\n"
+	"For various reasons, one may wish to keep different\n"
+	"configurations available on a single machine.\n"
+	"\n"
+	"Entering a file name here will allow you to later retrieve, modify\n"
+	"and use the current configuration as an alternate to whatever\n"
+	"configuration options you have selected at that time.\n"
+	"\n"
+	"If you are uncertain what all this means then you should probably\n"
+	"leave this blank.\n"),
+search_help[] = N_(
+	"\n"
+	"Search for CONFIG_ symbols and display their relations.\n"
+	"Regular expressions are allowed.\n"
+	"Example: search for \"^FOO\"\n"
+	"Result:\n"
+	"-----------------------------------------------------------------\n"
+	"Symbol: FOO [=m]\n"
+	"Prompt: Foo bus is used to drive the bar HW\n"
+	"Defined at drivers/pci/Kconfig:47\n"
+	"Depends on: X86_LOCAL_APIC && X86_IO_APIC || IA64\n"
+	"Location:\n"
+	"  -> Bus options (PCI, PCMCIA, EISA, MCA, ISA)\n"
+	"    -> PCI support (PCI [=y])\n"
+	"      -> PCI access mode (<choice> [=y])\n"
+	"Selects: LIBCRC32\n"
+	"Selected by: BAR\n"
+	"-----------------------------------------------------------------\n"
+	"o The line 'Prompt:' shows the text used in the menu structure for\n"
+	"  this CONFIG_ symbol\n"
+	"o The 'Defined at' line tell at what file / line number the symbol\n"
+	"  is defined\n"
+	"o The 'Depends on:' line tell what symbols needs to be defined for\n"
+	"  this symbol to be visible in the menu (selectable)\n"
+	"o The 'Location:' lines tell where in the menu structure this symbol\n"
+	"  is located\n"
+	"    A location followed by a [=y] indicate that this is a selectable\n"
+	"    menu item - and current value is displayed inside brackets.\n"
+	"o The 'Selects:' line tell what symbol will be automatically\n"
+	"  selected if this symbol is selected (y or m)\n"
+	"o The 'Selected by' line tell what symbol has selected this symbol\n"
+	"\n"
+	"Only relevant lines are shown.\n"
+	"\n\n"
+	"Search examples:\n"
+	"Examples: USB	=> find all CONFIG_ symbols containing USB\n"
+	"          ^USB => find all CONFIG_ symbols starting with USB\n"
+	"          USB$ => find all CONFIG_ symbols ending with USB\n"
+	"\n");
+
+static int indent;
+static struct menu *current_menu;
+static int child_count;
+static int single_menu_mode;
+
+static void conf(struct menu *menu);
+static void conf_choice(struct menu *menu);
+static void conf_string(struct menu *menu);
+static void conf_load(void);
+static void conf_save(void);
+static void show_textbox(const char *title, const char *text, int r, int c);
+static void show_helptext(const char *title, const char *text);
+static void show_help(struct menu *menu);
+
+static void get_prompt_str(struct gstr *r, struct property *prop)
+{
+	int i, j;
+	struct menu *submenu[8], *menu;
+
+	str_printf(r, _("Prompt: %s\n"), _(prop->text));
+	str_printf(r, _("  Defined at %s:%d\n"), prop->menu->file->name,
+		prop->menu->lineno);
+	if (!expr_is_yes(prop->visible.expr)) {
+		str_append(r, _("  Depends on: "));
+		expr_gstr_print(prop->visible.expr, r);
+		str_append(r, "\n");
+	}
+	menu = prop->menu->parent;
+	for (i = 0; menu != &rootmenu && i < 8; menu = menu->parent)
+		submenu[i++] = menu;
+	if (i > 0) {
+		str_printf(r, _("  Location:\n"));
+		for (j = 4; --i >= 0; j += 2) {
+			menu = submenu[i];
+			str_printf(r, "%*c-> %s", j, ' ', _(menu_get_prompt(menu)));
+			if (menu->sym) {
+				str_printf(r, " (%s [=%s])", menu->sym->name ?
+					menu->sym->name : _("<choice>"),
+					sym_get_string_value(menu->sym));
+			}
+			str_append(r, "\n");
+		}
+	}
+}
+
+static void get_symbol_str(struct gstr *r, struct symbol *sym)
+{
+	bool hit;
+	struct property *prop;
+
+	if (sym && sym->name)
+		str_printf(r, "Symbol: %s [=%s]\n", sym->name,
+		                                    sym_get_string_value(sym));
+	for_all_prompts(sym, prop)
+		get_prompt_str(r, prop);
+	hit = false;
+	for_all_properties(sym, prop, P_SELECT) {
+		if (!hit) {
+			str_append(r, "  Selects: ");
+			hit = true;
+		} else
+			str_printf(r, " && ");
+		expr_gstr_print(prop->expr, r);
+	}
+	if (hit)
+		str_append(r, "\n");
+	if (sym->rev_dep.expr) {
+		str_append(r, _("  Selected by: "));
+		expr_gstr_print(sym->rev_dep.expr, r);
+		str_append(r, "\n");
+	}
+	str_append(r, "\n\n");
+}
+
+static struct gstr get_relations_str(struct symbol **sym_arr)
+{
+	struct symbol *sym;
+	struct gstr res = str_new();
+	int i;
+
+	for (i = 0; sym_arr && (sym = sym_arr[i]); i++)
+		get_symbol_str(&res, sym);
+	if (!i)
+		str_append(&res, _("No matches found.\n"));
+	return res;
+}
+
+static char filename[PATH_MAX+1];
+static void set_config_filename(const char *config_filename)
+{
+	static char menu_backtitle[PATH_MAX+128];
+	int size;
+	struct symbol *sym;
+
+	sym = sym_lookup("KERNELVERSION", 0);
+	sym_calc_value(sym);
+	size = snprintf(menu_backtitle, sizeof(menu_backtitle),
+	                _("%s - coreboot v%s Configuration"),
+		        config_filename, getenv("KERNELVERSION"));
+	if (size >= sizeof(menu_backtitle))
+		menu_backtitle[sizeof(menu_backtitle)-1] = '\0';
+	set_dialog_backtitle(menu_backtitle);
+
+	size = snprintf(filename, sizeof(filename), "%s", config_filename);
+	if (size >= sizeof(filename))
+		filename[sizeof(filename)-1] = '\0';
+}
+
+
+static void search_conf(void)
+{
+	struct symbol **sym_arr;
+	struct gstr res;
+	char *dialog_input;
+	int dres;
+again:
+	dialog_clear();
+	dres = dialog_inputbox(_("Search Configuration Parameter"),
+			      _("Enter CONFIG_ (sub)string to search for "
+				"(with or without \"CONFIG\")"),
+			      10, 75, "");
+	switch (dres) {
+	case 0:
+		break;
+	case 1:
+		show_helptext(_("Search Configuration"), search_help);
+		goto again;
+	default:
+		return;
+	}
+
+	/* strip CONFIG_ if necessary */
+	dialog_input = dialog_input_result;
+	if (strncasecmp(dialog_input_result, "CONFIG_", 7) == 0)
+		dialog_input += 7;
+
+	sym_arr = sym_re_search(dialog_input);
+	res = get_relations_str(sym_arr);
+	free(sym_arr);
+	show_textbox(_("Search Results"), str_get(&res), 0, 0);
+	str_free(&res);
+}
+
+static void build_conf(struct menu *menu)
+{
+	struct symbol *sym;
+	struct property *prop;
+	struct menu *child;
+	int type, tmp, doint = 2;
+	tristate val;
+	char ch;
+
+	if (!menu_is_visible(menu))
+		return;
+
+	sym = menu->sym;
+	prop = menu->prompt;
+	if (!sym) {
+		if (prop && menu != current_menu) {
+			const char *prompt = menu_get_prompt(menu);
+			switch (prop->type) {
+			case P_MENU:
+				child_count++;
+				prompt = _(prompt);
+				if (single_menu_mode) {
+					item_make("%s%*c%s",
+						  menu->data ? "-->" : "++>",
+						  indent + 1, ' ', prompt);
+				} else
+					item_make("   %*c%s  --->", indent + 1, ' ', prompt);
+
+				item_set_tag('m');
+				item_set_data(menu);
+				if (single_menu_mode && menu->data)
+					goto conf_childs;
+				return;
+			case P_COMMENT:
+				if (prompt) {
+					child_count++;
+					item_make("   %*c*** %s ***", indent + 1, ' ', _(prompt));
+					item_set_tag(':');
+					item_set_data(menu);
+				}
+				break;
+			default:
+				if (prompt) {
+					child_count++;
+					item_make("---%*c%s", indent + 1, ' ', _(prompt));
+					item_set_tag(':');
+					item_set_data(menu);
+				}
+			}
+		} else
+			doint = 0;
+		goto conf_childs;
+	}
+
+	type = sym_get_type(sym);
+	if (sym_is_choice(sym)) {
+		struct symbol *def_sym = sym_get_choice_value(sym);
+		struct menu *def_menu = NULL;
+
+		child_count++;
+		for (child = menu->list; child; child = child->next) {
+			if (menu_is_visible(child) && child->sym == def_sym)
+				def_menu = child;
+		}
+
+		val = sym_get_tristate_value(sym);
+		if (sym_is_changable(sym)) {
+			switch (type) {
+			case S_BOOLEAN:
+				item_make("[%c]", val == no ? ' ' : '*');
+				break;
+			case S_TRISTATE:
+				switch (val) {
+				case yes: ch = '*'; break;
+				case mod: ch = 'M'; break;
+				default:  ch = ' '; break;
+				}
+				item_make("<%c>", ch);
+				break;
+			}
+			item_set_tag('t');
+			item_set_data(menu);
+		} else {
+			item_make("   ");
+			item_set_tag(def_menu ? 't' : ':');
+			item_set_data(menu);
+		}
+
+		item_add_str("%*c%s", indent + 1, ' ', _(menu_get_prompt(menu)));
+		if (val == yes) {
+			if (def_menu) {
+				item_add_str(" (%s)", _(menu_get_prompt(def_menu)));
+				item_add_str("  --->");
+				if (def_menu->list) {
+					indent += 2;
+					build_conf(def_menu);
+					indent -= 2;
+				}
+			}
+			return;
+		}
+	} else {
+		if (menu == current_menu) {
+			item_make("---%*c%s", indent + 1, ' ', _(menu_get_prompt(menu)));
+			item_set_tag(':');
+			item_set_data(menu);
+			goto conf_childs;
+		}
+		child_count++;
+		val = sym_get_tristate_value(sym);
+		if (sym_is_choice_value(sym) && val == yes) {
+			item_make("   ");
+			item_set_tag(':');
+			item_set_data(menu);
+		} else {
+			switch (type) {
+			case S_BOOLEAN:
+				if (sym_is_changable(sym))
+					item_make("[%c]", val == no ? ' ' : '*');
+				else
+					item_make("-%c-", val == no ? ' ' : '*');
+				item_set_tag('t');
+				item_set_data(menu);
+				break;
+			case S_TRISTATE:
+				switch (val) {
+				case yes: ch = '*'; break;
+				case mod: ch = 'M'; break;
+				default:  ch = ' '; break;
+				}
+				if (sym_is_changable(sym)) {
+					if (sym->rev_dep.tri == mod)
+						item_make("{%c}", ch);
+					else
+						item_make("<%c>", ch);
+				} else
+					item_make("-%c-", ch);
+				item_set_tag('t');
+				item_set_data(menu);
+				break;
+			default:
+				tmp = 2 + strlen(sym_get_string_value(sym)); /* () = 2 */
+				item_make("(%s)", sym_get_string_value(sym));
+				tmp = indent - tmp + 4;
+				if (tmp < 0)
+					tmp = 0;
+				item_add_str("%*c%s%s", tmp, ' ', _(menu_get_prompt(menu)),
+					     (sym_has_value(sym) || !sym_is_changable(sym)) ?
+					     "" : _(" (NEW)"));
+				item_set_tag('s');
+				item_set_data(menu);
+				goto conf_childs;
+			}
+		}
+		item_add_str("%*c%s%s", indent + 1, ' ', _(menu_get_prompt(menu)),
+			  (sym_has_value(sym) || !sym_is_changable(sym)) ?
+			  "" : _(" (NEW)"));
+		if (menu->prompt->type == P_MENU) {
+			item_add_str("  --->");
+			return;
+		}
+	}
+
+conf_childs:
+	indent += doint;
+	for (child = menu->list; child; child = child->next)
+		build_conf(child);
+	indent -= doint;
+}
+
+static void conf(struct menu *menu)
+{
+	struct menu *submenu;
+	const char *prompt = menu_get_prompt(menu);
+	struct symbol *sym;
+	struct menu *active_menu = NULL;
+	int res;
+	int s_scroll = 0;
+
+	while (1) {
+		item_reset();
+		current_menu = menu;
+		build_conf(menu);
+		if (!child_count)
+			break;
+		if (menu == &rootmenu) {
+			item_make("--- ");
+			item_set_tag(':');
+			item_make(_("    Load an Alternate Configuration File"));
+			item_set_tag('L');
+			item_make(_("    Save an Alternate Configuration File"));
+			item_set_tag('S');
+		}
+		dialog_clear();
+		res = dialog_menu(prompt ? _(prompt) : _("Main Menu"),
+				  _(menu_instructions),
+				  active_menu, &s_scroll);
+		if (res == 1 || res == KEY_ESC || res == -ERRDISPLAYTOOSMALL)
+			break;
+		if (!item_activate_selected())
+			continue;
+		if (!item_tag())
+			continue;
+
+		submenu = item_data();
+		active_menu = item_data();
+		if (submenu)
+			sym = submenu->sym;
+		else
+			sym = NULL;
+
+		switch (res) {
+		case 0:
+			switch (item_tag()) {
+			case 'm':
+				if (single_menu_mode)
+					submenu->data = (void *) (long) !submenu->data;
+				else
+					conf(submenu);
+				break;
+			case 't':
+				if (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes)
+					conf_choice(submenu);
+				else if (submenu->prompt->type == P_MENU)
+					conf(submenu);
+				break;
+			case 's':
+				conf_string(submenu);
+				break;
+			case 'L':
+				conf_load();
+				break;
+			case 'S':
+				conf_save();
+				break;
+			}
+			break;
+		case 2:
+			if (sym)
+				show_help(submenu);
+			else
+				show_helptext(_("README"), _(mconf_readme));
+			break;
+		case 3:
+			if (item_is_tag('t')) {
+				if (sym_set_tristate_value(sym, yes))
+					break;
+				if (sym_set_tristate_value(sym, mod))
+					show_textbox(NULL, setmod_text, 6, 74);
+			}
+			break;
+		case 4:
+			if (item_is_tag('t'))
+				sym_set_tristate_value(sym, no);
+			break;
+		case 5:
+			if (item_is_tag('t'))
+				sym_set_tristate_value(sym, mod);
+			break;
+		case 6:
+			if (item_is_tag('t'))
+				sym_toggle_tristate_value(sym);
+			else if (item_is_tag('m'))
+				conf(submenu);
+			break;
+		case 7:
+			search_conf();
+			break;
+		}
+	}
+}
+
+static void show_textbox(const char *title, const char *text, int r, int c)
+{
+	dialog_clear();
+	dialog_textbox(title, text, r, c);
+}
+
+static void show_helptext(const char *title, const char *text)
+{
+	show_textbox(title, text, 0, 0);
+}
+
+static void show_help(struct menu *menu)
+{
+	struct gstr help = str_new();
+	struct symbol *sym = menu->sym;
+
+	if (menu_has_help(menu))
+	{
+		if (sym->name) {
+			str_printf(&help, "CONFIG_%s:\n\n", sym->name);
+			str_append(&help, _(menu_get_help(menu)));
+			str_append(&help, "\n");
+		}
+	} else {
+		str_append(&help, nohelp_text);
+	}
+	get_symbol_str(&help, sym);
+	show_helptext(_(menu_get_prompt(menu)), str_get(&help));
+	str_free(&help);
+}
+
+static void conf_choice(struct menu *menu)
+{
+	const char *prompt = _(menu_get_prompt(menu));
+	struct menu *child;
+	struct symbol *active;
+
+	active = sym_get_choice_value(menu->sym);
+	while (1) {
+		int res;
+		int selected;
+		item_reset();
+
+		current_menu = menu;
+		for (child = menu->list; child; child = child->next) {
+			if (!menu_is_visible(child))
+				continue;
+			item_make("%s", _(menu_get_prompt(child)));
+			item_set_data(child);
+			if (child->sym == active)
+				item_set_selected(1);
+			if (child->sym == sym_get_choice_value(menu->sym))
+				item_set_tag('X');
+		}
+		dialog_clear();
+		res = dialog_checklist(prompt ? _(prompt) : _("Main Menu"),
+					_(radiolist_instructions),
+					 15, 70, 6);
+		selected = item_activate_selected();
+		switch (res) {
+		case 0:
+			if (selected) {
+				child = item_data();
+				sym_set_tristate_value(child->sym, yes);
+			}
+			return;
+		case 1:
+			if (selected) {
+				child = item_data();
+				show_help(child);
+				active = child->sym;
+			} else
+				show_help(menu);
+			break;
+		case KEY_ESC:
+			return;
+		case -ERRDISPLAYTOOSMALL:
+			return;
+		}
+	}
+}
+
+static void conf_string(struct menu *menu)
+{
+	const char *prompt = menu_get_prompt(menu);
+
+	while (1) {
+		int res;
+		const char *heading;
+
+		switch (sym_get_type(menu->sym)) {
+		case S_INT:
+			heading = _(inputbox_instructions_int);
+			break;
+		case S_HEX:
+			heading = _(inputbox_instructions_hex);
+			break;
+		case S_STRING:
+			heading = _(inputbox_instructions_string);
+			break;
+		default:
+			heading = _("Internal mconf error!");
+		}
+		dialog_clear();
+		res = dialog_inputbox(prompt ? _(prompt) : _("Main Menu"),
+				      heading, 10, 75,
+				      sym_get_string_value(menu->sym));
+		switch (res) {
+		case 0:
+			if (sym_set_string_value(menu->sym, dialog_input_result))
+				return;
+			show_textbox(NULL, _("You have made an invalid entry."), 5, 43);
+			break;
+		case 1:
+			show_help(menu);
+			break;
+		case KEY_ESC:
+			return;
+		}
+	}
+}
+
+static void conf_load(void)
+{
+
+	while (1) {
+		int res;
+		dialog_clear();
+		res = dialog_inputbox(NULL, load_config_text,
+				      11, 55, filename);
+		switch(res) {
+		case 0:
+			if (!dialog_input_result[0])
+				return;
+			if (!conf_read(dialog_input_result)) {
+				set_config_filename(dialog_input_result);
+				sym_set_change_count(1);
+				return;
+			}
+			show_textbox(NULL, _("File does not exist!"), 5, 38);
+			break;
+		case 1:
+			show_helptext(_("Load Alternate Configuration"), load_config_help);
+			break;
+		case KEY_ESC:
+			return;
+		}
+	}
+}
+
+static void conf_save(void)
+{
+	while (1) {
+		int res;
+		dialog_clear();
+		res = dialog_inputbox(NULL, save_config_text,
+				      11, 55, filename);
+		switch(res) {
+		case 0:
+			if (!dialog_input_result[0])
+				return;
+			if (!conf_write(dialog_input_result)) {
+				set_config_filename(dialog_input_result);
+				return;
+			}
+			show_textbox(NULL, _("Can't create file!  Probably a nonexistent directory."), 5, 60);
+			break;
+		case 1:
+			show_helptext(_("Save Alternate Configuration"), save_config_help);
+			break;
+		case KEY_ESC:
+			return;
+		}
+	}
+}
+
+int main(int ac, char **av)
+{
+	int saved_x = 0, saved_y = 0;
+	char *mode;
+	int res;
+
+	setlocale(LC_ALL, "");
+	bindtextdomain(PACKAGE, LOCALEDIR);
+	textdomain(PACKAGE);
+
+	conf_parse(av[1]);
+	conf_read(NULL);
+
+	mode = getenv("MENUCONFIG_MODE");
+	if (mode) {
+		if (!strcasecmp(mode, "single_menu"))
+			single_menu_mode = 1;
+	}
+
+	if (stdscr) getyx(stdscr, saved_y, saved_x);
+	if (init_dialog(NULL)) {
+		fprintf(stderr, N_("Your display is too small to run Menuconfig!\n"));
+		fprintf(stderr, N_("It must be at least 19 lines by 80 columns.\n"));
+		return 1;
+	}
+
+	set_config_filename(conf_get_configname());
+	do {
+		conf(&rootmenu);
+		dialog_clear();
+		if (conf_get_changed())
+			res = dialog_yesno(NULL,
+					   _("Do you wish to save your "
+					     "new configuration?\n"
+					     "<ESC><ESC> to continue."),
+					   6, 60);
+		else
+			res = -1;
+	} while (res == KEY_ESC);
+	end_dialog(saved_x, saved_y);
+
+	switch (res) {
+	case 0:
+		if (conf_write(filename)) {
+			fprintf(stderr, _("\n\n"
+				"Error during writing of the configuration.\n"
+				"Your configuration changes were NOT saved."
+				"\n\n"));
+			return 1;
+		}
+		if (conf_write_autoconf()) {
+			fprintf(stderr, _("\n*** Error during writing of the configuration.\n\n"));
+			return 1;
+		}
+	case -1:
+		printf(_("\n\n"
+			"*** End of coreboot configuration.\n"
+			"*** Execute 'make' to build or try 'make help'."
+			"\n\n"));
+		break;
+	default:
+		fprintf(stderr, _("\n\n"
+			"Your configuration changes were NOT saved."
+			"\n\n"));
+	}
+
+	return 0;
+}

Added: trunk/coreboot-v2/util/kconfig/menu.c
===================================================================
--- trunk/coreboot-v2/util/kconfig/menu.c	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/menu.c	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,463 @@
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel at linux-m68k.org>
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+#define LKC_DIRECT_LINK
+#include "lkc.h"
+
+struct menu rootmenu;
+static struct menu **last_entry_ptr;
+
+struct file *file_list;
+struct file *current_file;
+
+void menu_warn(struct menu *menu, const char *fmt, ...)
+{
+	va_list ap;
+	va_start(ap, fmt);
+	fprintf(stderr, "%s:%d:warning: ", menu->file->name, menu->lineno);
+	vfprintf(stderr, fmt, ap);
+	fprintf(stderr, "\n");
+	va_end(ap);
+}
+
+static void prop_warn(struct property *prop, const char *fmt, ...)
+{
+	va_list ap;
+	va_start(ap, fmt);
+	fprintf(stderr, "%s:%d:warning: ", prop->file->name, prop->lineno);
+	vfprintf(stderr, fmt, ap);
+	fprintf(stderr, "\n");
+	va_end(ap);
+}
+
+void menu_init(void)
+{
+	current_entry = current_menu = &rootmenu;
+	last_entry_ptr = &rootmenu.list;
+}
+
+void menu_add_entry(struct symbol *sym)
+{
+	struct menu *menu;
+
+	menu = malloc(sizeof(*menu));
+	memset(menu, 0, sizeof(*menu));
+	menu->sym = sym;
+	menu->parent = current_menu;
+	menu->file = current_file;
+	menu->lineno = zconf_lineno();
+
+	*last_entry_ptr = menu;
+	last_entry_ptr = &menu->next;
+	current_entry = menu;
+}
+
+void menu_end_entry(void)
+{
+}
+
+struct menu *menu_add_menu(void)
+{
+	menu_end_entry();
+	last_entry_ptr = &current_entry->list;
+	return current_menu = current_entry;
+}
+
+void menu_end_menu(void)
+{
+	last_entry_ptr = &current_menu->next;
+	current_menu = current_menu->parent;
+}
+
+struct expr *menu_check_dep(struct expr *e)
+{
+	if (!e)
+		return e;
+
+	switch (e->type) {
+	case E_NOT:
+		e->left.expr = menu_check_dep(e->left.expr);
+		break;
+	case E_OR:
+	case E_AND:
+		e->left.expr = menu_check_dep(e->left.expr);
+		e->right.expr = menu_check_dep(e->right.expr);
+		break;
+	case E_SYMBOL:
+		/* change 'm' into 'm' && MODULES */
+		if (e->left.sym == &symbol_mod)
+			return expr_alloc_and(e, expr_alloc_symbol(modules_sym));
+		break;
+	default:
+		break;
+	}
+	return e;
+}
+
+void menu_add_dep(struct expr *dep)
+{
+	current_entry->dep = expr_alloc_and(current_entry->dep, menu_check_dep(dep));
+}
+
+void menu_set_type(int type)
+{
+	struct symbol *sym = current_entry->sym;
+
+	if (sym->type == type)
+		return;
+	if (sym->type == S_UNKNOWN) {
+		sym->type = type;
+		return;
+	}
+	menu_warn(current_entry, "type of '%s' redefined from '%s' to '%s'",
+	    sym->name ? sym->name : "<choice>",
+	    sym_type_name(sym->type), sym_type_name(type));
+}
+
+struct property *menu_add_prop(enum prop_type type, char *prompt, struct expr *expr, struct expr *dep)
+{
+	struct property *prop = prop_alloc(type, current_entry->sym);
+
+	prop->menu = current_entry;
+	prop->expr = expr;
+	prop->visible.expr = menu_check_dep(dep);
+
+	if (prompt) {
+		if (isspace(*prompt)) {
+			prop_warn(prop, "leading whitespace ignored");
+			while (isspace(*prompt))
+				prompt++;
+		}
+		if (current_entry->prompt)
+			prop_warn(prop, "prompt redefined");
+		current_entry->prompt = prop;
+	}
+	prop->text = prompt;
+
+	return prop;
+}
+
+struct property *menu_add_prompt(enum prop_type type, char *prompt, struct expr *dep)
+{
+	return menu_add_prop(type, prompt, NULL, dep);
+}
+
+void menu_add_expr(enum prop_type type, struct expr *expr, struct expr *dep)
+{
+	menu_add_prop(type, NULL, expr, dep);
+}
+
+void menu_add_symbol(enum prop_type type, struct symbol *sym, struct expr *dep)
+{
+	menu_add_prop(type, NULL, expr_alloc_symbol(sym), dep);
+}
+
+void menu_add_option(int token, char *arg)
+{
+	struct property *prop;
+
+	switch (token) {
+	case T_OPT_MODULES:
+		prop = prop_alloc(P_DEFAULT, modules_sym);
+		prop->expr = expr_alloc_symbol(current_entry->sym);
+		break;
+	case T_OPT_DEFCONFIG_LIST:
+		if (!sym_defconfig_list)
+			sym_defconfig_list = current_entry->sym;
+		else if (sym_defconfig_list != current_entry->sym)
+			zconf_error("trying to redefine defconfig symbol");
+		break;
+	case T_OPT_ENV:
+		prop_add_env(arg);
+		break;
+	}
+}
+
+static int menu_range_valid_sym(struct symbol *sym, struct symbol *sym2)
+{
+	return sym2->type == S_INT || sym2->type == S_HEX ||
+	       (sym2->type == S_UNKNOWN && sym_string_valid(sym, sym2->name));
+}
+
+void sym_check_prop(struct symbol *sym)
+{
+	struct property *prop;
+	struct symbol *sym2;
+	for (prop = sym->prop; prop; prop = prop->next) {
+		switch (prop->type) {
+		case P_DEFAULT:
+			if ((sym->type == S_STRING || sym->type == S_INT || sym->type == S_HEX) &&
+			    prop->expr->type != E_SYMBOL)
+				prop_warn(prop,
+				    "default for config symbol '%'"
+				    " must be a single symbol", sym->name);
+			break;
+		case P_SELECT:
+			sym2 = prop_get_symbol(prop);
+			if (sym->type != S_BOOLEAN && sym->type != S_TRISTATE)
+				prop_warn(prop,
+				    "config symbol '%s' uses select, but is "
+				    "not boolean or tristate", sym->name);
+			else if (sym2->type != S_UNKNOWN &&
+			         sym2->type != S_BOOLEAN &&
+			         sym2->type != S_TRISTATE)
+				prop_warn(prop,
+				    "'%s' has wrong type. 'select' only "
+				    "accept arguments of boolean and "
+				    "tristate type", sym2->name);
+			break;
+		case P_RANGE:
+			if (sym->type != S_INT && sym->type != S_HEX)
+				prop_warn(prop, "range is only allowed "
+				                "for int or hex symbols");
+			if (!menu_range_valid_sym(sym, prop->expr->left.sym) ||
+			    !menu_range_valid_sym(sym, prop->expr->right.sym))
+				prop_warn(prop, "range is invalid");
+			break;
+		default:
+			;
+		}
+	}
+}
+
+void menu_finalize(struct menu *parent)
+{
+	struct menu *menu, *last_menu;
+	struct symbol *sym;
+	struct property *prop;
+	struct expr *parentdep, *basedep, *dep, *dep2, **ep;
+
+	sym = parent->sym;
+	if (parent->list) {
+		if (sym && sym_is_choice(sym)) {
+			/* find the first choice value and find out choice type */
+			for (menu = parent->list; menu; menu = menu->next) {
+				if (menu->sym) {
+					current_entry = parent;
+					if (sym->type == S_UNKNOWN)
+						menu_set_type(menu->sym->type);
+					current_entry = menu;
+					if (menu->sym->type == S_UNKNOWN)
+						menu_set_type(sym->type);
+					break;
+				}
+			}
+			parentdep = expr_alloc_symbol(sym);
+		} else if (parent->prompt)
+			parentdep = parent->prompt->visible.expr;
+		else
+			parentdep = parent->dep;
+
+		for (menu = parent->list; menu; menu = menu->next) {
+			basedep = expr_transform(menu->dep);
+			basedep = expr_alloc_and(expr_copy(parentdep), basedep);
+			basedep = expr_eliminate_dups(basedep);
+			menu->dep = basedep;
+			if (menu->sym)
+				prop = menu->sym->prop;
+			else
+				prop = menu->prompt;
+			for (; prop; prop = prop->next) {
+				if (prop->menu != menu)
+					continue;
+				dep = expr_transform(prop->visible.expr);
+				dep = expr_alloc_and(expr_copy(basedep), dep);
+				dep = expr_eliminate_dups(dep);
+				if (menu->sym && menu->sym->type != S_TRISTATE)
+					dep = expr_trans_bool(dep);
+				prop->visible.expr = dep;
+				if (prop->type == P_SELECT) {
+					struct symbol *es = prop_get_symbol(prop);
+					es->rev_dep.expr = expr_alloc_or(es->rev_dep.expr,
+							expr_alloc_and(expr_alloc_symbol(menu->sym), expr_copy(dep)));
+				}
+			}
+		}
+		for (menu = parent->list; menu; menu = menu->next)
+			menu_finalize(menu);
+	} else if (sym) {
+		basedep = parent->prompt ? parent->prompt->visible.expr : NULL;
+		basedep = expr_trans_compare(basedep, E_UNEQUAL, &symbol_no);
+		basedep = expr_eliminate_dups(expr_transform(basedep));
+		last_menu = NULL;
+		for (menu = parent->next; menu; menu = menu->next) {
+			dep = menu->prompt ? menu->prompt->visible.expr : menu->dep;
+			if (!expr_contains_symbol(dep, sym))
+				break;
+			if (expr_depends_symbol(dep, sym))
+				goto next;
+			dep = expr_trans_compare(dep, E_UNEQUAL, &symbol_no);
+			dep = expr_eliminate_dups(expr_transform(dep));
+			dep2 = expr_copy(basedep);
+			expr_eliminate_eq(&dep, &dep2);
+			expr_free(dep);
+			if (!expr_is_yes(dep2)) {
+				expr_free(dep2);
+				break;
+			}
+			expr_free(dep2);
+		next:
+			menu_finalize(menu);
+			menu->parent = parent;
+			last_menu = menu;
+		}
+		if (last_menu) {
+			parent->list = parent->next;
+			parent->next = last_menu->next;
+			last_menu->next = NULL;
+		}
+	}
+	for (menu = parent->list; menu; menu = menu->next) {
+		if (sym && sym_is_choice(sym) && menu->sym) {
+			menu->sym->flags |= SYMBOL_CHOICEVAL;
+			if (!menu->prompt)
+				menu_warn(menu, "choice value must have a prompt");
+			for (prop = menu->sym->prop; prop; prop = prop->next) {
+				if (prop->type == P_PROMPT && prop->menu != menu) {
+					prop_warn(prop, "choice values "
+					    "currently only support a "
+					    "single prompt");
+				}
+				if (prop->type == P_DEFAULT)
+					prop_warn(prop, "defaults for choice "
+					    "values not supported");
+			}
+			current_entry = menu;
+			if (menu->sym->type == S_UNKNOWN)
+				menu_set_type(sym->type);
+			/* Non-tristate choice values of tristate choices must
+			 * depend on the choice being set to Y. The choice
+			 * values' dependencies were propagated to their
+			 * properties above, so the change here must be re-
+			 * propagated. */
+			if (sym->type == S_TRISTATE && menu->sym->type != S_TRISTATE) {
+				basedep = expr_alloc_comp(E_EQUAL, sym, &symbol_yes);
+				basedep = expr_alloc_and(basedep, menu->dep);
+				basedep = expr_eliminate_dups(basedep);
+				menu->dep = basedep;
+				for (prop = menu->sym->prop; prop; prop = prop->next) {
+					if (prop->menu != menu)
+						continue;
+					dep = expr_alloc_and(expr_copy(basedep),
+							     prop->visible.expr);
+					dep = expr_eliminate_dups(dep);
+					dep = expr_trans_bool(dep);
+					prop->visible.expr = dep;
+					if (prop->type == P_SELECT) {
+						struct symbol *es = prop_get_symbol(prop);
+						dep2 = expr_alloc_symbol(menu->sym);
+						dep = expr_alloc_and(dep2,
+								     expr_copy(dep));
+						dep = expr_alloc_or(es->rev_dep.expr, dep);
+						dep = expr_eliminate_dups(dep);
+						es->rev_dep.expr = dep;
+					}
+				}
+			}
+			menu_add_symbol(P_CHOICE, sym, NULL);
+			prop = sym_get_choice_prop(sym);
+			for (ep = &prop->expr; *ep; ep = &(*ep)->left.expr)
+				;
+			*ep = expr_alloc_one(E_LIST, NULL);
+			(*ep)->right.sym = menu->sym;
+		}
+		if (menu->list && (!menu->prompt || !menu->prompt->text)) {
+			for (last_menu = menu->list; ; last_menu = last_menu->next) {
+				last_menu->parent = parent;
+				if (!last_menu->next)
+					break;
+			}
+			last_menu->next = menu->next;
+			menu->next = menu->list;
+			menu->list = NULL;
+		}
+	}
+
+	if (sym && !(sym->flags & SYMBOL_WARNED)) {
+		if (sym->type == S_UNKNOWN)
+			menu_warn(parent, "config symbol defined without type");
+
+		if (sym_is_choice(sym) && !parent->prompt)
+			menu_warn(parent, "choice must have a prompt");
+
+		/* Check properties connected to this symbol */
+		sym_check_prop(sym);
+		sym->flags |= SYMBOL_WARNED;
+	}
+
+	if (sym && !sym_is_optional(sym) && parent->prompt) {
+		sym->rev_dep.expr = expr_alloc_or(sym->rev_dep.expr,
+				expr_alloc_and(parent->prompt->visible.expr,
+					expr_alloc_symbol(&symbol_mod)));
+	}
+}
+
+bool menu_is_visible(struct menu *menu)
+{
+	struct menu *child;
+	struct symbol *sym;
+	tristate visible;
+
+	if (!menu->prompt)
+		return false;
+	sym = menu->sym;
+	if (sym) {
+		sym_calc_value(sym);
+		visible = menu->prompt->visible.tri;
+	} else
+		visible = menu->prompt->visible.tri = expr_calc_value(menu->prompt->visible.expr);
+
+	if (visible != no)
+		return true;
+	if (!sym || sym_get_tristate_value(menu->sym) == no)
+		return false;
+
+	for (child = menu->list; child; child = child->next)
+		if (menu_is_visible(child))
+			return true;
+	return false;
+}
+
+const char *menu_get_prompt(struct menu *menu)
+{
+	if (menu->prompt)
+		return menu->prompt->text;
+	else if (menu->sym)
+		return menu->sym->name;
+	return NULL;
+}
+
+struct menu *menu_get_root_menu(struct menu *menu)
+{
+	return &rootmenu;
+}
+
+struct menu *menu_get_parent_menu(struct menu *menu)
+{
+	enum prop_type type;
+
+	for (; menu != &rootmenu; menu = menu->parent) {
+		type = menu->prompt ? menu->prompt->type : 0;
+		if (type == P_MENU)
+			break;
+	}
+	return menu;
+}
+
+bool menu_has_help(struct menu *menu)
+{
+	return menu->help != NULL;
+}
+
+const char *menu_get_help(struct menu *menu)
+{
+	if (menu->help)
+		return menu->help;
+	else
+		return "";
+}

Added: trunk/coreboot-v2/util/kconfig/qconf.cc
===================================================================
--- trunk/coreboot-v2/util/kconfig/qconf.cc	                        (rev 0)
+++ trunk/coreboot-v2/util/kconfig/qconf.cc	2009-08-12 15:00:51 UTC (rev 4534)
@@ -0,0 +1,1764 @@
+/*
+ * Copyright (C) 2002 Roman Zippel <zippel at linux-m68k.org>
+ * Released under the terms of the GNU GPL v2.0.
+ */
+
+#include <qapplication.h>
+#include <qmainwindow.h>
+#include <qtoolbar.h>
+#include <qlayout.h>
+#include <qvbox.h>
+#include <qsplitter.h>
+#include <qlistview.h>
+#include <qtextbrowser.h>
+#include <qlineedit.h>
+#include <qlabel.h>
+#include <qpushbutton.h>
+#include <qmenubar.h>
+#include <qmessagebox.h>
+#include <qaction.h>
+#include <qheader.h>
+#include <qfiledialog.h>
+#include <qdragobject.h>
+#include <qregexp.h>
+
+#include <stdlib.h>
+
+#include "lkc.h"
+#include "qconf.h"
+
+#include "qconf.moc"
+#include "images.c"
+
+#ifdef _
+# undef _
+# define _ qgettext
+#endif
+
+static QApplication *configApp;
+static ConfigSettings *configSettings;
+
+QAction *ConfigMainWindow::saveAction;
+
+static inline QString qgettext(const char* str)
+{
+	return QString::fromLocal8Bit(gettext(str));
+}
+
+static inline QString qgettext(const QString& str)
+{
+	return QString::fromLocal8Bit(gettext(str.latin1()));
+}
+
+/**
+ * Reads a list of integer values from the application settings.
+ */
+QValueList<int> ConfigSettings::readSizes(const QString& key, bool *ok)
+{
+	QValueList<int> result;
+	QStringList entryList = readListEntry(key, ok);
+	if (ok) {
+		QStringList::Iterator it;
+		for (it = entryList.begin(); it != entryList.end(); ++it)
+			result.push_back((*it).toInt());
+	}
+
+	return result;
+}
+
+/**
+ * Writes a list of integer values to the application settings.
+ */
+bool ConfigSettings::writeSizes(const QString& key, const QValueList<int>& value)
+{
+	QStringList stringList;
+	QValueList<int>::ConstIterator it;
+
+	for (it = value.begin(); it != value.end(); ++it)
+		stringList.push_back(QString::number(*it));
+	return writeEntry(key, stringList);
+}
+
+
+#if QT_VERSION >= 300
+/*
+ * set the new data
+ * TODO check the value
+ */
+void ConfigItem::okRename(int col)
+{
+	Parent::okRename(col);
+	sym_set_string_value(menu->sym, text(dataColIdx).latin1());
+	listView()->updateList(this);
+}
+#endif
+
+/*
+ * update the displayed of a menu entry
+ */
+void ConfigItem::updateMenu(void)
+{
+	ConfigList* list;
+	struct symbol* sym;
+	struct property *prop;
+	QString prompt;
+	int type;
+	tristate expr;
+
+	list = listView();
+	if (goParent) {
+		setPixmap(promptColIdx, list->menuBackPix);
+		prompt = "..";
+		goto set_prompt;
+	}
+
+	sym = menu->sym;
+	prop = menu->prompt;
+	prompt = _(menu_get_prompt(menu));
+
+	if (prop) switch (prop->type) {
+	case P_MENU:
+		if (list->mode == singleMode || list->mode == symbolMode) {
+			/* a menuconfig entry is displayed differently
+			 * depending whether it's at the view root or a child.
+			 */
+			if (sym && list->rootEntry == menu)
+				break;
+			setPixmap(promptColIdx, list->menuPix);
+		} else {
+			if (sym)
+				break;
+			setPixmap(promptColIdx, 0);
+		}
+		goto set_prompt;
+	case P_COMMENT:
+		setPixmap(promptColIdx, 0);
+		goto set_prompt;
+	default:
+		;
+	}
+	if (!sym)
+		goto set_prompt;
+
+	setText(nameColIdx, QString::fromLocal8Bit(sym->name));
+
+	type = sym_get_type(sym);
+	switch (type) {
+	case S_BOOLEAN:
+	case S_TRISTATE:
+		char ch;
+
+		if (!sym_is_changable(sym) && !list->showAll) {
+			setPixmap(promptColIdx, 0);
+			setText(noColIdx, QString::null);
+			setText(modColIdx, QString::null);
+			setText(yesColIdx, QString::null);
+			break;
+		}
+		expr = sym_get_tristate_value(sym);
+		switch (expr) {
+		case yes:
+			if (sym_is_choice_value(sym) && type == S_BOOLEAN)
+				setPixmap(promptColIdx, list->choiceYesPix);
+			else
+				setPixmap(promptColIdx, list->symbolYesPix);
+			setText(yesColIdx, "Y");
+			ch = 'Y';
+			break;
+		case mod:
+			setPixmap(promptColIdx, list->symbolModPix);
+			setText(modColIdx, "M");
+			ch = 'M';
+			break;
+		default:
+			if (sym_is_choice_value(sym) && type == S_BOOLEAN)
+				setPixmap(promptColIdx, list->choiceNoPix);
+			else
+				setPixmap(promptColIdx, list->symbolNoPix);
+			setText(noColIdx, "N");
+			ch = 'N';
+			break;
+		}
+		if (expr != no)
+			setText(noColIdx, sym_tristate_within_range(sym, no) ? "_" : 0);
+		if (expr != mod)
+			setText(modColIdx, sym_tristate_within_range(sym, mod) ? "_" : 0);
+		if (expr != yes)
+			setText(yesColIdx, sym_tristate_within_range(sym, yes) ? "_" : 0);
+
+		setText(dataColIdx, QChar(ch));
+		break;
+	case S_INT:
+	case S_HEX:
+	case S_STRING:
+		const char* data;
+
+		data = sym_get_string_value(sym);
+
+#if QT_VERSION >= 300
+		int i = list->mapIdx(dataColIdx);
+		if (i >= 0)
+			setRenameEnabled(i, TRUE);
+#endif
+		setText(dataColIdx, data);
+		if (type == S_STRING)
+			prompt = QString("%1: %2").arg(prompt).arg(data);
+		else
+			prompt = QString("(%2) %1").arg(prompt).arg(data);
+		break;
+	}
+	if (!sym_has_value(sym) && visible)
+		prompt += _(" (NEW)");
+set_prompt:
+	setText(promptColIdx, prompt);
+}
+
+void ConfigItem::testUpdateMenu(bool v)
+{
+	ConfigItem* i;
+
+	visible = v;
+	if (!menu)
+		return;
+
+	sym_calc_value(menu->sym);
+	if (menu->flags & MENU_CHANGED) {
+		/* the menu entry changed, so update all list items */
+		menu->flags &= ~MENU_CHANGED;
+		for (i = (ConfigItem*)menu->data; i; i = i->nextItem)
+			i->updateMenu();
+	} else if (listView()->updateAll)
+		updateMenu();
+}
+
+void ConfigItem::paintCell(QPainter* p, const QColorGroup& cg, int column, int width, int align)
+{
+	ConfigList* list = listView();
+
+	if (visible) {
+		if (isSelected() && !list->hasFocus() && list->mode == menuMode)
+			Parent::paintCell(p, list->inactivedColorGroup, column, width, align);
+		else
+			Parent::paintCell(p, cg, column, width, align);
+	} else
+		Parent::paintCell(p, list->disabledColorGroup, column, width, align);
+}
+
+/*
+ * construct a menu entry
+ */
+void ConfigItem::init(void)
+{
+	if (menu) {
+		ConfigList* list = listView();
+		nextItem = (ConfigItem*)menu->data;
+		menu->data = this;
+
+		if (list->mode != fullMode)
+			setOpen(TRUE);
+		sym_calc_value(menu->sym);
+	}
+	updateMenu();
+}
+
+/*
+ * destruct a menu entry
+ */
+ConfigItem::~ConfigItem(void)
+{
+	if (menu) {
+		ConfigItem** ip = (ConfigItem**)&menu->data;
+		for (; *ip; ip = &(*ip)->nextItem) {
+			if (*ip == this) {
+				*ip = nextItem;
+				break;
+			}
+		}
+	}
+}
+
+ConfigLineEdit::ConfigLineEdit(ConfigView* parent)
+	: Parent(parent)
+{
+	connect(this, SIGNAL(lostFocus()), SLOT(hide()));
+}
+
+void ConfigLineEdit::show(ConfigItem* i)
+{
+	item = i;
+	if (sym_get_string_value(item->menu->sym))
+		setText(QString::fromLocal8Bit(sym_get_string_value(item->menu->sym)));
+	else
+		setText(QString::null);
+	Parent::show();
+	setFocus();
+}
+
+void ConfigLineEdit::keyPressEvent(QKeyEvent* e)
+{
+	switch (e->key()) {
+	case Key_Escape:
+		break;
+	case Key_Return:
+	case Key_Enter:
+		sym_set_string_value(item->menu->sym, text().latin1());
+		parent()->updateList(item);
+		break;
+	default:
+		Parent::keyPressEvent(e);
+		return;
+	}
+	e->accept();
+	parent()->list->setFocus();
+	hide();
+}
+
+ConfigList::ConfigList(ConfigView* p, const char *name)
+	: Parent(p, name),
+	  updateAll(false),
+	  symbolYesPix(xpm_symbol_yes), symbolModPix(xpm_symbol_mod), symbolNoPix(xpm_symbol_no),
+	  choiceYesPix(xpm_choice_yes), choiceNoPix(xpm_choice_no),
+	  menuPix(xpm_menu), menuInvPix(xpm_menu_inv), menuBackPix(xpm_menuback), voidPix(xpm_void),
+	  showAll(false), showName(false), showRange(false), showData(false),
+	  rootEntry(0), headerPopup(0)
+{
+	int i;
+
+	setSorting(-1);
+	setRootIsDecorated(TRUE);
+	disabledColorGroup = palette().active();
+	disabledColorGroup.setColor(QColorGroup::Text, palette().disabled().text());
+	inactivedColorGroup = palette().active();
+	inactivedColorGroup.setColor(QColorGroup::Highlight, palette().disabled().highlight());
+
+	connect(this, SIGNAL(selectionChanged(void)),
+		SLOT(updateSelection(void)));
+
+	if (name) {
+		configSettings->beginGroup(name);
+		showAll = configSettings->readBoolEntry("/showAll", false);
+		showName = configSettings->readBoolEntry("/showName", false);
+		showRange = configSettings->readBoolEntry("/showRange", false);
+		showData = configSettings->readBoolEntry("/showData", false);
+		configSettings->endGroup();
+		connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings()));
+	}
+
+	for (i = 0; i < colNr; i++)
+		colMap[i] = colRevMap[i] = -1;
+	addColumn(promptColIdx, _("Option"));
+
+	reinit();
+}
+
+void ConfigList::reinit(void)
+{
+	removeColumn(dataColIdx);
+	removeColumn(yesColIdx);
+	removeColumn(modColIdx);
+	removeColumn(noColIdx);
+	removeColumn(nameColIdx);
+
+	if (showName)
+		addColumn(nameColIdx, _("Name"));
+	if (showRange) {
+		addColumn(noColIdx, "N");
+		addColumn(modColIdx, "M");
+		addColumn(yesColIdx, "Y");
+	}
+	if (showData)
+		addColumn(dataColIdx, _("Value"));
+
+	updateListAll();
+}
+
+void ConfigList::saveSettings(void)
+{
+	if (name()) {
+		configSettings->beginGroup(name());
+		configSettings->writeEntry("/showName", showName);
+		configSettings->writeEntry("/showRange", showRange);
+		configSettings->writeEntry("/showData", showData);
+		configSettings->writeEntry("/showAll", showAll);
+		configSettings->endGroup();
+	}
+}
+
+ConfigItem* ConfigList::findConfigItem(struct menu *menu)
+{
+	ConfigItem* item = (ConfigItem*)menu->data;
+
+	for (; item; item = item->nextItem) {
+		if (this == item->listView())
+			break;
+	}
+
+	return item;
+}
+
+void ConfigList::updateSelection(void)
+{
+	struct menu *menu;
+	enum prop_type type;
+
+	ConfigItem* item = (ConfigItem*)selectedItem();
+	if (!item)
+		return;
+
+	menu = item->menu;
+	emit menuChanged(menu);
+	if (!menu)
+		return;
+	type = menu->prompt ? menu->prompt->type : P_UNKNOWN;
+	if (mode == menuMode && type == P_MENU)
+		emit menuSelected(menu);
+}
+
+void ConfigList::updateList(ConfigItem* item)
+{
+	ConfigItem* last = 0;
+
+	if (!rootEntry) {
+		if (mode != listMode)
+			goto update;
+		QListViewItemIterator it(this);
+		ConfigItem* item;
+
+		for (; it.current(); ++it) {
+			item = (ConfigItem*)it.current();
+			if (!item->menu)
+				continue;
+			item->testUpdateMenu(menu_is_visible(item->menu));
+		}
+		return;
+	}
+
+	if (rootEntry != &rootmenu && (mode == singleMode ||
+	    (mode == symbolMode && rootEntry->parent != &rootmenu))) {
+		item = firstChild();
+		if (!item)
+			item = new ConfigItem(this, 0, true);
+		last = item;
+	}
+	if ((mode == singleMode || (mode == symbolMode && !(rootEntry->flags & MENU_ROOT))) &&
+	    rootEntry->sym && rootEntry->prompt) {
+		item = last ? last->nextSibling() : firstChild();
+		if (!item)
+			item = new ConfigItem(this, last, rootEntry, true);
+		else
+			item->testUpdateMenu(true);
+
+		updateMenuList(item, rootEntry);
+		triggerUpdate();
+		return;
+	}
+update:
+	updateMenuList(this, rootEntry);
+	triggerUpdate();
+}
+
+void ConfigList::setValue(ConfigItem* item, tristate val)
+{
+	struct symbol* sym;
+	int type;
+	tristate oldval;
+
+	sym = item->menu ? item->menu->sym : 0;
+	if (!sym)
+		return;
+
+	type = sym_get_type(sym);
+	switch (type) {
+	case S_BOOLEAN:
+	case S_TRISTATE:
+		oldval = sym_get_tristate_value(sym);
+
+		if (!sym_set_tristate_value(sym, val))
+			return;
+		if (oldval == no && item->menu->list)
+			item->setOpen(TRUE);
+		parent()->updateList(item);
+		break;
+	}
+}
+
+void ConfigList::changeValue(ConfigItem* item)
+{
+	struct symbol* sym;
+	struct menu* menu;
+	int type, oldexpr, newexpr;
+
+	menu = item->menu;
+	if (!menu)
+		return;
+	sym = menu->sym;
+	if (!sym) {
+		if (item->menu->list)
+			item->setOpen(!item->isOpen());
+		return;
+	}
+
+	type = sym_get_type(sym);
+	switch (type) {
+	case S_BOOLEAN:
+	case S_TRISTATE:
+		oldexpr = sym_get_tristate_value(sym);
+		newexpr = sym_toggle_tristate_value(sym);
+		if (item->menu->list) {
+			if (oldexpr == newexpr)
+				item->setOpen(!item->isOpen());
+			else if (oldexpr == no)
+				item->setOpen(TRUE);
+		}
+		if (oldexpr != newexpr)
+			parent()->updateList(item);
+		break;
+	case S_INT:
+	case S_HEX:
+	case S_STRING:
+#if QT_VERSION >= 300
+		if (colMap[dataColIdx] >= 0)
+			item->startRename(colMap[dataColIdx]);
+		else
+#endif
+			parent()->lineEdit->show(item);
+		break;
+	}
+}
+
+void ConfigList::setRootMenu(struct menu *menu)
+{
+	enum prop_type type;
+
+	if (rootEntry == menu)
+		return;
+	type = menu && menu->prompt ? menu->prompt->type : P_UNKNOWN;
+	if (type != P_MENU)
+		return;
+	updateMenuList(this, 0);
+	rootEntry = menu;
+	updateListAll();
+	setSelected(currentItem(), hasFocus());
+	ensureItemVisible(currentItem());
+}
+
+void ConfigList::setParentMenu(void)
+{
+	ConfigItem* item;
+	struct menu *oldroot;
+
+	oldroot = rootEntry;
+	if (rootEntry == &rootmenu)
+		return;
+	setRootMenu(menu_get_parent_menu(rootEntry->parent));
+
+	QListViewItemIterator it(this);
+	for (; (item = (ConfigItem*)it.current()); it++) {
+		if (item->menu == oldroot) {
+			setCurrentItem(item);
+			ensureItemVisible(item);
+			break;
+		}
+	}
+}
+
+/*
+ * update all the children of a menu entry
+ *   removes/adds the entries from the parent widget as necessary
+ *
+ * parent: either the menu list widget or a menu entry widget
+ * menu: entry to be updated
+ */
+template <class P>
+void ConfigList::updateMenuList(P* parent, struct menu* menu)
+{
+	struct menu* child;
+	ConfigItem* item;
+	ConfigItem* last;
+	bool visible;
+	enum prop_type type;
+
+	if (!menu) {
+		while ((item = parent->firstChild()))
+			delete item;
+		return;
+	}
+
+	last = parent->firstChild();
+	if (last && !last->goParent)
+		last = 0;
+	for (child = menu->list; child; child = child->next) {
+		item = last ? last->nextSibling() : parent->firstChild();
+		type = child->prompt ? child->prompt->type : P_UNKNOWN;
+
+		switch (mode) {
+		case menuMode:
+			if (!(child->flags & MENU_ROOT))
+				goto hide;
+			break;
+		case symbolMode:
+			if (child->flags & MENU_ROOT)
+				goto hide;
+			break;
+		default:
+			break;
+		}
+
+		visible = menu_is_visible(child);
+		if (showAll || visible) {
+			if (!child->sym && !child->list && !child->prompt)
+				continue;
+			if (!item || item->menu != child)
+				item = new ConfigItem(parent, last, child, visible);
+			else
+				item->testUpdateMenu(visible);
+
+			if (mode == fullMode || mode == menuMode || type != P_MENU)
+				updateMenuList(item, child);
+			else
+				updateMenuList(item, 0);
+			last = item;
+			continue;
+		}
+	hide:
+		if (item && item->menu == child) {
+			last = parent->firstChild();
+			if (last == item)
+				last = 0;
+			else while (last->nextSibling() != item)
+				last = last->nextSibling();
+			delete item;
+		}
+	}
+}
+
+void ConfigList::keyPressEvent(QKeyEvent* ev)
+{
+	QListViewItem* i = currentItem();
+	ConfigItem* item;
+	struct menu *menu;
+	enum prop_type type;
+
+	if (ev->key() == Key_Escape && mode != fullMode && mode != listMode) {
+		emit parentSelected();
+		ev->accept();
+		return;
+	}
+
+	if (!i) {
+		Parent::keyPressEvent(ev);
+		return;
+	}
+	item = (ConfigItem*)i;
+
+	switch (ev->key()) {
+	case Key_Return:
+	case Key_Enter:
+		if (item->goParent) {
+			emit parentSelected();
+			break;
+		}
+		menu = item->menu;
+		if (!menu)
+			break;
+		type = menu->prompt ? menu->prompt->type : P_UNKNOWN;
+		if (type == P_MENU && rootEntry != menu &&
+		    mode != fullMode && mode != menuMode) {
+			emit menuSelected(menu);
+			break;
+		}
+	case Key_Space:
+		changeValue(item);
+		break;
+	case Key_N:
+		setValue(item, no);
+		break;
+	case Key_M:
+		setValue(item, mod);
+		break;
+	case Key_Y:
+		setValue(item, yes);
+		break;
+	default:
+		Parent::keyPressEvent(ev);
+		return;
+	}
+	ev->accept();
+}
+
+void ConfigList::contentsMousePressEvent(QMouseEvent* e)
+{
+	//QPoint p(contentsToViewport(e->pos()));
+	//printf("contentsMousePressEvent: %d,%d\n", p.x(), p.y());
+	Parent::contentsMousePressEvent(e);
+}
+
+void ConfigList::contentsMouseReleaseEvent(QMouseEvent* e)
+{
+	QPoint p(contentsToViewport(e->pos()));
+	ConfigItem* item = (ConfigItem*)itemAt(p);
+	struct menu *menu;
+	enum prop_type ptype;
+	const QPixmap* pm;
+	int idx, x;
+
+	if (!item)
+		goto skip;
+
+	menu = item->menu;
+	x = header()->offset() + p.x();
+	idx = colRevMap[header()->sectionAt(x)];
+	switch (idx) {
+	case promptColIdx:
+		pm = item->pixmap(promptColIdx);
+		if (pm) {
+			int off = header()->sectionPos(0) + itemMargin() +
+				treeStepSize() * (item->depth() + (rootIsDecorated() ? 1 : 0));
+			if (x >= off && x < off + pm->width()) {
+				if (item->goParent) {
+					emit parentSelected();
+					break;
+				} else if (!menu)
+					break;
+				ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN;
+				if (ptype == P_MENU && rootEntry != menu &&
+				    mode != fullMode && mode != menuMode)
+					emit menuSelected(menu);
+				else
+					changeValue(item);
+			}
+		}
+		break;
+	case noColIdx:
+		setValue(item, no);
+		break;
+	case modColIdx:
+		setValue(item, mod);
+		break;
+	case yesColIdx:
+		setValue(item, yes);
+		break;
+	case dataColIdx:
+		changeValue(item);
+		break;
+	}
+
+skip:
+	//printf("contentsMouseReleaseEvent: %d,%d\n", p.x(), p.y());
+	Parent::contentsMouseReleaseEvent(e);
+}
+
+void ConfigList::contentsMouseMoveEvent(QMouseEvent* e)
+{
+	//QPoint p(contentsToViewport(e->pos()));
+	//printf("contentsMouseMoveEvent: %d,%d\n", p.x(), p.y());
+	Parent::contentsMouseMoveEvent(e);
+}
+
+void ConfigList::contentsMouseDoubleClickEvent(QMouseEvent* e)
+{
+	QPoint p(contentsToViewport(e->pos()));
+	ConfigItem* item = (ConfigItem*)itemAt(p);
+	struct menu *menu;
+	enum prop_type ptype;
+
+	if (!item)
+		goto skip;
+	if (item->goParent) {
+		emit parentSelected();
+		goto skip;
+	}
+	menu = item->menu;
+	if (!menu)
+		goto skip;
+	ptype = menu->prompt ? menu->prompt->type : P_UNKNOWN;
+	if (ptype == P_MENU && (mode == singleMode || mode == symbolMode))
+		emit menuSelected(menu);
+	else if (menu->sym)
+		changeValue(item);
+
+skip:
+	//printf("contentsMouseDoubleClickEvent: %d,%d\n", p.x(), p.y());
+	Parent::contentsMouseDoubleClickEvent(e);
+}
+
+void ConfigList::focusInEvent(QFocusEvent *e)
+{
+	struct menu *menu = NULL;
+
+	Parent::focusInEvent(e);
+
+	ConfigItem* item = (ConfigItem *)currentItem();
+	if (item) {
+		setSelected(item, TRUE);
+		menu = item->menu;
+	}
+	emit gotFocus(menu);
+}
+
+void ConfigList::contextMenuEvent(QContextMenuEvent *e)
+{
+	if (e->y() <= header()->geometry().bottom()) {
+		if (!headerPopup) {
+			QAction *action;
+
+			headerPopup = new QPopupMenu(this);
+			action = new QAction(NULL, _("Show Name"), 0, this);
+			  action->setToggleAction(TRUE);
+			  connect(action, SIGNAL(toggled(bool)),
+				  parent(), SLOT(setShowName(bool)));
+			  connect(parent(), SIGNAL(showNameChanged(bool)),
+				  action, SLOT(setOn(bool)));
+			  action->setOn(showName);
+			  action->addTo(headerPopup);
+			action = new QAction(NULL, _("Show Range"), 0, this);
+			  action->setToggleAction(TRUE);
+			  connect(action, SIGNAL(toggled(bool)),
+				  parent(), SLOT(setShowRange(bool)));
+			  connect(parent(), SIGNAL(showRangeChanged(bool)),
+				  action, SLOT(setOn(bool)));
+			  action->setOn(showRange);
+			  action->addTo(headerPopup);
+			action = new QAction(NULL, _("Show Data"), 0, this);
+			  action->setToggleAction(TRUE);
+			  connect(action, SIGNAL(toggled(bool)),
+				  parent(), SLOT(setShowData(bool)));
+			  connect(parent(), SIGNAL(showDataChanged(bool)),
+				  action, SLOT(setOn(bool)));
+			  action->setOn(showData);
+			  action->addTo(headerPopup);
+		}
+		headerPopup->exec(e->globalPos());
+		e->accept();
+	} else
+		e->ignore();
+}
+
+ConfigView* ConfigView::viewList;
+
+ConfigView::ConfigView(QWidget* parent, const char *name)
+	: Parent(parent, name)
+{
+	list = new ConfigList(this, name);
+	lineEdit = new ConfigLineEdit(this);
+	lineEdit->hide();
+
+	this->nextView = viewList;
+	viewList = this;
+}
+
+ConfigView::~ConfigView(void)
+{
+	ConfigView** vp;
+
+	for (vp = &viewList; *vp; vp = &(*vp)->nextView) {
+		if (*vp == this) {
+			*vp = nextView;
+			break;
+		}
+	}
+}
+
+void ConfigView::setShowAll(bool b)
+{
+	if (list->showAll != b) {
+		list->showAll = b;
+		list->updateListAll();
+		emit showAllChanged(b);
+	}
+}
+
+void ConfigView::setShowName(bool b)
+{
+	if (list->showName != b) {
+		list->showName = b;
+		list->reinit();
+		emit showNameChanged(b);
+	}
+}
+
+void ConfigView::setShowRange(bool b)
+{
+	if (list->showRange != b) {
+		list->showRange = b;
+		list->reinit();
+		emit showRangeChanged(b);
+	}
+}
+
+void ConfigView::setShowData(bool b)
+{
+	if (list->showData != b) {
+		list->showData = b;
+		list->reinit();
+		emit showDataChanged(b);
+	}
+}
+
+void ConfigList::setAllOpen(bool open)
+{
+	QListViewItemIterator it(this);
+
+	for (; it.current(); it++)
+		it.current()->setOpen(open);
+}
+
+void ConfigView::updateList(ConfigItem* item)
+{
+	ConfigView* v;
+
+	for (v = viewList; v; v = v->nextView)
+		v->list->updateList(item);
+}
+
+void ConfigView::updateListAll(void)
+{
+	ConfigView* v;
+
+	for (v = viewList; v; v = v->nextView)
+		v->list->updateListAll();
+}
+
+ConfigInfoView::ConfigInfoView(QWidget* parent, const char *name)
+	: Parent(parent, name), menu(0), sym(0)
+{
+	if (name) {
+		configSettings->beginGroup(name);
+		_showDebug = configSettings->readBoolEntry("/showDebug", false);
+		configSettings->endGroup();
+		connect(configApp, SIGNAL(aboutToQuit()), SLOT(saveSettings()));
+	}
+}
+
+void ConfigInfoView::saveSettings(void)
+{
+	if (name()) {
+		configSettings->beginGroup(name());
+		configSettings->writeEntry("/showDebug", showDebug());
+		configSettings->endGroup();
+	}
+}
+
+void ConfigInfoView::setShowDebug(bool b)
+{
+	if (_showDebug != b) {
+		_showDebug = b;
+		if (menu)
+			menuInfo();
+		else if (sym)
+			symbolInfo();
+		emit showDebugChanged(b);
+	}
+}
+
+void ConfigInfoView::setInfo(struct menu *m)
+{
+	if (menu == m)
+		return;
+	menu = m;
+	sym = NULL;
+	if (!menu)
+		clear();
+	else
+		menuInfo();
+}
+
+void ConfigInfoView::setSource(const QString& name)
+{
+	const char *p = name.latin1();
+
+	menu = NULL;
+	sym = NULL;
+
+	switch (p[0]) {
+	case 'm':
+		struct menu *m;
+
+		if (sscanf(p, "m%p", &m) == 1 && menu != m) {
+			menu = m;
+			menuInfo();
+			emit menuSelected(menu);
+		}
+		break;
+	case 's':
+		struct symbol *s;
+
+		if (sscanf(p, "s%p", &s) == 1 && sym != s) {
+			sym = s;
+			symbolInfo();
+		}
+		break;
+	}
+}
+
+void ConfigInfoView::symbolInfo(void)
+{
+	QString str;
+
+	str += "<big>Symbol: <b>";
+	str += print_filter(sym->name);
+	str += "</b></big><br><br>value: ";
+	str += print_filter(sym_get_string_value(sym));
+	str += "<br>visibility: ";
+	str += sym->visible == yes ? "y" : sym->visible == mod ? "m" : "n";
+	str += "<br>";
+	str += debug_info(sym);
+
+	setText(str);
+}
+
+void ConfigInfoView::menuInfo(void)
+{
+	struct symbol* sym;
+	QString head, debug, help;
+
+	sym = menu->sym;
+	if (sym) {
+		if (menu->prompt) {
+			head += "<big><b>";
+			head += print_filter(_(menu->prompt->text));
+			head += "</b></big>";
+			if (sym->name) {
+				head += " (";
+				if (showDebug())
+					head += QString().sprintf("<a href=\"s%p\">", sym);
+				head += print_filter(sym->name);
+				if (showDebug())
+					head += "</a>";
+				head += ")";
+			}
+		} else if (sym->name) {
+			head += "<big><b>";
+			if (showDebug())
+				head += QString().sprintf("<a href=\"s%p\">", sym);
+			head += print_filter(sym->name);
+			if (showDebug())
+				head += "</a>";
+			head += "</b></big>";
+		}
+		head += "<br><br>";
+
+		if (showDebug())
+			debug = debug_info(sym);
+
+		help = menu_get_help(menu);
+		/* Gettextize if the help text not empty */
+		if (help.isEmpty())
+			help = print_filter(menu_get_help(menu));
+		else
+			help = print_filter(_(menu_get_help(menu)));
+	} else if (menu->prompt) {
+		head += "<big><b>";
+