[coreboot] [patch] Patches for CN400 / EPIA-N / VT8237R

Myles Watson mylesgw at gmail.com
Mon Aug 10 17:32:49 CEST 2009

> -----Original Message-----
> From: coreboot-bounces at coreboot.org [mailto:coreboot-bounces at coreboot.org]
> On Behalf Of Harrison, Jon (SELEX GALILEO, UK)
> Sent: Thursday, August 06, 2009 5:46 AM
> To: coreboot at coreboot.org
> Subject: [coreboot] [patch] Patches for CN400 / EPIA-N / VT8237R
> Dear Corebooters,
> Please find attached a number of patches that get the Via
> EPIA-N(L)/CN400 to a reasonable level of maturity::
> Tested on Via EPIA-NL8000EG with FILO payload booting FC9 (2.6.25
> kernel) from SATA HDD.
Good work!

> ACPI is working for PCI interrupt routing, some memory stuff and
> Soft-Off.
> USB/SATA Working
> VGA Console Working
> X Working via Onboard AGP
> There are a total of four patches::
> *********************
> pci_ids.patch (apply at src/include level)::
> Adds a couple of VT8237R Ids for the USB UHCI/EHCI interfaces.

> This is a dependency for all that follows.
> *********************
> vt8237r.patch (apply at src/southbridge level)::
> This uses the CONFIG_EPIA_VT8237R_INIT option to customise SB init for
> the EPIA-N
> The main differences between the EPIA-N init and what is already there
> is that the Via C3 CPU uses the secondary APIC bus rather than FSB for
> IOAPIC to LAPIC comms.

	res->base = VT8237R_APIC_BASE;
 	res->size = 256;
-	res->limit = 0xffffffffUL;
+	res->limit = res->base + res->size - 1;
+	res->align = 8;
+	res->gran = 8;

The limit should be 0xffffffff for mem resources unless they are 64 bit.

-	res = new_resource(dev, 1);
-	res->base = 0x0UL;
-	res->size = 0x1000UL;
-	res->limit = 0xffffUL;

Why did you want to remove this reserved region?  It just makes it so that
allocations have to be above 0x1000.  It doesn't affect other fixed regions.

> There are a few other EPIA MoBo specific tweaks in there too.
> This is a dependency for all that follows
> *********************
> cn400.patch (apply at src/northbridge level)::
> Fixes for Vlink, RAM, Performance and Video
> This is a dependency for all that follows.
> *********************
> epia-n.patch (apply at src/motherboard level)::
> Adds ACPI/APIC Support to EPIA-N
> irq_tables.c is chaged to one generated from an earlier version of
> getpir in reponse to issues raised with other ports on the code header
> from newer versions of the tool

Why is the compiled dsdt in the tree?  It looks like the source is there

> I have tried to keep any whitespace/comment only changes to a minimum.
I'd appreciate it if you'd remove any white space at the end of lines.  You
should be able to use find/replace in the patches.

Search for + at the beginning of the line with whitespace at the end. 
in vi: /^+.*[\t ][\t ]*$


More information about the coreboot mailing list