[coreboot] malloc.c problems of option rom
Jason Wang
wangqingpei at gmail.com
Sat Aug 1 22:27:36 CEST 2009
Hi all,
I added some printf message into malloc.c, and find that the function
setup() which used to init the memory seems not executed very well.
I put my own malloc.c and the log attached to this mail. Hope some one can
help me to find out the problems.
static void setup(void)
{
int size = (unsigned int)(&_eheap - &_heap) - HDRSIZE;
*((hdrtype_t *) hstart) = FREE_BLOCK(size);
printf("%s the memory size:0x%x,begin:0x%x end:0x%x,
hstart:0x%x\n",__func__,size,(unsigned int)&_heap,(unsigned
int)&_eheap,(unsigned int )*((hdrtype_t *) hstart));
}
static void *alloc(int len)
{
hdrtype_t header;
void *ptr = hstart;
printf("%s length=0x%x, the ptr=0x%x\n",__func__,len,(unsigned int
)*((hdrtype_t*)ptr));
printf("%s the memory begin:0x%x end:0x%x,
hstart:0x%x\n",__func__,(unsigned int)&_heap,(unsigned int)&_eheap,(unsigned
int )*((hdrtype_t *) hstart));
/* Align the size. */
len = (len + 3) & ~3;
if (!len || len > 0xffffff)
return (void *)NULL;
/* Make sure the region is setup correctly. */
if (!HAS_MAGIC(*((hdrtype_t *) ptr)))
setup();
if (!HAS_MAGIC(*((hdrtype_t *) ptr))){
printf("set up failed,ptr=0x%x\n",(unsigned int)*((hdrtype_t *)
ptr));
}
/* Find some free space. */
do {
header = *((hdrtype_t *) ptr);
int size = SIZE(header);
if (!HAS_MAGIC(header) || size == 0) {
printf("memory allocator panic!!! the size=0x%x.
header=0x%x\n",size,(unsigned int)header);
halt();
}
if (header & FLAG_FREE) {
if (len <= size) {
void *nptr = ptr + (HDRSIZE + len);
int nsize = size - (HDRSIZE + len);
/* If there is still room in this block,
* then mark it as such otherwise account
* the whole space for that block.
*/
if (nsize > 0) {
/* Mark the block as used. */
*((hdrtype_t *) ptr) = USED_BLOCK(len);
/* Create a new free block. */
*((hdrtype_t *) nptr) =
FREE_BLOCK(nsize);
} else {
/* Mark the block as used. */
*((hdrtype_t *) ptr) = USED_BLOCK(size);
}
return (void *)(ptr + HDRSIZE);
}
}
ptr += HDRSIZE + size;
} while (ptr < hend);
/* Nothing available. */
return (void *)NULL;
}
log:
Attempting to init PCI bdf 06:05.0 (dev/ven 30381106)
Copying option rom (size 130560) from 0xfff00000 to ce000
Checking rom 0x000ce000 (sig aa55 size 255)
Running option rom at ce00:0003
hello, initialize_usb
00:13.0 4387:1002.0 OHCI controller
Not supported.
00:13.1 4388:1002.1 OHCI controller
Not supported.
00:13.2 4389:1002.2 OHCI controller
Not supported.
00:13.3 438a:1002.3 OHCI controller
Not supported.
00:13.4 438b:1002.4 OHCI controller
Not supported.
00:13.5 4386:1002.5 EHCI controller
Not supported.
00:05.0 3038:1106.0 UHCI controller
alloc length=0x238, the ptr=0x0
alloc the memory begin:0x7860 end:0x57860, hstart:0x0
setup the memory size:0x4fffc,begin:0x7860 end:0x57860, hstart:0xaa04fffc
set up failed,ptr=0x0
memory allocator panic!!! the size=0x0. header=0x0
--
Jason Wang
Peking University
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/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* This is a classically weak malloc() implementation. We have a relatively
* small and static heap, so we take the easy route with an O(N) loop
* through the tree for every malloc() and free(). Obviously, this doesn't
* scale past a few hundred KB (if that).
*
* We're also susceptible to the usual buffer overrun poisoning, though the
* risk is within acceptable ranges for this implementation (don't overrun
* your buffers, kids!).
*/
#include <libpayload.h>
extern char _heap, _eheap; /* Defined in the ldscript. */
static void *hstart = (void *)&_heap;
static void *hend = (void *)&_eheap;
typedef unsigned int hdrtype_t;
#define MAGIC (0x2a << 26)
#define FLAG_FREE (1 << 25)
#define FLAG_USED (1 << 24)
#define SIZE(_h) ((_h) & 0xFFFFFF)
#define _HEADER(_s, _f) ((hdrtype_t) (MAGIC | (_f) | ((_s) & 0xFFFFFF)))
#define FREE_BLOCK(_s) _HEADER(_s, FLAG_FREE)
#define USED_BLOCK(_s) _HEADER(_s, FLAG_USED)
#define HDRSIZE (sizeof(hdrtype_t))
#define IS_FREE(_h) (((_h) & (MAGIC | FLAG_FREE)) == (MAGIC | FLAG_FREE))
#define HAS_MAGIC(_h) (((_h) & MAGIC) == MAGIC)
static int free_aligned(void* addr);
void print_malloc_map(void);
static void setup(void)
{
int size = (unsigned int)(&_eheap - &_heap) - HDRSIZE;
*((hdrtype_t *) hstart) = FREE_BLOCK(size);
printf("%s the memory size:0x%x,begin:0x%x end:0x%x, hstart:0x%x\n",__func__,size,(unsigned int)&_heap,(unsigned int)&_eheap,(unsigned int )*((hdrtype_t *) hstart));
}
static void *alloc(int len)
{
hdrtype_t header;
void *ptr = hstart;
printf("%s length=0x%x, the ptr=0x%x\n",__func__,len,(unsigned int )*((hdrtype_t*)ptr));
printf("%s the memory begin:0x%x end:0x%x, hstart:0x%x\n",__func__,(unsigned int)&_heap,(unsigned int)&_eheap,(unsigned int )*((hdrtype_t *) hstart));
/* Align the size. */
len = (len + 3) & ~3;
if (!len || len > 0xffffff)
return (void *)NULL;
/* Make sure the region is setup correctly. */
if (!HAS_MAGIC(*((hdrtype_t *) ptr)))
setup();
if (!HAS_MAGIC(*((hdrtype_t *) ptr))){
printf("set up failed,ptr=0x%x\n",(unsigned int)*((hdrtype_t *) ptr));
}
/* Find some free space. */
do {
header = *((hdrtype_t *) ptr);
int size = SIZE(header);
if (!HAS_MAGIC(header) || size == 0) {
printf("memory allocator panic!!! the size=0x%x. header=0x%x\n",size,(unsigned int)header);
halt();
}
if (header & FLAG_FREE) {
if (len <= size) {
void *nptr = ptr + (HDRSIZE + len);
int nsize = size - (HDRSIZE + len);
/* If there is still room in this block,
* then mark it as such otherwise account
* the whole space for that block.
*/
if (nsize > 0) {
/* Mark the block as used. */
*((hdrtype_t *) ptr) = USED_BLOCK(len);
/* Create a new free block. */
*((hdrtype_t *) nptr) =
FREE_BLOCK(nsize);
} else {
/* Mark the block as used. */
*((hdrtype_t *) ptr) = USED_BLOCK(size);
}
return (void *)(ptr + HDRSIZE);
}
}
ptr += HDRSIZE + size;
} while (ptr < hend);
/* Nothing available. */
return (void *)NULL;
}
static void _consolidate(void)
{
void *ptr = hstart;
while (ptr < hend) {
void *nptr;
hdrtype_t hdr = *((hdrtype_t *) ptr);
unsigned int size = 0;
if (!IS_FREE(hdr)) {
ptr += HDRSIZE + SIZE(hdr);
continue;
}
size = SIZE(hdr);
nptr = ptr + HDRSIZE + SIZE(hdr);
while (nptr < hend) {
hdrtype_t nhdr = *((hdrtype_t *) nptr);
if (!(IS_FREE(nhdr)))
break;
size += SIZE(nhdr) + HDRSIZE;
*((hdrtype_t *) nptr) = 0;
nptr += (HDRSIZE + SIZE(nhdr));
}
*((hdrtype_t *) ptr) = FREE_BLOCK(size);
ptr = nptr;
}
}
void free(void *ptr)
{
hdrtype_t hdr;
if (free_aligned(ptr)) return;
ptr -= HDRSIZE;
/* Sanity check. */
if (ptr < hstart || ptr >= hend)
return;
hdr = *((hdrtype_t *) ptr);
/* Not our header (we're probably poisoned). */
if (!HAS_MAGIC(hdr))
return;
/* Double free. */
if (hdr & FLAG_FREE)
return;
*((hdrtype_t *) ptr) = FREE_BLOCK(SIZE(hdr));
_consolidate();
}
void *malloc(size_t size)
{
return alloc(size);
}
void *calloc(size_t nmemb, size_t size)
{
size_t total = nmemb * size;
void *ptr = alloc(total);
if (ptr)
memset(ptr, 0, total);
return ptr;
}
void *realloc(void *ptr, size_t size)
{
void *ret, *pptr;
unsigned int osize;
if (ptr == NULL)
return alloc(size);
pptr = ptr - HDRSIZE;
if (!HAS_MAGIC(*((hdrtype_t *) pptr)))
return NULL;
/* Get the original size of the block. */
osize = SIZE(*((hdrtype_t *) pptr));
/*
* Free the memory to update the tables - this won't touch the actual
* memory, so we can still use it for the copy after we have
* reallocated the new space.
*/
free(ptr);
ret = alloc(size);
/*
* if ret == NULL, then doh - failure.
* if ret == ptr then woo-hoo! no copy needed.
*/
if (ret == NULL || ret == ptr)
return ret;
/* Copy the memory to the new location. */
memcpy(ret, ptr, osize > size ? size : osize);
return ret;
}
struct align_region_t
{
int alignment;
/* start in memory, and size in bytes */
void* start;
int size;
/* layout within a region:
- num_elements bytes, 0: free, 1: used, 2: used, combines with next
- padding to alignment
- data section
- waste space
start_data points to the start of the data section
*/
void* start_data;
/* number of free blocks sized "alignment" */
int free;
struct align_region_t *next;
};
static struct align_region_t* align_regions = 0;
static struct align_region_t *allocate_region(struct align_region_t *old_first, int alignment, int num_elements)
{
struct align_region_t *new_region = malloc(sizeof(struct align_region_t));
new_region->alignment = alignment;
new_region->start = malloc((num_elements+1) * alignment + num_elements);
new_region->start_data = (void*)((u32)(new_region->start + num_elements + alignment - 1) & (~(alignment-1)));
new_region->size = num_elements * alignment;
new_region->free = num_elements;
new_region->next = old_first;
memset(new_region->start, 0, num_elements);
return new_region;
}
static int free_aligned(void* addr)
{
struct align_region_t *reg = align_regions;
while (reg != 0)
{
if ((addr >= reg->start_data) && (addr < reg->start_data + reg->size))
{
int i = (addr-reg->start_data)/reg->alignment;
while (((u8*)reg->start)[i]==2)
{
((u8*)reg->start)[i++]=0;
reg->free++;
}
((u8*)reg->start)[i]=0;
reg->free++;
return 1;
}
reg = reg->next;
}
return 0;
}
void *memalign(size_t align, size_t size)
{
if (size == 0) return 0;
if (align_regions == 0) {
align_regions = malloc(sizeof(struct align_region_t));
if (align_regions == NULL)
return NULL;
memset(align_regions, 0, sizeof(struct align_region_t));
}
struct align_region_t *reg = align_regions;
look_further:
while (reg != 0)
{
if ((reg->alignment == align) && (reg->free >= (size + align - 1)/align))
{
break;
}
reg = reg->next;
}
if (reg == 0)
{
align_regions = allocate_region(align_regions, align, (size/align<99)?100:((size/align)+1));
reg = align_regions;
}
int i, count = 0, target = (size+align-1)/align;
for (i = 0; i < (reg->size/align); i++)
{
if (((u8*)reg->start)[i] == 0)
{
count++;
if (count == target) {
count = i+1-count;
for (i=0; i<target-1; i++)
{
((u8*)reg->start)[count+i]=2;
}
((u8*)reg->start)[count+target-1]=1;
reg->free -= target;
return reg->start_data+(align*count);
}
} else {
count = 0;
}
}
goto look_further; // end condition is once a new region is allocated - it always has enough space
}
/* This is for debugging purposes. */
#ifdef TEST
void print_malloc_map(void)
{
void *ptr = hstart;
while (ptr < hend) {
hdrtype_t hdr = *((hdrtype_t *) ptr);
if (!HAS_MAGIC(hdr)) {
printf("Poisoned magic - we're toast\n");
break;
}
/* FIXME: Verify the size of the block. */
printf("%x: %s (%x bytes)\n",
(unsigned int)(ptr - hstart),
hdr & FLAG_FREE ? "FREE" : "USED", SIZE(hdr));
ptr += HDRSIZE + SIZE(hdr);
}
}
#endif
-------------- next part --------------
coreboot-2.0.0-r4253M Tue Jul 28 03:50:01 CST 2009 starting...
bsp_apicid=0x0
core0 started:
01SBLink=00
NC node|link=00
rs690_early_setup()
get_cpu_rev EAX=0x60f82.
CPU Rev is K8_G0.
NB Revision is A12.
k8_optimization()
rs690_por_init
sb600_early_setup()
sb600_devices_por_init()
sb600_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is 0x13
sb600_devices_por_init(): IDE Device, BDF:0-20-1
sb600_devices_por_init(): LPC Device, BDF:0-20-3
sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
sb600_devices_por_init(): SATA Device, BDF:0-18-0
sb600_pmio_por_init()
begin msr fid, vid: hi=0x32111e1e, lo=0x110d0000
Current fid_cur: 0x0, fid_max: 0xd
Requested fid_new: 0xd
FidVid table step fidvid: 0xa
FidVid table step fidvid: 0xa
200MHZ step fidvid: 0xc
200MHZ step fidvid: 0xc
200MHZ step fidvid: 0xc
200MHZ step fidvid: 0xc
100MHZ step fidvid: 0xd
end msr fid, vid: hi=0x32111e11, lo=0x110d000d
needs_reset=0x1
ht reset -
coreboot-2.0.0-r4253M Tue Jul 28 03:50:01 CST 2009 starting...
bsp_apicid=0x0
core0 started:
01SBLink=00
NC node|link=00
rs690_early_setup()
get_cpu_rev EAX=0x60f82.
CPU Rev is K8_G0.
NB Revision is A12.
k8_optimization()
rs690_por_init
sb600_early_setup()
sb600_devices_por_init()
sb600_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is 0x13
sb600_devices_por_init(): IDE Device, BDF:0-20-1
sb600_devices_por_init(): LPC Device, BDF:0-20-3
sb600_devices_por_init(): P2P Bridge, BDF:0-20-4
sb600_devices_por_init(): SATA Device, BDF:0-18-0
sb600_pmio_por_init()
begin msr fid, vid: hi=0x32111e11, lo=0x110d000d
end msr fid, vid: hi=0x32111e11, lo=0x110d000d
needs_reset=0x0
sysinfo->nodes: 1 sysinfo->ctrl: cf188 spd_addr: ffffa348
Ram1.00
Ram2.00
sdram_set_spd_registers: paramx :000cece4
Unbuffered
400MHz
400MHz
RAM: 0x00100000 kB
Ram3
sdram_enable: tsc0[8]: 000ceda4Initializing memory: done
Setting variable MTRR 2, base: 0MB, range: 1024MB, type WB
DQS Training:RcvrEn:Pass1: 00
CTLRMaxDelay=15
done
DQS Training:DQSPos: 00
TrainDQSRdWrPos: buf_a:000ce870
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
TrainDQSPos: MutualCSPassW[48] :000ce754
done
DQS Training:RcvrEn:Pass2: 00
CTLRMaxDelay=2c
done
DQS SAVE NVRAM: c2000
DQS Training:tsc[00]=0000000018251b35
DQS Training:tsc[01]=00000000193f8558
DQS Training:tsc[02]=000000001946b6a3
DQS Training:tsc[03]=000000003adf7190
DQS Training:tsc[04]=000000003c163939
Ram4
v_esp=000cee78
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Uncompressing image to RAM.
Jumping to image.
coreboot-2.0.0-r4253M Tue Jul 28 03:50:01 CST 2009 booting...
Enumerating buses...
Mainboard DBM690T Enable. dev=0x00025690
dbm690t_enable, TOP MEM: msr.lo = 0x40000000, msr.hi = 0x00000000
dbm690t_enable, TOP MEM2: msr2.lo = 0x00000000, msr2.hi = 0x00000000
dbm690t_enable: uma size 0x08000000, memory start 0x38000000
enable_onboard_nic.
Init adt7461 end , status 0x02 00
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 enabled
PCI: 00:18.3 siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1100] enabled
PCI: 00:18.1 [1022/1101] enabled
PCI: 00:18.2 [1022/1102] enabled
PCI: 00:18.3 [1022/1103] enabled
rs690_enable: dev=00027908, VID_DID=0x79101002
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x00027908, dev=0x00029b68, port=0x8
PCI: 00:00.0 [1002/7910] enabled
PCI: 00:00.0 [1002/7910] enabled next_unitid: 0015
PCI: pci_scan_bus for bus 00
rs690_enable: dev=00027908, VID_DID=0x79101002
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
gpp_sb_init nb_dev=0x00027908, dev=0x00029b68, port=0x8
PCI: 00:00.0 [1002/7910] enabled
rs690_enable: dev=00027d54, VID_DID=0x79121002
Bus-0, Dev-1, Fun-0.
PCI: 00:01.0 [1002/7912] enabled
rs690_enable: dev=000281a0, VID_DID=0x79131002
Bus-0, Dev-2,3, Fun-0. enable=1
rs690_gfx_init, nb_dev=0x00027908, dev=0x000281a0, port=0x2.
rs690_gfx_init step0.
rs690_gfx_init step1.
rs690_gfx_init step2.
rs690_gfx_init step4.
rs690_gfx_init step8.1.
rs690_gfx_init step8.2.
rs690_gfx_init step8.3.
rs690_gfx_init step8.4.
rs690_gfx_init step8.5.
rs690_gfx_init step8.6.
rs690_gfx_init step8.8.
rs690_gfx_init step8.9.
rs690_gfx_init step8.10.
rs690_gfx_init step8.11.
rs690_gfx_init step8.12.
rs690_gfx_init step8.13.
rs690_gfx_init single_port_configuration.
PcieLinkTraining port=2:lc current state=2030400
rs690_gfx_init single_port_configuration step12.
rs690_gfx_init single_port_configuration step13.
rs690_gfx_init single_port_configuration step14.
Disabling static device: PCI: 00:02.0
rs690_enable: dev=000285ec, VID_DID=0xffffffff
Bus-0, Dev-2,3, Fun-0. enable=0
rs690_enable: dev=00028a38, VID_DID=0x79141002
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x00027908, dev=0x00028a38, port=0x4
PcieLinkTraining port=4:lc current state=4000102
PcieTrainPort port=0x4 result=0
PCI: 00:04.0 subbordinate bus PCI Express
PCI: 00:04.0 [1002/7914] enabled
rs690_enable: dev=00028e84, VID_DID=0x79151002
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x00027908, dev=0x00028e84, port=0x5
PcieLinkTraining port=5:lc current state=4000102
PcieTrainPort port=0x5 result=0
PCI: 00:05.0 subbordinate bus PCI Express
PCI: 00:05.0 [1002/7915] enabled
rs690_enable: dev=000292d0, VID_DID=0x79161002
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x00027908, dev=0x000292d0, port=0x6
PcieLinkTraining port=6:lc current state=4000102
PcieTrainPort port=0x6 result=0
PCI: 00:06.0 subbordinate bus PCI Express
PCI: 00:06.0 [1002/7916] enabled
rs690_enable: dev=0002971c, VID_DID=0x79171002
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x00027908, dev=0x0002971c, port=0x7
PcieLinkTraining port=7:lc current state=a0b0f10
addr=e0000004,bus=0,devfn=38
PcieTrainPort reg=0x0
PcieTrainPort port=0x7 result=1
PCI: 00:07.0 subbordinate bus PCI Express
PCI: 00:07.0 [1002/7917] enabled
rs690_enable: dev=00029b68, VID_DID=0x79181002
Bus-0, Dev-8, Fun-0. enable=0
disable_pcie_bar3()
sb600_enable()
PCI: 00:12.0 [1002/4380] enabled
sb600_enable()
PCI: 00:13.0 [1002/4387] enabled
sb600_enable()
PCI: 00:13.1 [1002/4388] enabled
sb600_enable()
PCI: 00:13.2 [1002/4389] enabled
sb600_enable()
PCI: 00:13.3 [1002/438a] enabled
sb600_enable()
PCI: 00:13.4 [1002/438b] enabled
sb600_enable()
PCI: 00:13.5 [1002/4386] enabled
sb600_enable()
PCI: 00:14.0 [1002/4385] enabled
sb600_enable()
PCI: 00:14.1 [1002/438c] enabled
sb600_enable()
PCI: 00:14.2 [1002/4383] enabled
sb600_enable()
PCI: 00:14.3 [1002/438d] enabled
sb600_enable()
PCI: 00:14.4 [1002/4384] enabled
sb600_enable()
PCI: 00:14.5 [1002/4382] enabled
sb600_enable()
PCI: 00:14.6 [1002/438e] enabled
PCI: pci_scan_bus for bus 01
rs690_internal_gfx_enable dev=0x00029fb8, nb_dev=0x00027908.
nb_dev, 0x8c=0x10002333
PCI: 01:05.0 [1002/791f] enabled
PCI: 01:05.2 [1002/7919] enabled
PCI: pci_scan_bus returning with max=001
PCI: pci_scan_bus for bus 02
PCI: pci_scan_bus returning with max=002
PCI: pci_scan_bus for bus 03
PCI: pci_scan_bus returning with max=003
PCI: pci_scan_bus for bus 04
PCI: pci_scan_bus returning with max=004
PCI: pci_scan_bus for bus 05
PCI: 05:00.0 [14e4/169d] enabled
PCI: pci_scan_bus returning with max=005
PCIe: tuning PCI: 05:00.0
smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:52 enabled
smbus: PCI: 00:14.0[0]->I2C: 01:53 enabled
PNP: 002e.0 disabled
PNP: 002e.1 enabled
PNP: 002e.2 disabled
PNP: 002e.3 disabled
PNP: 002e.4 disabled
PNP: 002e.5 enabled
PNP: 002e.6 enabled
PNP: 002e.7 disabled
PNP: 002e.8 disabled
PNP: 002e.9 disabled
PNP: 002e.a disabled
PCI: pci_scan_bus for bus 06
PCI: 06:05.0 [1106/3038] enabled
PCI: 06:05.1 [1106/3038] enabled
PCI: 06:05.2 [1106/3104] enabled
PCI: pci_scan_bus returning with max=006
PCI: pci_scan_bus returning with max=006
PCI: pci_scan_bus returning with max=006
done
Allocating resources...
Reading resources...
PCI: 00:00.0 register 1c(e0000004), read-only ignoring it
rs690_gfx_read_resources.
PCI: 00:04.0 1c <- [0x0001fff000 - 0x0001ffefff] size 0x00000000 gran 0x0c bus 02 io
PCI: 00:04.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 02 prefmem
PCI: 00:04.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 02 mem
PCI: 00:05.0 1c <- [0x0001fff000 - 0x0001ffefff] size 0x00000000 gran 0x0c bus 03 io
PCI: 00:05.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 03 prefmem
PCI: 00:05.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 03 mem
PCI: 00:06.0 1c <- [0x0001fff000 - 0x0001ffefff] size 0x00000000 gran 0x0c bus 04 io
PCI: 00:06.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 00:06.0 20 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 04 mem
PCI: 00:07.0 1c <- [0x0001fff000 - 0x0001ffefff] size 0x00000000 gran 0x0c bus 05 io
PCI: 00:07.0 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 05 prefmem
PCI: 00:14.4 24 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x14 bus 06 prefmem
Done reading resources.
Allocating VGA resource PCI: 01:05.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Setting resources...
0: mmio_basek=003c0000, basek=00000300, limitk=00100000
VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device
PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io <node 0 link 0>
PCI: 00:18.0 1b8 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 prefmem <node 0 link 0>
PCI: 00:18.0 1b0 <- [0x00fc000000 - 0x00fc4fffff] size 0x00500000 gran 0x14 mem <node 0 link 0>
PCI: 00:01.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
PCI: 00:01.0 24 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x14 bus 01 prefmem
PCI: 00:01.0 20 <- [0x00fc000000 - 0x00fc1fffff] size 0x00200000 gran 0x14 bus 01 mem
PCI: 01:05.0 10 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem64
PCI: 01:05.0 18 <- [0x00fc100000 - 0x00fc10ffff] size 0x00010000 gran 0x10 mem64
PCI: 01:05.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
PCI: 01:05.0 24 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 mem
PCI: 01:05.0 30 <- [0x00fff00000 - 0x00ffefffff] size 0x00000000 gran 0x00 romem
PCI: 01:05.2 10 <- [0x00fc110000 - 0x00fc113fff] size 0x00004000 gran 0x0e mem64
PCI: 00:07.0 20 <- [0x00fc200000 - 0x00fc2fffff] size 0x00100000 gran 0x14 bus 05 mem
PCI: 05:00.0 10 <- [0x00fc200000 - 0x00fc20ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:12.0 10 <- [0x0000003020 - 0x0000003027] size 0x00000008 gran 0x03 io
PCI: 00:12.0 14 <- [0x0000003060 - 0x0000003063] size 0x00000004 gran 0x02 io
PCI: 00:12.0 18 <- [0x0000003030 - 0x0000003037] size 0x00000008 gran 0x03 io
PCI: 00:12.0 1c <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io
PCI: 00:12.0 20 <- [0x0000003000 - 0x000000300f] size 0x00000010 gran 0x04 io
PCI: 00:12.0 24 <- [0x00fc409000 - 0x00fc4093ff] size 0x00000400 gran 0x0a mem
PCI: 00:13.0 10 <- [0x00fc404000 - 0x00fc404fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.1 10 <- [0x00fc405000 - 0x00fc405fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.2 10 <- [0x00fc406000 - 0x00fc406fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.3 10 <- [0x00fc407000 - 0x00fc407fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.4 10 <- [0x00fc408000 - 0x00fc408fff] size 0x00001000 gran 0x0c mem
PCI: 00:13.5 10 <- [0x00fc40a000 - 0x00fc40a0ff] size 0x00000100 gran 0x08 mem
ERROR: PCI: 00:14.0 74 mem size: 0x0000001000 not assigned
ERROR: PCI: 00:14.0 14 mem size: 0x0000000400 not assigned
ERROR: PCI: 00:14.0 10 io size: 0x0000000010 not assigned
PCI: 00:14.1 10 <- [0x0000003040 - 0x0000003047] size 0x00000008 gran 0x03 io
PCI: 00:14.1 14 <- [0x0000003080 - 0x0000003083] size 0x00000004 gran 0x02 io
PCI: 00:14.1 18 <- [0x0000003050 - 0x0000003057] size 0x00000008 gran 0x03 io
PCI: 00:14.1 1c <- [0x0000003090 - 0x0000003093] size 0x00000004 gran 0x02 io
PCI: 00:14.1 20 <- [0x0000003010 - 0x000000301f] size 0x00000010 gran 0x04 io
PCI: 00:14.2 10 <- [0x00fc400000 - 0x00fc403fff] size 0x00004000 gran 0x0e mem64
PCI: 00:14.3 a0 <- [0x00fc40d000 - 0x00fc40d01f] size 0x00000020 gran 0x05 mem
PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
PCI: 00:14.4 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 06 io
PCI: 00:14.4 20 <- [0x00fc300000 - 0x00fc3fffff] size 0x00100000 gran 0x14 bus 06 mem
PCI: 06:05.0 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
PCI: 06:05.1 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io
PCI: 06:05.2 10 <- [0x00fc300000 - 0x00fc3000ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.5 10 <- [0x00fc40b000 - 0x00fc40b0ff] size 0x00000100 gran 0x08 mem
PCI: 00:14.6 10 <- [0x00fc40c000 - 0x00fc40c0ff] size 0x00000100 gran 0x08 mem
PCI: 00:18.3 94 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a mem <gart>
Done setting resources.
Done allocating resources.
Enabling resources...
PCI: 00:18.0 cmd <- 00
PCI: 00:00.0 subsystem <- 1022/3050
PCI: 00:00.0 cmd <- 06
PCI: 00:01.0 bridge ctrl <- 000b
PCI: 00:01.0 cmd <- 07
PCI: 01:05.0 subsystem <- 1022/3050
PCI: 01:05.0 cmd <- 03
PCI: 01:05.2 cmd <- 02
PCI: 00:04.0 bridge ctrl <- 0003
PCI: 00:04.0 cmd <- 00
PCI: 00:05.0 bridge ctrl <- 0003
PCI: 00:05.0 cmd <- 00
PCI: 00:06.0 bridge ctrl <- 0003
PCI: 00:06.0 cmd <- 00
PCI: 00:07.0 bridge ctrl <- 0003
PCI: 00:07.0 cmd <- 06
PCI: 05:00.0 cmd <- 02
PCI: 00:12.0 cmd <- 03
PCI: 00:13.0 subsystem <- 1022/3050
PCI: 00:13.0 cmd <- 02
PCI: 00:13.1 subsystem <- 1022/3050
PCI: 00:13.1 cmd <- 02
PCI: 00:13.2 subsystem <- 1022/3050
PCI: 00:13.2 cmd <- 02
PCI: 00:13.3 subsystem <- 1022/3050
PCI: 00:13.3 cmd <- 02
PCI: 00:13.4 subsystem <- 1022/3050
PCI: 00:13.4 cmd <- 02
PCI: 00:13.5 subsystem <- 1022/3050
PCI: 00:13.5 cmd <- 02
PCI: 00:14.0 subsystem <- 1022/3050
PCI: 00:14.0 cmd <- 403
PCI: 00:14.1 subsystem <- 1022/3050
PCI: 00:14.1 cmd <- 01
PCI: 00:14.2 subsystem <- 1022/3050
PCI: 00:14.2 cmd <- 02
PCI: 00:14.3 subsystem <- 1022/3050
PCI: 00:14.3 cmd <- 0f
sb600 lpc decode:PNP: 002e.1, base=0x000003f8, end=0x000003ff
sb600 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060
sb600 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064
PCI: 00:14.4 bridge ctrl <- 0003
PCI: 00:14.4 cmd <- 07
PCI: 06:05.0 cmd <- 01
PCI: 06:05.1 cmd <- 01
PCI: 06:05.2 cmd <- 02
PCI: 00:14.5 subsystem <- 1022/3050
PCI: 00:14.5 cmd <- 02
PCI: 00:14.6 subsystem <- 1022/3050
PCI: 00:14.6 cmd <- 02
PCI: 00:18.1 subsystem <- 1022/3050
PCI: 00:18.1 cmd <- 00
PCI: 00:18.2 subsystem <- 1022/3050
PCI: 00:18.2 cmd <- 00
PCI: 00:18.3 cmd <- 00
done.
Initializing devices...
Root Device init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor AMD device 60f82
CPU: family 0f, model 68, stepping 02
Enabling cache
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB
Setting variable MTRR 1, base: 1024MB, range: 128MB, type WB
Setting variable MTRR 2, base: 896MB, range: 128MB, type UC
DONE variable MTRRs
Clear out the extra MTRR's
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
CPU model AMD Turion(tm) 64 X2 Mobile Technology TL-62
Setting up local apic... apic_id: 0x00 done.
ECC Disabled
CPU #0 initialized
Initializing CPU #1
Waiting for 1 CPUS to stop
CPU: vendor AMD device 60f82
CPU: family 0f, model 68, stepping 02
Enabling cache
Setting fixed MTRRs(0-88) type: UC
Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM
Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM
DONE fixed MTRRs
Setting variable MTRR 0, base: 0MB, range: 1024MB, type WB
Setting variable MTRR 1, base: 1024MB, range: 128MB, type WB
Setting variable MTRR 2, base: 896MB, range: 128MB, type UC
DONE variable MTRRs
Clear out the extra MTRR's
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
CPU model AMD Turion(tm) 64 X2 Mobile Technology TL-62
Setting up local apic... apic_id: 0x01 done.
CPU #1 initialized
All AP CPUs stopped
PCI: 00:18.0 init
PCI: 00:00.0 init
pcie_init in rs690_ht.c
PCI: 01:05.0 init
internal_gfx_pci_dev_init device=791f, vendor=1002, vga_rom_address=0xfff00000.
On mainboard, rom address for PCI: 01:05.0 = fff00000
Device or Vendor ID mismatch Vendor 1002, Device 4387
PCI: 00:12.0 init
No Primary Master SATA drive on Slot0
No Primary Slave SATA drive on Slot1
No Secondary Master SATA drive on Slot2
No Secondary Slave SATA drive on Slot3
PCI: 00:13.0 init
PCI: 00:13.1 init
PCI: 00:13.2 init
PCI: 00:13.3 init
PCI: 00:13.4 init
PCI: 00:13.5 init
usb2_bar0=fc40a000
PCI: 00:14.0 init
sm_init().
lapicid = 0000000000000000
set power on after power fail
++++++++++no set NMI+++++
RTC Init
3.11, ABCFG:0x54
3.12, ABCFG:0x54
sm_init() end
PCI: 00:14.1 init
On mainboard, rom address for PCI: 00:14.1 = 0
PCI: 00:14.2 init
base = fc400000
codec_mask = 04
codec viddid: 10ec0882
Dev=PCI: 00:14.2
Default viddid=10ec0882
Reading viddid=10ec0882
verb_size: 48
verb loaded!
PCI: 00:14.3 init
PNP: 002e.1 init
PNP: 002e.5 init
Keyboard init...
Keyboard selftest failed ACK: 0xfe
PNP: 002e.6 init
PCI: 00:14.4 init
PCI: 00:18.1 init
On mainboard, rom address for PCI: 00:18.1 = 0
PCI: 00:18.2 init
On mainboard, rom address for PCI: 00:18.2 = 0
PCI: 00:18.3 init
NB: Function 3 Misc Control.. done.
PCI: 01:05.2 init
On card, rom address for PCI: 01:05.2 = 0
PCI: 05:00.0 init
On card, rom address for PCI: 05:00.0 = 0
PCI: 06:05.0 init
On card, rom address for PCI: 06:05.0 = 0
PCI: 06:05.1 init
On card, rom address for PCI: 06:05.1 = 0
PCI: 06:05.2 init
On card, rom address for PCI: 06:05.2 = 0
Devices initialized
High Tables Base is 3fff0000.
Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
Writing IRQ routing tables to 0x3fff0000...write_pirq_routing_table done.
ACPI: Writing ACPI tables at 3fff0400...
ACPI: * HPET
ACPI: added table 1/9 Length now 40
ACPI: * MADT
ACPI: added table 2/9 Length now 44
ACPI: * SSDT
processor_brand=AMD Turion(tm) 64 X2 Mobile Technology TL-62
Pstates Algorithm ...
Pstate_freq[0] = 2100MHz Pstate_vid[0] = 19 Pstate_volt[0] = 1075mv Pstate_power[0] = 35
000mw
Pstate_freq[1] = 2000MHz Pstate_vid[1] = 20 Pstate_volt[1] = 1050mv Pstate_power[1] = 31
800mw
Pstate_freq[2] = 1800MHz Pstate_vid[2] = 21 Pstate_volt[2] = 1025mv Pstate_power[2] = 27
274mw
Pstate_freq[3] = 1600MHz Pstate_vid[3] = 22 Pstate_volt[3] = 1000mv Pstate_power[3] = 23
075mw
Pstate_freq[4] = 800MHz Pstate_vid[4] = 30 Pstate_volt[4] = 800mv Pstate_power[4] = 7384mw
ACPI: added table 3/9 Length now 48
ACPI: * FACS
ACPI: * DSDT
ACPI: * DSDT @ 3fff08ba Length 267c
ACPI: * FADT
pm_base: 0x0800
ACPI: added table 4/9 Length now 52
ACPI: done.
Wrote the mp table end at: 00000020 - 00000134
Wrote the mp table end at: 3fff3410 - 3fff3524
Moving GDT to 0x3fff3800...ok
Multiboot Information structure has been written.
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518 checksum 83df
New low_table_end: 0x00000500
Now going to write high coreboot table at 0x3fff3c00
rom_table_end = 0x3fff3c00
Adjust low_table_end from 0x00000500 to 0x00001000
Adjust rom_table_end from 0x3fff3c00 to 0x40000000
Adding high table area
uma_memory_base=0x38000000, uma_memory_size=0x8000000
Wrote coreboot table at: 3fff3c00 - 3fff3de4 checksum b52b
elfboot: Attempting to load payload.
rom_stream: 0xfffc0000 - 0xfffdffff
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
New segment addr 0xf0000 size 0x10000 offset 0x1000 filesize 0x10000
(cleaned up) New segment addr 0xf0000 size 0x10000 offset 0x1000 filesize 0x10000
Dropping non PT_LOAD segment
Loading Segment: addr: 0x00000000000f0000 memsz: 0x0000000000010000 filesz: 0x0000000000010000
Jumping to boot code at 000fc275
Start bios
init ivt
init bda
init pic
init timer
tsc calibrate start=3490835980 end=3494443139 diff=3607159
CPU Mhz=2101
math cp init
bios_table_addr: 0x000fd500 end=0x000fdd00
Find memory size
Attempting to find coreboot table
Found coreboot table forwarder.
Now attempting to find coreboot memory map
init SMBIOS tables
SMBIOS table addr=0x000fd500
Ram Size=0x38000000
Found 2 cpu(s)
init PNPBIOS table
Scan for VGA option rom
Attempting to init PCI bdf 01:05.0 (dev/ven 791f1002)
Copying option rom (size 55808) from 0xfff1fe00 to c0000
Checking rom 0x000c0000 (sig aa55 size 109)
Running option rom at c000:0003
fail handle_15XX:314(86):
a=01284e08 b=00000080 c=00000000 d=0000c000 ds=c000 es=f000 ss=0000
si=0000abac di=0000b24c bp=00000000 sp=00007a6a cs=c000 ip=2ca6 f=0046
fail handle_15XX:314(86):
a=07ff4e08 b=00000005 c=00004e17 d=0000c002 ds=c000 es=f000 ss=0000
si=00002d3c di=0000b24c bp=00007a4e sp=00007a6a cs=c000 ip=2c43 f=0046
fail handle_15XX:314(86):
a=00004e08 b=00000000 c=0000a401 d=00000080 ds=c000 es=f000 ss=0000
si=0000abac di=0000b24c bp=00007a4e sp=00007a68 cs=c000 ip=2bfd f=0046
Turning on vga console
Starting SeaBIOS
init keyboard
i8042 ctr old=0 new=20
Got ps2 nak (status=51); continuing
ps2_recvbyte timeout
keyboard command 2ff failed
init lpt
Found 0 lpt ports
init serial
Found 1 serial ports
init mouse
e820 map has 5 items:
0: 0000000000000000 - 000000000009fc00 = 1
1: 000000000009fc00 - 00000000000a0000 = 2
2: 00000000000f0000 - 0000000000100000 = 2
3: 0000000000100000 - 0000000038000000 = 1
4: 0000000038000000 - 0000000040000000 = 2
final bios_table_addr: 0x000fd5e3 (used 11%)
init boot device ordering
init floppy drives
init hard drives
ATA controller 0 at 3020/3060 (dev 90 prog_if 8f)
ATA controller 1 at 3030/3070 (dev 90 prog_if 8f)
ATA controller 2 at 1f0/3f0 (dev a1 prog_if 8a)
ATA controller 3 at 170/370 (dev a1 prog_if 8a)
powerup iobase=3020 st=7f
powerup iobase=3020 st=7f
ata_detect drive=0 sc=7f sn=7f dh=7f
powerup iobase=3020 st=7f
powerup iobase=3020 st=7f
ata_detect drive=1 sc=7f sn=7f dh=7f
powerup iobase=3030 st=7f
powerup iobase=3030 st=7f
ata_detect drive=2 sc=7f sn=7f dh=7f
powerup iobase=3030 st=7f
powerup iobase=3030 st=7f
ata_detect drive=3 sc=7f sn=7f dh=7f
powerup IDE floating
powerup IDE floating
ata_detect drive=4 sc=ff sn=ff dh=ff
powerup IDE floating
powerup IDE floating
ata_detect drive=5 sc=ff sn=ff dh=ff
powerup IDE floating
powerup IDE floating
ata_detect drive=6 sc=ff sn=ff dh=ff
powerup IDE floating
powerup IDE floating
ata_detect drive=7 sc=ff sn=ff dh=ff
Scan for option roms
Attempting to init PCI bdf 00:00.0 (dev/ven 79101002)
Attempting to map option rom on dev 00:00.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:01.0 (dev/ven 79121002)
Attempting to map option rom on dev 00:01.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:04.0 (dev/ven 79141002)
Attempting to map option rom on dev 00:04.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:05.0 (dev/ven 79151002)
Attempting to map option rom on dev 00:05.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:06.0 (dev/ven 79161002)
Attempting to map option rom on dev 00:06.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:07.0 (dev/ven 79171002)
Attempting to map option rom on dev 00:07.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:13.0 (dev/ven 43871002)
Attempting to map option rom on dev 00:13.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:13.1 (dev/ven 43881002)
Attempting to map option rom on dev 00:13.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:13.2 (dev/ven 43891002)
Attempting to map option rom on dev 00:13.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:13.3 (dev/ven 438a1002)
Attempting to map option rom on dev 00:13.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:13.4 (dev/ven 438b1002)
Attempting to map option rom on dev 00:13.4
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:13.5 (dev/ven 43861002)
Attempting to map option rom on dev 00:13.5
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.0 (dev/ven 43851002)
Attempting to map option rom on dev 00:14.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.2 (dev/ven 43831002)
Attempting to map option rom on dev 00:14.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.3 (dev/ven 438d1002)
Attempting to map option rom on dev 00:14.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:14.4 (dev/ven 43841002)
Attempting to map option rom on dev 00:14.4
Skipping non-normal pci device (type=81)
Attempting to init PCI bdf 00:18.0 (dev/ven 11001022)
Attempting to map option rom on dev 00:18.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.1 (dev/ven 11011022)
Attempting to map option rom on dev 00:18.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.2 (dev/ven 11021022)
Attempting to map option rom on dev 00:18.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:18.3 (dev/ven 11031022)
Attempting to map option rom on dev 00:18.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 01:05.2 (dev/ven 79191002)
Attempting to map option rom on dev 01:05.2
Option rom sizing returned 0 0
Attempting to init PCI bdf 05:00.0 (dev/ven 169d14e4)
Attempting to map option rom on dev 05:00.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 06:05.0 (dev/ven 30381106)
Copying option rom (size 130560) from 0xfff00000 to ce000
Checking rom 0x000ce000 (sig aa55 size 255)
Running option rom at ce00:0003
hello, initialize_usb
00:13.0 4387:1002.0 OHCI controller
Not supported.
00:13.1 4388:1002.1 OHCI controller
Not supported.
00:13.2 4389:1002.2 OHCI controller
Not supported.
00:13.3 438a:1002.3 OHCI controller
Not supported.
00:13.4 438b:1002.4 OHCI controller
Not supported.
00:13.5 4386:1002.5 EHCI controller
Not supported.
00:05.0 3038:1106.0 UHCI controller
alloc length=0x238, the ptr=0x0
alloc the memory begin:0x7860 end:0x57860, hstart:0x0
setup the memory size:0x4fffc,begin:0x7860 end:0x57860, hstart:0xaa04fffc
set up failed,ptr=0x0
memory allocator panic!!! the size=0x0. header=0x0
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