[coreboot] [v2] r4233 - in trunk/coreboot-v2/src: arch/i386/init arch/i386/lib boot console cpu/amd/car cpu/intel/model_6ex cpu/intel/model_6fx cpu/x86/car lib mainboard/amd/dbm690t mainboard/amd/pistachio mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah_fam10 mainboard/arima/hdama mainboard/asus/a8n_e mainboard/asus/a8v-e_se mainboard/asus/m2v-mx_se mainboard/broadcom/blast mainboard/gigabyte/ga_2761gxdk mainboard/gigabyte/m57sli mainboard/hp/dl145_g3 mainboard/ibm/e325 mainboard/ibm/e326 mainboard/iwill/dk8_htx mainboard/iwill/dk8s2 mainboard/iwill/dk8x mainboard/kontron/986lcd-m mainboard/msi/ms7135 mainboard/msi/ms7260 mainboard/msi/ms9185 mainboard/msi/ms9282 mainboard/newisys/khepri mainboard/nvidia/l1_2pvv mainboard/sunw/ultra40 mainboard/supermicro/h8dme mainboard/supermicro/h8dmr mainboard/technexion/tim8690 mainboard/tyan/s2735 mainboard/tyan/s2850 mainboard/tyan/s2875 mainboard/tyan/s2880 mainboard/tyan/s2881 mainboard/tyan/s2882 mainboard/tyan/s2885 mainboard/tyan/s2891 mainboard/tyan/s2892 mainboard/tyan/s2895 mainboard/tyan/s2912 mainboard/tyan/s2912_fam10 mainboard/tyan/s4880 mainboard/tyan/s4882 mainboard/via/vt8454c northbridge/intel/i945 pc80 stream
svn at coreboot.org
svn at coreboot.org
Thu Apr 30 09:07:22 CEST 2009
Author: oxygene
Date: 2009-04-30 09:07:22 +0200 (Thu, 30 Apr 2009)
New Revision: 4233
Modified:
trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb
trunk/coreboot-v2/src/arch/i386/init/ldscript.lb
trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb
trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb
trunk/coreboot-v2/src/arch/i386/lib/Config.lb
trunk/coreboot-v2/src/arch/i386/lib/console.c
trunk/coreboot-v2/src/boot/Config.lb
trunk/coreboot-v2/src/boot/hardwaremain.c
trunk/coreboot-v2/src/console/Config.lb
trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c
trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c
trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c
trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c
trunk/coreboot-v2/src/lib/Config.lb
trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c
trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c
trunk/coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/msi/ms9282/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/newisys/khepri/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/supermicro/h8dme/apc_auto.c
trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/apc_auto.c
trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s2885/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/tyan/s4882/cache_as_ram_auto.c
trunk/coreboot-v2/src/mainboard/via/vt8454c/auto.c
trunk/coreboot-v2/src/northbridge/intel/i945/raminit.c
trunk/coreboot-v2/src/pc80/serial.c
trunk/coreboot-v2/src/stream/Config.lb
Log:
Refactor copy_and_run so that it uses a single code base instead of
3 (with one of them way too much assembler code).
On the way, I had to make some changes to the way the code is built,
which is an effort I want to expand over time.
Right now, large portions of the in-ROM part of coreboot is compiled as
a single file, with lots of .c files including other .c files.
That has its justification for pre-raminit code, but it also affects
lots of post-raminit code (memcpy doesn't really make sense before
raminit, or at least CAR)
The coreboot_apc code (AMD boards) gained some .c includes because I
don't know that part of the code enough to really rework it and only
have limited possibilities to test it. The includes should give an
identical situation for this part of the code.
This change was posted as set of 6 patches to the list, but they
were mostly split for review purposes, hence commit them all at once.
They can still be backed up using the patch files, if necessary.
Signed-off-by: Patrick Georgi <patrick.georgi at coresystems.de>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Modified: trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb 2009-04-30 07:07:22 UTC (rev 4233)
@@ -69,107 +69,19 @@
* the location it is compiled to run at.
* Normally this is copying from FLASH ROM to RAM.
*/
-#if !CONFIG_COMPRESS
+ movl %ebp, %esi
+ movl $0x4000000, %esp
+ movl %esp, %ebp
+ pushl %esi
movl $_liseg, %esi
movl $_iseg, %edi
movl $_eiseg, %ecx
subl %edi, %ecx
- movb %cl, %al
- shrl $2, %ecx
- andb $3, %al
- rep movsl
- movb %al, %cl
- rep movsb
-#else
- leal 4+_liseg, %esi
- leal _iseg, %edi
- movl %ebp, %esp /* preserve %ebp */
- movl $-1, %ebp /* last_m_off = -1 */
- jmp dcl1_n2b
+ pushl %ecx
+ pushl %edi
+ pushl %esi
+ call copy_and_run_core
-/* ------------- DECOMPRESSION -------------
-
- Input:
- %esi - source
- %edi - dest
- %ebp - -1
- cld
-
- Output:
- %eax - 0
- %ecx - 0
-*/
-
-.macro getbit bits
-.if \bits == 1
- addl %ebx, %ebx
- jnz 1f
-.endif
- movl (%esi), %ebx
- subl $-4, %esi /* sets carry flag */
- adcl %ebx, %ebx
-1:
-.endm
-
-decompr_literals_n2b:
- movsb
-
-decompr_loop_n2b:
- addl %ebx, %ebx
- jnz dcl2_n2b
-dcl1_n2b:
- getbit 32
-dcl2_n2b:
- jc decompr_literals_n2b
- xorl %eax, %eax
- incl %eax /* m_off = 1 */
-loop1_n2b:
- getbit 1
- adcl %eax, %eax /* m_off = m_off*2 + getbit() */
- getbit 1
- jnc loop1_n2b /* while(!getbit()) */
- xorl %ecx, %ecx
- subl $3, %eax
- jb decompr_ebpeax_n2b /* if (m_off == 2) goto decompr_ebpeax_n2b ? */
- shll $8, %eax
- movb (%esi), %al /* m_off = (m_off - 3)*256 + src[ilen++] */
- incl %esi
- xorl $-1, %eax
- jz decompr_end_n2b /* if (m_off == 0xffffffff) goto decomp_end_n2b */
- movl %eax, %ebp /* last_m_off = m_off ?*/
-decompr_ebpeax_n2b:
- getbit 1
- adcl %ecx, %ecx /* m_len = getbit() */
- getbit 1
- adcl %ecx, %ecx /* m_len = m_len*2 + getbit()) */
- jnz decompr_got_mlen_n2b /* if (m_len == 0) goto decompr_got_mlen_n2b */
- incl %ecx /* m_len++ */
-loop2_n2b:
- getbit 1
- adcl %ecx, %ecx /* m_len = m_len*2 + getbit() */
- getbit 1
- jnc loop2_n2b /* while(!getbit()) */
- incl %ecx
- incl %ecx /* m_len += 2 */
-decompr_got_mlen_n2b:
- cmpl $-0xd00, %ebp
- adcl $1, %ecx /* m_len = m_len + 1 + (last_m_off > 0xd00) */
- movl %esi, %edx
- leal (%edi,%ebp), %esi /* m_pos = dst + olen + -m_off */
- rep
- movsb /* dst[olen++] = *m_pos++ while(m_len > 0) */
- movl %edx, %esi
- jmp decompr_loop_n2b
-decompr_end_n2b:
- intel_chip_post_macro(0x12) /* post 12 */
-
- movl %esp, %ebp
-#endif
-
- CONSOLE_DEBUG_TX_STRING($str_pre_main)
- leal _iseg, %edi
- jmp *%edi
-
.Lhlt:
intel_chip_post_macro(0xee) /* post fe */
hlt
Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript.lb 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript.lb 2009-04-30 07:07:22 UTC (rev 4233)
@@ -48,6 +48,7 @@
_rom = .;
*(.rom.text);
*(.rom.data);
+ *(.rodata.*);
*(.rom.data.*);
. = ALIGN(16);
_erom = .;
Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript_failover.lb 2009-04-30 07:07:22 UTC (rev 4233)
@@ -42,6 +42,7 @@
*(.rom.text);
*(.rom.data);
*(.rom.data.*);
+ *(.rodata.*);
. = ALIGN(16);
_erom = .;
}
Modified: trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/arch/i386/init/ldscript_fallback.lb 2009-04-30 07:07:22 UTC (rev 4233)
@@ -52,6 +52,8 @@
_rom = .;
*(.rom.text);
*(.rom.data);
+ *(.init.rodata.*);
+ *(.rodata.*);
*(.rom.data.*);
. = ALIGN(16);
_erom = .;
Modified: trunk/coreboot-v2/src/arch/i386/lib/Config.lb
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/Config.lb 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/arch/i386/lib/Config.lb 2009-04-30 07:07:22 UTC (rev 4233)
@@ -1,5 +1,6 @@
uses CONFIG_USE_INIT
uses CONFIG_USE_PRINTK_IN_CAR
+uses USE_FAILOVER_IMAGE
object c_start.S
object cpu.c
@@ -9,9 +10,9 @@
object pci_ops_auto.c
object exception.c
-if CONFIG_USE_INIT
- if CONFIG_USE_PRINTK_IN_CAR
- initobject printk_init.o
- end
+initobject printk_init.o
+
+if USE_FAILOVER_IMAGE
+else
+ initobject copy_and_run.o
end
-
Modified: trunk/coreboot-v2/src/arch/i386/lib/console.c
===================================================================
--- trunk/coreboot-v2/src/arch/i386/lib/console.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/arch/i386/lib/console.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -13,12 +13,6 @@
#include "console_printk.c"
-#if CONFIG_USE_INIT == 0
-// do_printk
-#include "../../../console/vtxprintf.c"
-#include "printk_init.c"
-#endif
-
#endif /* CONFIG_USE_PRINTK_IN_CAR */
#ifndef COREBOOT_EXTRA_VERSION
Modified: trunk/coreboot-v2/src/boot/Config.lb
===================================================================
--- trunk/coreboot-v2/src/boot/Config.lb 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/boot/Config.lb 2009-04-30 07:07:22 UTC (rev 4233)
@@ -1,7 +1,8 @@
-object elfboot.o
object hardwaremain.o
if CONFIG_CBFS
object selfboot.o
+else
+ object elfboot.o
end
if CONFIG_FS_PAYLOAD
object filo.o
Modified: trunk/coreboot-v2/src/boot/hardwaremain.c
===================================================================
--- trunk/coreboot-v2/src/boot/hardwaremain.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/boot/hardwaremain.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -103,7 +103,7 @@
# else
void (*pl)(void) = cbfs_load_payload(lb_mem, "normal/payload");
# endif
-#endif
+#else
#if CONFIG_FS_PAYLOAD == 1
#warning "CONFIG_FS_PAYLOAD is deprecated."
@@ -112,6 +112,7 @@
#warning "elfboot will soon be deprecated."
elfboot(lb_mem);
#endif
+#endif
printk_err("Boot failed.\n");
}
Modified: trunk/coreboot-v2/src/console/Config.lb
===================================================================
--- trunk/coreboot-v2/src/console/Config.lb 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/console/Config.lb 2009-04-30 07:07:22 UTC (rev 4233)
@@ -28,8 +28,4 @@
object vtxprintf.o
object vsprintf.o
-if CONFIG_USE_INIT
-# if CONFIG_USE_PRINTK_IN_CAR
- initobject vtxprintf.o
-# end
-end
+initobject vtxprintf.o
Modified: trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/cpu/amd/car/copy_and_run.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -2,119 +2,36 @@
moved from nrv2v.c and some lines from crt0.S
2006/05/02 - stepan: move nrv2b to an extra file.
*/
-static inline void print_debug_cp_run(const char *strval, uint32_t val)
-{
-#if CONFIG_USE_PRINTK_IN_CAR
- printk_debug("%s%08x\r\n", strval, val);
-#else
- print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
-#endif
-}
-#if CONFIG_COMPRESS
-#define ENDIAN 0
-#define BITSIZE 32
-#include "lib/nrv2b.c"
-#endif
+void copy_and_run_core(u8 *src, u8 *dst, unsigned long ilen, unsigned ebp);
+extern u8 _liseg, _iseg, _eiseg;
static void copy_and_run(void)
{
uint8_t *src, *dst;
- unsigned long ilen, olen;
+ unsigned long ilen;
+ src = &_liseg;
+ dst = &_iseg;
+ ilen = &_eiseg - dst;
-#if !CONFIG_COMPRESS
- print_debug("Copying coreboot to RAM.\r\n");
- __asm__ volatile (
- "leal _liseg, %0\n\t"
- "leal _iseg, %1\n\t"
- "leal _eiseg, %2\n\t"
- "subl %1, %2\n\t"
- : "=a" (src), "=b" (dst), "=c" (olen)
- );
- memcpy(dst, src, olen);
-#else
- print_debug("Uncompressing coreboot to RAM.\r\n");
-
- __asm__ volatile (
- "leal _liseg, %0\n\t"
- "leal _iseg, %1\n\t"
- : "=a" (src) , "=b" (dst)
- );
-
- print_debug_cp_run("src=",(uint32_t)src);
- print_debug_cp_run("dst=",(uint32_t)dst);
-
-// dump_mem(src, src+0x100);
-
- olen = unrv2b(src, dst, &ilen);
- print_debug_cp_run("coreboot_ram.nrv2b length = ", ilen);
-
-#endif
-// dump_mem(dst, dst+0x100);
-
- print_debug_cp_run("coreboot_ram.bin length = ", olen);
-
- print_debug("Jumping to coreboot.\r\n");
-
- __asm__ volatile (
- "xorl %ebp, %ebp\n\t" /* cpu_reset for hardwaremain dummy */
- "cli\n\t"
- "leal _iseg, %edi\n\t"
- "jmp *%edi\n\t"
- );
-
+ copy_and_run_core(src, dst, ilen, 0);
}
#if CONFIG_AP_CODE_IN_CAR == 1
+extern u8 _liseg_apc, _iseg_apc, _eiseg_apc;
+
static void copy_and_run_ap_code_in_car(unsigned ret_addr)
{
uint8_t *src, *dst;
- unsigned long ilen, olen;
+ unsigned long ilen;
-// print_debug("Copying coreboot AP code to CAR.\r\n");
+ src = &_liseg_apc;
+ dst = &_iseg_apc;
+ ilen = &_eiseg_apc - dst;
-#if !CONFIG_COMPRESS
- __asm__ volatile (
- "leal _liseg_apc, %0\n\t"
- "leal _iseg_apc, %1\n\t"
- "leal _eiseg_apc, %2\n\t"
- "subl %1, %2\n\t"
- : "=a" (src), "=b" (dst), "=c" (olen)
- );
- memcpy(dst, src, olen);
-#else
-
- __asm__ volatile (
- "leal _liseg_apc, %0\n\t"
- "leal _iseg_apc, %1\n\t"
- : "=a" (src) , "=b" (dst)
- );
-
-// print_debug_cp_run("src=",(uint32_t)src);
-// print_debug_cp_run("dst=",(uint32_t)dst);
-
-// dump_mem(src, src+0x100);
-
- olen = unrv2b(src, dst, &ilen);
-// print_debug_cp_run("coreboot_apc.nrv2b length = ", ilen);
-
-#endif
-// dump_mem(dst, dst+0x100);
-
-// print_debug_cp_run("coreboot_apc.bin length = ", olen);
-
-// print_debug("Jumping to coreboot AP code in CAR.\r\n");
-
- __asm__ volatile (
- "movl %0, %%ebp\n\t" /* cpu_reset for hardwaremain dummy */
- "cli\n\t"
- "leal _iseg_apc, %%edi\n\t"
- "jmp *%%edi\n\t"
- :: "a"(ret_addr)
- );
-
+ copy_and_run_core(src, dst, ilen, ret_addr);
}
#endif
Modified: trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/cpu/intel/model_6ex/cache_as_ram_disable.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -102,6 +102,11 @@
:"=a" (new_cpu_reset)
);
+#ifdef CONFIG_DEACTIVATE_CAR
+ print_debug("Deactivating CAR");
+#include CONFIG_DEACTIVATE_CAR_FILE
+ print_debug(" - Done.\r\n");
+#endif
/* Copy and execute coreboot_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
Modified: trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c
===================================================================
--- trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/cpu/intel/model_6fx/cache_as_ram_disable.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -102,6 +102,11 @@
:"=a" (new_cpu_reset)
);
+#ifdef CONFIG_DEACTIVATE_CAR
+ print_debug("Deactivating CAR");
+#include CONFIG_DEACTIVATE_CAR_FILE
+ print_debug(" - Done.\r\n");
+#endif
/* Copy and execute coreboot_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
Modified: trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c
===================================================================
--- trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/cpu/x86/car/copy_and_run.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -1,83 +1,23 @@
-/* by yhlu 6.2005
- moved from nrv2v.c and some lines from crt0.S
- 2006/05/02 - stepan: move nrv2b to an extra file.
+/* Copyright (C) 2009 coresystems GmbH
+ (Written by Patrick Georgi <patrick.georgi at coresystems.de> for coresystems GmbH
*/
-#if CONFIG_COMPRESS
-#define ENDIAN 0
-#define BITSIZE 32
-#include "lib/nrv2b.c"
-#endif
+void copy_and_run_core(u8 *src, u8 *dst, unsigned long ilen, unsigned ebp);
+extern u8 _liseg, _iseg, _eiseg;
+
static void copy_and_run(unsigned cpu_reset)
{
uint8_t *src, *dst;
-#if !CONFIG_COMPRESS
- unsigned long dst_len;
-#endif
- unsigned long ilen, olen;
+ unsigned long ilen;
-#if !CONFIG_COMPRESS
- print_debug("Copying coreboot to RAM.\r\n");
- __asm__ volatile (
- "leal _liseg, %0\n\t"
- "leal _iseg, %1\n\t"
- "leal _eiseg, %2\n\t"
- "subl %1, %2\n\t"
- : "=a" (src), "=b" (dst), "=c" (dst_len)
- );
- memcpy(src, dst, dst_len);
-#else
- print_debug("Uncompressing coreboot to RAM.\r\n");
+ src = &_liseg;
+ dst = &_iseg;
+ ilen = &_eiseg - dst;
- __asm__ volatile (
- "leal _liseg, %0\n\t"
- "leal _iseg, %1\n\t"
- : "=a" (src) , "=b" (dst)
- );
+ if (cpu_reset == 1) cpu_reset = -1;
+ else cpu_reset = 0;
-#if CONFIG_USE_INIT
- printk_spew("src=%08x\r\n",src);
- printk_spew("dst=%08x\r\n",dst);
-#else
- print_spew("src="); print_spew_hex32((uint32_t)src); print_spew("\r\n");
- print_spew("dst="); print_spew_hex32((uint32_t)dst); print_spew("\r\n");
-#endif
-
-// dump_mem(src, src+0x100);
-
- olen = unrv2b(src, dst, &ilen);
-
-#endif
-// dump_mem(dst, dst+0x100);
-#if CONFIG_USE_INIT
- printk_spew("coreboot_ram.bin length = %08x\r\n", olen);
-#else
- print_spew("coreboot_ram.bin length = "); print_spew_hex32(olen); print_spew("\r\n");
-#endif
-#ifdef CONFIG_DEACTIVATE_CAR
- print_debug("Deactivating CAR");
-#include CONFIG_DEACTIVATE_CAR_FILE
- print_debug(" - Done.\r\n");
-#endif
- print_debug("Jumping to coreboot.\r\n");
-
- if(cpu_reset == 1 ) {
- __asm__ volatile (
- "movl $0xffffffff, %ebp\n\t"
- );
- }
- else {
- __asm__ volatile (
- "xorl %ebp, %ebp\n\t"
- );
- }
-
- __asm__ volatile (
- "cli\n\t"
- "leal _iseg, %edi\n\t"
- "jmp *%edi\n\t"
- );
-
+ copy_and_run_core(src, dst, ilen, cpu_reset);
}
Modified: trunk/coreboot-v2/src/lib/Config.lb
===================================================================
--- trunk/coreboot-v2/src/lib/Config.lb 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/lib/Config.lb 2009-04-30 07:07:22 UTC (rev 4233)
@@ -21,12 +21,10 @@
# Force version.o to recompile every time
makedefine .PHONY : version.o
-if CONFIG_USE_INIT
- initobject uart8250.c
- initobject memset.o
- initobject memcpy.o
- initobject memcmp.o
-end
+initobject uart8250.c
+initobject memset.o
+initobject memcpy.o
+initobject memcmp.o
if CONFIG_CBFS
object cbfs.o
Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -37,6 +37,7 @@
#define SMBUS_HUB 0x71
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -54,10 +55,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -31,6 +31,7 @@
#define DIMM1 0x51
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -48,10 +49,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -21,12 +21,15 @@
#include "option_table.h"
#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
+#include "./arch/i386/lib/printk_init.c"
#if CONFIG_USE_INIT == 0
#include "lib/memcpy.c"
#endif
#include "arch/i386/lib/console.c"
+#include "lib/uart8250.c"
+#include "console/vtxprintf.c"
#if 0
static void post_code(uint8_t value) {
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -24,6 +24,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -63,9 +64,6 @@
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb 2009-04-30 07:07:22 UTC (rev 4233)
@@ -136,7 +136,7 @@
#FALLBACK: 512K - 4K
default FALLBACK_SIZE=0x7f000
#FAILOVER: 4k
-default FAILOVER_SIZE=0x01000
+default FAILOVER_SIZE=0x02000
#more 1M for pgtbl
#if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -45,6 +45,7 @@
#define FAM10_SET_FIDVID_CORE_RANGE 0
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -81,10 +82,6 @@
#if (USE_FAILOVER_IMAGE == 0)
- #if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
- #endif
-
#include "northbridge/amd/amdfam10/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -21,10 +21,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -38,6 +38,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -54,10 +55,6 @@
/* Used by ck894_early_setup(). */
#define CK804_NUM 1
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -43,6 +43,7 @@
/* #define DEBUG_SMBUS 1 */
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -56,9 +57,6 @@
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -47,6 +47,7 @@
/* #define DEBUG_SMBUS 1 */
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -61,9 +62,6 @@
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -11,6 +11,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -40,10 +41,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -48,6 +48,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -85,10 +86,6 @@
#include "cpu/x86/bist.h"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -46,6 +46,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -82,10 +83,6 @@
#include "cpu/x86/bist.h"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -51,6 +51,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -87,10 +88,6 @@
#include "cpu/x86/bist.h"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -21,10 +22,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -21,10 +22,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -24,6 +24,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -52,15 +53,6 @@
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
- // TODO: This doesn't compile at the moment. Fix later.
- // #if CONFIG_USE_PRINTK_IN_CAR == 1
- // #include "lib/uart8250.c"
- // #include "console/vtxprintf.c"
- // #include "arch/i386/lib/printk_init.c"
- // #endif
-#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -24,6 +24,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -52,15 +53,6 @@
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
- // TODO: This doesn't compile at the moment. Fix later.
- // #if CONFIG_USE_PRINTK_IN_CAR == 1
- // #include "lib/uart8250.c"
- // #include "console/vtxprintf.c"
- // #include "arch/i386/lib/printk_init.c"
- // #endif
-#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -24,6 +24,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -52,15 +53,6 @@
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
- // TODO: This doesn't compile at the moment. Fix later.
- // #if CONFIG_USE_PRINTK_IN_CAR == 1
- // #include "lib/uart8250.c"
- // #include "console/vtxprintf.c"
- // #include "arch/i386/lib/printk_init.c"
- // #endif
-#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
Modified: trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -23,6 +23,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_def.h>
@@ -45,10 +46,6 @@
#include "northbridge/intel/i945/udelay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
#include "northbridge/intel/i945/ich7.h"
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -38,6 +38,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -56,10 +57,6 @@
#define CK804_USE_NIC 1
#define CK804_USE_ACI 1
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -50,6 +50,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -84,9 +85,6 @@
#if USE_FAILOVER_IMAGE == 0
#include "cpu/x86/bist.h"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -47,6 +47,7 @@
#define DEBUG_SMBUS 1
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -75,11 +76,7 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9282/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9282/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9282/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -41,6 +41,7 @@
#define DEBUG_SMBUS 1
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -57,10 +58,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/newisys/khepri/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/newisys/khepri/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/newisys/khepri/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -7,6 +7,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -37,10 +38,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -46,6 +46,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -82,10 +83,6 @@
#include "cpu/x86/bist.h"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -14,6 +14,7 @@
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -32,10 +33,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/apc_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/apc_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/apc_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -48,6 +48,9 @@
#endif
#include "arch/i386/lib/console.c"
+#include "lib/uart8250.c"
+#include "console/vtxprintf.c"
+#include "./arch/i386/lib/printk_init.c"
#if 0
static void post_code(uint8_t value) {
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -40,6 +40,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -75,10 +76,6 @@
#include "cpu/x86/bist.h"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/apc_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/apc_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/apc_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -48,6 +48,9 @@
#endif
#include "arch/i386/lib/console.c"
+#include "lib/uart8250.c"
+#include "console/vtxprintf.c"
+#include "./arch/i386/lib/printk_init.c"
#if 0
static void post_code(uint8_t value) {
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -44,6 +44,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -79,10 +80,6 @@
#include "cpu/x86/bist.h"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -37,6 +37,7 @@
#define SMBUS_HUB 0x71
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -54,10 +55,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -27,10 +28,6 @@
#include "southbridge/intel/i82801er/i82801er_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/intel/e7501/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
@@ -259,6 +256,11 @@
print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
#endif
+#ifdef CONFIG_DEACTIVATE_CAR
+ print_debug("Deactivating CAR");
+#include CONFIG_DEACTIVATE_CAR_FILE
+ print_debug(" - Done.\r\n");
+#endif
/*copy and execute coreboot_ram */
copy_and_run(new_cpu_reset);
/* We will not return */
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -32,10 +33,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -21,10 +22,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -22,10 +23,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -8,6 +8,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -38,10 +39,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -21,10 +22,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2885/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2885/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2885/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -32,10 +33,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -9,6 +9,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -27,9 +28,6 @@
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -21,10 +22,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -12,6 +12,7 @@
#endif
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -47,10 +48,6 @@
#include "cpu/x86/bist.h"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -46,6 +46,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -82,10 +83,6 @@
#include "cpu/x86/bist.h"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -39,6 +39,7 @@
#define DBGP_DEFAULT 7
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
@@ -78,10 +79,6 @@
#include "cpu/x86/bist.h"
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
-#endif
-
#include "northbridge/amd/amdfam10/debug.c"
#include "cpu/amd/mtrr/amd_earlymtrr.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -21,10 +22,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/tyan/s4882/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s4882/cache_as_ram_auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/tyan/s4882/cache_as_ram_auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -2,6 +2,7 @@
#define __ROMCC__
#include <stdint.h>
+#include <string.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
@@ -20,10 +21,6 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-#if CONFIG_USE_INIT == 0
-#include "lib/memcpy.c"
-#endif
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
Modified: trunk/coreboot-v2/src/mainboard/via/vt8454c/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/vt8454c/auto.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/mainboard/via/vt8454c/auto.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -119,6 +119,12 @@
sdram_set_registers(cx700);
enable_shadow_ram(cx700);
sdram_enable(cx700);
+
+#ifdef CONFIG_DEACTIVATE_CAR
+ print_debug("Deactivating CAR");
+#include CONFIG_DEACTIVATE_CAR_FILE
+ print_debug(" - Done.\r\n");
+#endif
copy_and_run(0);
}
Modified: trunk/coreboot-v2/src/northbridge/intel/i945/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/intel/i945/raminit.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/northbridge/intel/i945/raminit.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -25,8 +25,6 @@
#include "raminit.h"
#include "i945.h"
-#include "lib/memset.c"
-
#define DEBUG_RAM_SETUP
/* Debugging macros. */
Modified: trunk/coreboot-v2/src/pc80/serial.c
===================================================================
--- trunk/coreboot-v2/src/pc80/serial.c 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/pc80/serial.c 2009-04-30 07:07:22 UTC (rev 4233)
@@ -94,9 +94,6 @@
#else
/* CONFIG_USE_PRINTK_IN_CAR == 1 */
-#if CONFIG_USE_INIT == 0
-#include "../lib/uart8250.c"
-#endif
extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
static void uart_init(void)
Modified: trunk/coreboot-v2/src/stream/Config.lb
===================================================================
--- trunk/coreboot-v2/src/stream/Config.lb 2009-04-29 20:34:41 UTC (rev 4232)
+++ trunk/coreboot-v2/src/stream/Config.lb 2009-04-30 07:07:22 UTC (rev 4233)
@@ -3,7 +3,10 @@
uses CONFIG_FS_PAYLOAD
uses CONFIG_IDE
uses CONFIG_SERIAL_PAYLOAD
+uses CONFIG_CBFS
+if CONFIG_CBFS
+else
if CONFIG_ROM_PAYLOAD
object rom_stream.o
end
@@ -21,3 +24,4 @@
if CONFIG_SERIAL_PAYLOAD
object serial_stream.o
end
+end
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