[coreboot] [v2] r4148 - trunk/coreboot-v2/src/config

svn at coreboot.org svn at coreboot.org
Tue Apr 21 02:25:23 CEST 2009


Author: hailfinger
Date: 2009-04-21 02:25:23 +0200 (Tue, 21 Apr 2009)
New Revision: 4148

Added:
   trunk/coreboot-v2/src/config/failovercalculation.lb
   trunk/coreboot-v2/src/config/nofailovercalculation.lb
Log:
Somehow svn add didn't work for the include files. Commit the remainder
of r4147.

Thanks to Myles' patch adding support for include statements,
refactoring Config.lb became possible.

Factor out ROM size calculation from Config.lb.
  
This patch converts 87 boards (with and without USE_FAILOVER_IMAGE),
but it has to work around a parser bug. 

89 files changed, 209 insertions(+), 2415 deletions(-)
A total of 2206 removed lines.
  
Abuild works for all changed boards on khepri.

Myles writes:
I've tested serengeti for the failover portion and s2892 for the
nofailover portion.  ldoptions are exactly the same and they both boot
the same.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Myles Watson <mylesgw at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>
Acked-by: Uwe Hermann <uwe at hermann-uwe.de>


Added: trunk/coreboot-v2/src/config/failovercalculation.lb
===================================================================
--- trunk/coreboot-v2/src/config/failovercalculation.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/config/failovercalculation.lb	2009-04-21 00:25:23 UTC (rev 4148)
@@ -0,0 +1,48 @@
+##
+## Compute the location and size of where this firmware image
+## (coreboot plus bootloader) will live in the boot rom chip.
+##
+if USE_FAILOVER_IMAGE
+	default ROM_SECTION_SIZE   = FAILOVER_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
+else
+    if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+    else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+	default ROM_SECTION_OFFSET = 0
+    end
+end
+
+##
+## Compute the start location and size size of
+## The coreboot bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of coreboot will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up coreboot,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE = 64 * 1024
+
+if USE_FAILOVER_IMAGE
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+else
+    if USE_FALLBACK_IMAGE
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
+    else
+	default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+    end
+end
+

Added: trunk/coreboot-v2/src/config/nofailovercalculation.lb
===================================================================
--- trunk/coreboot-v2/src/config/nofailovercalculation.lb	                        (rev 0)
+++ trunk/coreboot-v2/src/config/nofailovercalculation.lb	2009-04-21 00:25:23 UTC (rev 4148)
@@ -0,0 +1,38 @@
+##
+## Compute the location and size of where this firmware image
+## (coreboot plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The coreboot bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of coreboot will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up coreboot,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE = 64 * 1024
+default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE )
+
+## This is needed to work around a parser bug.
+if USE_FALLBACK_IMAGE
+end
+





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