[coreboot] Remaining ROMCC targets

[Joseph Smith]

On Mon, 20 Apr 2009 17:58:00 +0200, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> On 20.04.2009 17:39, Joseph Smith wrote:
>>> On Fri, Apr 3, 2009 at 8:03 PM, Joseph Smith <joe at settoplinux.org>
> wrote:
>>>
>>>
>>>>
>>>>> http://download.intel.com/design/PentiumIII/datashts/27367305.pdf
>>>>>
>>>>> It just says:
>>>>> • On-die primary (L1) instruction and data caches
>>>>>   — 4-way set associative, 32-byte line size, 1 line per sector
>>>>>   — 16-Kbyte instruction cache and 16-Kbyte write-back data cache
>>>>>   — Cacheable range controlled by processor programmable registers
>>>>> • On-die second level (L2) cache
>>>>>   — 8-way set associative, 32-byte line size, 1 line per sector
>>>>>   — Operates at full core speed
>>>>>   — 512-Kbyte ECC protected cache data array
>>>>>
>>>>>
>>>> Oh does that mean the L1 cache is 16K? That seems so small...
>>>>
>>>>
>>> 4k should be enough
>>>
>>>
>> Just curious, no pressure, have you made any progress on this yet
>> Carl-Daniel?
>>
> 
> The Config.lb cleanups were preparations for this step in v2 (where the
> majority of boards lives).
> 
Ok great :-)
>
> Sorry if you already wrote it somewhere, but which Super I/O do you
> have? I want to make sure it is supported in v3.
> 
SMSC LPC47M192

All the hardware is listed here:
http://www.settoplinux.org/index.php?title=Thomson_IP1000

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org