[coreboot] Timing via serial port

[Kevin O'Connor]

On Sat, Apr 18, 2009 at 09:40:56PM -0400, Kevin O'Connor wrote:
> On Sat, Apr 18, 2009 at 09:14:06PM -0400, Kevin O'Connor wrote:
> > On my epia-cn machine, it takes coreboot-v2 8.7 seconds to launch
> > SeaBIOS.  It looks like about 4 seconds is lost due to a reboot
> > half-way through the startup - I'm guessing a watchdog timer is
> > kicking in.  As to why it takes so long to boot - maybe rom caching is
> > off?
> 
> Nope - looks like calibrate_tsc is taking 2.9 seconds to calibrate:
> 
> 00.608: Jumping to coreboot.
> 00.609: coreboot-2.0.0-epiacn Sat Apr 18 21:34:47 EDT 2009 booting...
> 00.612: Calibrating delay loop...

If I add the following to Config.lb:

option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1

then the problem goes away - coreboot takes only 1.8 seconds.

The weird thing is that:

default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1

is already in the epia-cn Options.lb file.  Perhaps the 'default' line
in src/cpu/x86/tsc/Config.lb is overriding it?

-Kevin (dreams of Kconfig)