[coreboot] [v2] r4093 - in trunk/coreboot-v2/src/mainboard: amd/db800 amd/dbm690t amd/norwich amd/pistachio amd/serengeti_cheetah amd/serengeti_cheetah_fam10 artecgroup/dbe61 asus/a8n_e asus/a8v-e_se asus/m2v-mx_se broadcom/blast digitallogic/msm800sev gigabyte/ga_2761gxdk gigabyte/m57sli iei/pcisa-lx-800-r10 iwill/dk8_htx lippert/roadrunner-lx lippert/spacerunner-lx msi/ms7135 msi/ms7260 msi/ms9185 nvidia/l1_2pvv pcengines/alix1c supermicro/h8dme supermicro/h8dmr technexion/tim8690 tyan/s2912 tyan/s2912_fam10
svn at coreboot.org
svn at coreboot.org
Sat Apr 11 16:51:49 CEST 2009
Author: hailfinger
Date: 2009-04-11 16:51:49 +0200 (Sat, 11 Apr 2009)
New Revision: 4093
Modified:
trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb
trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb
trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb
trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb
trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb
trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb
trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb
trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb
trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb
trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb
trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb
trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb
trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb
trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb
trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb
trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb
trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb
trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb
trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb
trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb
trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb
trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb
trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb
trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb
trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb
Log:
Kill remaining unneeded CAR/ROMCC if-blocks.
Lots of Config.lb files still have "if USE_DCACHE_RAM" sections although
USE_DCACHE_RAM is always set for them. Such checks are not only
pointless, they actively make the files hard to read.
A full abuild run confirmed that compilation did not change with this
patch applied.
The patch does not change whitespace of the remaining code to ease
review and svn blame.
With this change, it should be possible to have two or three Config.lb
variants in total (except the actual hardware config). Right now, some
Config.lb have comments, some don't, some have empty lines for better
readability, some don't, some have leading whitespace, some don't. This
is an utter mess and unifying these files would certainly reduce the
headaches I have when looking at them.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Peter Stuge <peter at stuge.se>
Modified: trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/amd/db800/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -50,7 +50,6 @@
object irq_tables.o
end
-if USE_DCACHE_RAM
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -58,9 +57,7 @@
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -108,10 +105,8 @@
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
-if USE_DCACHE_RAM
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
mainboardinit ./cache_as_ram_auto.inc
-end
##
## Include the secondary Configuration files
Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -83,8 +83,6 @@
#object reset.o
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
@@ -103,14 +101,12 @@
end
-end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -118,7 +114,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -137,12 +132,10 @@
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -150,12 +143,7 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
- end
end
###
@@ -165,16 +153,12 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
-
##
## Include the secondary Configuration files
##
Modified: trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/amd/norwich/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -52,7 +52,6 @@
#object reset.o
-if USE_DCACHE_RAM
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -60,9 +59,7 @@
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -110,10 +107,8 @@
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
-if USE_DCACHE_RAM
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
mainboardinit ./cache_as_ram_auto.inc
-end
##
## Include the secondary Configuration files
Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -83,8 +83,6 @@
#object reset.o
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
@@ -103,14 +101,12 @@
end
-end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -118,7 +114,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -137,12 +132,10 @@
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -150,12 +143,7 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
- end
end
###
@@ -165,16 +153,12 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
-
##
## Include the secondary Configuration files
##
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -122,8 +122,6 @@
end
end
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
@@ -140,7 +138,6 @@
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-end
if USE_FAILOVER_IMAGE
else
@@ -170,7 +167,6 @@
end
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -178,7 +174,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -207,12 +202,10 @@
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -221,15 +214,11 @@
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
@@ -240,16 +229,12 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
-
##
## Include the secondary Configuration files
##
Modified: trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -129,7 +129,6 @@
end
end
-if USE_DCACHE_RAM
makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c
if CONFIG_USE_INIT
@@ -149,7 +148,6 @@
end
end
-end
if USE_FAILOVER_IMAGE
else
@@ -179,7 +177,6 @@
end
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -187,7 +184,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -217,12 +213,10 @@
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -231,15 +225,11 @@
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
@@ -250,16 +240,12 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
-
##
## Include the secondary Configuration files
##
Modified: trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -47,8 +47,6 @@
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-
-if USE_DCACHE_RAM
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -56,9 +54,7 @@
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -106,10 +102,8 @@
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
-if USE_DCACHE_RAM
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
mainboardinit ./cache_as_ram_auto.inc
-end
##
## Include the secondary Configuration files
Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -54,7 +54,6 @@
object get_bus_conf.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -68,7 +67,6 @@
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-end
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
@@ -81,12 +79,10 @@
end
end
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@@ -104,10 +100,6 @@
ldscript /cpu/x86/32bit/reset32.lds
end
end
-if USE_DCACHE_RAM
-else
- mainboardinit arch/i386/lib/cpu_reset.inc
-end
# Include an ID string (for safe flashing).
mainboardinit southbridge/nvidia/ck804/id.inc
ldscript /southbridge/nvidia/ck804/id.lds
@@ -123,29 +115,21 @@
ldscript /southbridge/nvidia/ck804/romstrap.lds
end
end
-if USE_DCACHE_RAM
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-end
config chip.h
chip northbridge/amd/amdk8/root_complex # Root complex
Modified: trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/asus/a8v-e_se/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -52,7 +52,6 @@
if HAVE_PIRQ_TABLE object irq_tables.o end
# object reset.o
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -66,7 +65,6 @@
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-end
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
@@ -77,14 +75,12 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@@ -94,23 +90,17 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
config chip.h
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -55,7 +55,6 @@
if HAVE_PIRQ_TABLE object irq_tables.o end
# object reset.o
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -69,7 +68,6 @@
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-end
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
@@ -80,14 +78,12 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
@@ -97,23 +93,17 @@
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
config chip.h
Modified: trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/broadcom/blast/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -50,8 +50,6 @@
#object reset.o
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
@@ -70,14 +68,12 @@
end
-end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -85,7 +81,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -104,12 +99,10 @@
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -117,12 +110,7 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
- end
end
###
@@ -132,16 +120,12 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
-
##
## Include the secondary Configuration files
##
Modified: trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/digitallogic/msm800sev/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -48,7 +48,6 @@
object irq_tables.o
end
-if USE_DCACHE_RAM
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -56,10 +55,7 @@
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
-end
-
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -107,10 +103,8 @@
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
-if USE_DCACHE_RAM
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
mainboardinit ./cache_as_ram_auto.inc
-end
##
## Include the secondary Configuration files
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -82,7 +82,6 @@
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
@@ -98,8 +97,6 @@
end
end
-end
-
if USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
@@ -129,7 +126,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -137,9 +133,7 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
-
##
## Build our reset vector (This is where coreboot is entered)
##
@@ -182,12 +176,10 @@
end
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -196,29 +188,22 @@
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
##
## Include the secondary Configuration files
Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -80,7 +80,6 @@
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
@@ -96,8 +95,6 @@
end
end
-end
-
if USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
@@ -127,7 +124,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -135,9 +131,7 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
-
##
## Build our reset vector (This is where coreboot is entered)
##
@@ -180,12 +174,10 @@
end
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -194,15 +186,11 @@
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
@@ -213,14 +201,11 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
##
## Include the secondary Configuration files
Modified: trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/iei/pcisa-lx-800-r10/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -35,7 +35,6 @@
if HAVE_PIRQ_TABLE
object irq_tables.o
end
-if USE_DCACHE_RAM
# Compile cache_as_ram.c to auto.inc.
makerule ./cache_as_ram_auto.inc
# depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -44,7 +43,6 @@
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
-end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
@@ -63,10 +61,8 @@
# mainboardinit ./failover.inc
end
mainboardinit cpu/x86/fpu/enable_fpu.inc
-if USE_DCACHE_RAM
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
mainboardinit ./cache_as_ram_auto.inc
-end
dir /pc80
config chip.h
Modified: trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/iwill/dk8_htx/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -129,8 +129,6 @@
end
end
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
@@ -148,7 +146,6 @@
end
end
-end
if USE_FAILOVER_IMAGE
else
@@ -178,7 +175,6 @@
end
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -186,7 +182,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -215,12 +210,10 @@
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -229,15 +222,11 @@
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
@@ -248,16 +237,12 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
-
##
## Include the secondary Configuration files
##
Modified: trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/lippert/roadrunner-lx/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -72,7 +72,6 @@
object irq_tables.o
end
-if USE_DCACHE_RAM
# compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c"
@@ -80,9 +79,7 @@
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
-end
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -130,10 +127,8 @@
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
-if USE_DCACHE_RAM
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
mainboardinit ./cache_as_ram_auto.inc
-end
##
## Include the secondary configuration files
Modified: trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/lippert/spacerunner-lx/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -70,7 +70,6 @@
object irq_tables.o
end
-if USE_DCACHE_RAM
# compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c"
@@ -78,7 +77,6 @@
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
-end
##
## Build our 16 bit and 32 bit coreboot entry code
@@ -127,10 +125,8 @@
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
-if USE_DCACHE_RAM
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
mainboardinit ./cache_as_ram_auto.inc
-end
##
## Include the secondary configuration files
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7135/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -90,7 +90,6 @@
object irq_tables.o
end
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -104,7 +103,6 @@
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-end
##
## Build our 16 bit and 32 bit coreboot entry code.
@@ -123,12 +121,10 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (this is where coreboot is entered).
@@ -151,12 +147,6 @@
end
end
-if USE_DCACHE_RAM
-else
- ### Should this be in the northbridge code?
- mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an ID string (for safe flashing).
##
@@ -178,14 +168,11 @@
end
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
-
###
### This is the early phase of coreboot startup.
### Things are delicate and we test to see if we should
@@ -193,15 +180,11 @@
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
@@ -212,13 +195,11 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-end
##
## Include the secondary configuration files
Modified: trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/msi/ms7260/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -54,7 +54,6 @@
if HAVE_PIRQ_TABLE object irq_tables.o end
# object reset.o
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -68,7 +67,6 @@
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
end
-end
if USE_FAILOVER_IMAGE
else
@@ -95,14 +93,12 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
@@ -138,31 +134,23 @@
end
end
-if USE_DCACHE_RAM
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
config chip.h
Modified: trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/msi/ms9185/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -77,8 +77,6 @@
object irq_tables.o
end
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
# compile cache_as_ram.c to auto.o
makerule ./cache_as_ram_auto.o
@@ -96,7 +94,6 @@
end
end
-end
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -107,7 +104,6 @@
end
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -115,7 +111,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -134,12 +129,10 @@
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -147,9 +140,7 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
###
@@ -159,16 +150,12 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
-
##
## Include the secondary Configuration files
##
Modified: trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/nvidia/l1_2pvv/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -111,8 +111,6 @@
end
end
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -127,8 +125,6 @@
end
end
-end
-
if USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
@@ -158,7 +154,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -166,9 +161,7 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
-
##
## Build our reset vector (This is where coreboot is entered)
##
@@ -211,12 +204,10 @@
end
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -225,29 +216,22 @@
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
##
## Include the secondary Configuration files
Modified: trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/pcengines/alix1c/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -68,7 +68,6 @@
object irq_tables.o
end
-if USE_DCACHE_RAM
#compile cache_as_ram.c to auto.inc
makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -76,10 +75,7 @@
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
-end
-
-
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -127,10 +123,8 @@
##
mainboardinit cpu/x86/fpu/enable_fpu.inc
-if USE_DCACHE_RAM
mainboardinit cpu/amd/model_lx/cache_as_ram.inc
mainboardinit ./cache_as_ram_auto.inc
-end
##
## Include the secondary Configuration files
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dme/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -77,7 +77,6 @@
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
@@ -93,8 +92,6 @@
end
end
-end
-
if USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
@@ -124,7 +121,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -132,9 +128,7 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
-
##
## Build our reset vector (This is where coreboot is entered)
##
@@ -177,12 +171,10 @@
end
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -191,29 +183,22 @@
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-end
##
## Include the secondary Configuration files
Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -80,7 +80,6 @@
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
makerule ./auto.o
@@ -96,8 +95,6 @@
end
end
-end
-
if USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
@@ -127,7 +124,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -135,9 +131,7 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
-
##
## Build our reset vector (This is where coreboot is entered)
##
@@ -180,12 +174,10 @@
end
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -194,29 +186,22 @@
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-end
##
## Include the secondary Configuration files
Modified: trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/technexion/tim8690/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -83,8 +83,6 @@
#object reset.o
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
@@ -103,14 +101,12 @@
end
-end
##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -118,7 +114,6 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -137,12 +132,10 @@
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -150,12 +143,7 @@
### failover to another image.
###
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
- end
end
###
@@ -165,16 +153,12 @@
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
-
##
## Include the secondary Configuration files
##
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -81,8 +81,6 @@
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
@@ -97,8 +95,6 @@
end
end
-end
-
if USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
@@ -128,7 +124,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -136,9 +131,7 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
-
##
## Build our reset vector (This is where coreboot is entered)
##
@@ -181,12 +174,10 @@
end
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -195,29 +186,22 @@
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
##
## Include the secondary Configuration files
Modified: trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-04-11 13:59:00 UTC (rev 4092)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2912_fam10/Config.lb 2009-04-11 14:51:49 UTC (rev 4093)
@@ -81,7 +81,6 @@
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
-if USE_DCACHE_RAM
makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c
if CONFIG_USE_INIT
@@ -98,8 +97,6 @@
end
end
-end
-
if USE_FAILOVER_IMAGE
else
if CONFIG_AP_CODE_IN_CAR
@@ -129,7 +126,6 @@
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -137,9 +133,7 @@
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
-
##
## Build our reset vector (This is where coreboot is entered)
##
@@ -182,12 +176,10 @@
end
end
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -196,29 +188,22 @@
###
if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds
- end
end
else
if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds
- end
end
end
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject cache_as_ram_auto.o
else
mainboardinit ./cache_as_ram_auto.inc
end
-end
##
## Include the secondary Configuration files
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