[coreboot] Cache aliasing

Marc Jones marcj303 at gmail.com
Wed Apr 8 18:27:20 CEST 2009

On Wed, Apr 8, 2009 at 9:03 AM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:

> If all of the above is true, it should be possible to use CAR on every
> processor which has a fine-grained memory range cache control like MTRR.
> Simply make sure the cacheable area is smaller than cache size and
> smaller than the minimum aliasing distance, switch caches on and be
> happy. (External hardware may need to be told it should not trigger
> invalidation.)
> Is it really that easy?

Yes, but you want to use the CD bit trick to be safe as Ron mentioned.
Once you set a range cachable, validated the tags, and then set CD
disabled. That region of cache will continue to be used since the tags
are valid but it won't get flushed because no new tags will be
allocated. As you pointed out instructions can cause the flush but it
won't happen automatically. The Geode is actually very close to older
Intel processors but uses RCONFs intead of MTRRs.



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