[coreboot] flashrom fails to write/erase on VIA VT8237

[Corey Osgood]

Look through the vt823x code in chipset_enable.c and also the epia-cn code
in board_enable.c. Check the values of the registers modified by those
functions, and if your board's registers don't match those values, call the
appropriate function at the end of the board_enable for your board. Sorry I
can't be more specific, I only have a few minutes to check email.

-Corey

2009/4/1 vinuxes gmail <vinuxes at gmail.com>

> Hello Peter,
> Is there something that i can look into? or any pointers?
> Please help!
>
> Rgds,
> Vinod
>
>
> On Tue, Mar 31, 2009 at 10:31 AM, vinuxesgmail <vinuxes at gmail.com> wrote:
>
>> Peter,
>>   I am stuck with the same error even after applying the new patch. Here's
>> the command output:
>> {-------------------
>> stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -E          Calibrating
>> delay loop... OK.
>> No coreboot table found.
>> Found chipset "VIA VT8237", enabling flash write... OK.
>> Found board "Portwell PPAP-2020VL", enabling flash write... OK.
>> Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000.
>> Erasing flash chip... ERASE FAILED!
>> FAILED!
>> ERROR at 0x00000000: Expected=0xff, Read=0x49
>> -------------------
>> stress:/tmp # ./flashrom -m "portwell:ppap-2020vl" -w backup.bin
>> Calibrating delay loop... OK.
>> No coreboot table found.
>> Found chipset "VIA VT8237", enabling flash write... OK.
>> Found board "Portwell PPAP-2020VL", enabling flash write... OK.
>> Found chip "SST SST49LF004A/B" (512 KB) at physical address 0xfff80000.
>> Flash image seems to be a legacy BIOS. Disabling checks.
>> ERASE FAILED!
>> -------------------}
>>
>> Please guide me further.
>>
>> Regards,
>> Vinod
>>
>> Peter Stuge wrote:
>>
>>> Gah! Sorry. Here it is.
>>>
>>>
>>> //Peter
>>>
>>>
>>
>>
>
> --
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