[coreboot] Cache as RAM - is it possible to execute code in cache?

Stefan Reinauer stepan at coresystems.de
Sat Sep 6 23:02:40 CEST 2008

Jackie Pan wrote:
> I'm very curious about how you achieve this. As Intel's separate L1
> data cache and instruction cache,
> after checking the prog. manual I come to the conclusion that the
> i-cache can only be filled by instruction fetching 
> process(or am i wrong?), when I copy code into the CAR region(i.e.,
> not by caching of the XIP region using MTRR), 
> the data I supplied goes directly into the d-cache, at the same time
> the corresponding line in the i-cache(if any) gets
> invalidated immediately, or more exactly for the CAR case, there's no
> such line in the i-cache at all because there's
> not been any instruction fetching targeting at the CAR region before.
> Thus it seems impossible to synchronize the
> i-cache and d-cache without a RAM as backup.
> let me guess, are you implying storing  to another core's cache while
> using MESI for the purpose of synchronizing? 
I don't know much about MESI except it exists. But for CAR as we do it
on Intel CPUs it is essential that we keep all AP cores in Wait for SIPI
state to get them out of the way. They're only re-activated when RAM is
working, at which point we're using ram based semaphores.


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