[coreboot] r971 - in coreboot-v3: . superio superio/via superio/via/vt1211
svn at coreboot.org
svn at coreboot.org
Fri Oct 31 19:44:57 CET 2008
Author: stuge
Date: 2008-10-31 19:44:57 +0100 (Fri, 31 Oct 2008)
New Revision: 971
Added:
coreboot-v3/superio/via/
coreboot-v3/superio/via/vt1211/
coreboot-v3/superio/via/vt1211/Makefile
coreboot-v3/superio/via/vt1211/stage1.c
coreboot-v3/superio/via/vt1211/superio.c
coreboot-v3/superio/via/vt1211/vt1211.h
Modified:
coreboot-v3/Kconfig
Log:
v3: superio/via/vt1211 with serial port init but nothing else
Signed-off-by: Peter Stuge <peter at stuge.se>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Modified: coreboot-v3/Kconfig
===================================================================
--- coreboot-v3/Kconfig 2008-10-31 18:39:46 UTC (rev 970)
+++ coreboot-v3/Kconfig 2008-10-31 18:44:57 UTC (rev 971)
@@ -122,6 +122,8 @@
boolean
config SUPERIO_ITE_IT8712F
boolean
+config SUPERIO_VIA_VT1211
+ boolean
menu "Payload"
Added: coreboot-v3/superio/via/vt1211/Makefile
===================================================================
--- coreboot-v3/superio/via/vt1211/Makefile (rev 0)
+++ coreboot-v3/superio/via/vt1211/Makefile 2008-10-31 18:44:57 UTC (rev 971)
@@ -0,0 +1,29 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Peter Stuge <peter at stuge.se>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ifeq ($(CONFIG_SUPERIO_VIA_VT1211),y)
+
+STAGE0_CHIPSET_SRC += $(src)/superio/via/vt1211/stage1.c
+STAGE0_CHIPSET_SRC += $(src)/device/pnp_raw.c
+
+# Always add to variables, as there could be more than one Super I/O.
+#STAGE2_CHIPSET_SRC += $(src)/superio/via/vt1211/superio.c
+
+endif
Added: coreboot-v3/superio/via/vt1211/stage1.c
===================================================================
--- coreboot-v3/superio/via/vt1211/stage1.c (rev 0)
+++ coreboot-v3/superio/via/vt1211/stage1.c 2008-10-31 18:44:57 UTC (rev 971)
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Peter Stuge <peter at stuge.se>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <io.h>
+#include <device/pnp.h>
+#include "vt1211.h"
+
+void vt1211_enable_serial(u8 dev, u8 serial, u16 iobase)
+{
+ rawpnp_enter_ext_func_mode(dev);
+ rawpnp_set_logical_device(dev, serial);
+ rawpnp_set_enable(dev, 0);
+ rawpnp_set_iobase(dev, 2, (iobase>>2) & 0xff);
+ rawpnp_set_enable(dev, 1);
+ rawpnp_exit_ext_func_mode(dev);
+}
Added: coreboot-v3/superio/via/vt1211/superio.c
===================================================================
--- coreboot-v3/superio/via/vt1211/superio.c (rev 0)
+++ coreboot-v3/superio/via/vt1211/superio.c 2008-10-31 18:44:57 UTC (rev 971)
@@ -0,0 +1,216 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2000 AG Electronics Ltd.
+ * Copyright 2003-2004 Linux Networx
+ * Copyright 2004 Tyan
+ * By LYH change from PC87360
+ * Copyright 2007 coresystems GmbH
+ *
+ * FIXME: This is total hack and slash of v2 code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <io.h>
+#include <lib.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console.h>
+#include <string.h>
+//#include <bitops.h>
+#include <uart8250.h>
+#include <keyboard.h>
+// #include <pc80/mc146818rtc.h>
+#include <statictree.h>
+#include "w83627hf.h"
+
+static void pnp_enter_ext_func_mode(struct device * dev)
+{
+ outb(0x87, dev->path.pnp.port);
+ outb(0x87, dev->path.pnp.port);
+}
+
+static void pnp_exit_ext_func_mode(struct device * dev)
+{
+ outb(0xaa, dev->path.pnp.port);
+}
+
+static void pnp_write_index(u16 port_base, u8 reg, u8 value)
+{
+ outb(reg, port_base);
+ outb(value, port_base + 1);
+}
+
+static u8 pnp_read_index(u16 port_base, u8 reg)
+{
+ outb(reg, port_base);
+ return inb(port_base + 1);
+}
+
+static void enable_hwm_smbus(struct device * dev) {
+ /* set the pin 91,92 as I2C bus */
+ u8 reg, value;
+ reg = 0x2b;
+ value = pnp_read_config(dev, reg);
+ value &= 0x3f;
+ pnp_write_config(dev, reg, value);
+}
+
+static void init_acpi(struct device * dev)
+{
+ u8 value = 0x20;
+ int power_on = 1;
+#warning Fix CMOS handling
+ // get_option(&power_on, "power_on_after_fail");
+ pnp_enter_ext_func_mode(dev);
+ pnp_write_index(dev->path.pnp.port,7,0x0a);
+ value = pnp_read_config(dev, 0xE4);
+ value &= ~(3<<5);
+ if(power_on) {
+ value |= (1<<5);
+ }
+ pnp_write_config(dev, 0xE4, value);
+ pnp_exit_ext_func_mode(dev);
+}
+
+static void init_hwm(u16 base)
+{
+ u8 reg, value;
+ int i;
+
+ unsigned hwm_reg_values[] = {
+ /* reg, mask, data */
+ 0x40, 0xff, 0x81, /* start HWM */
+ 0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */
+ 0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus base to 0x94>>1 */
+ 0x4e, 0x80, 0x00,
+ 0x43, 0x00, 0xff,
+ 0x44, 0x00, 0x3f,
+ 0x4c, 0xbf, 0x18,
+ 0x4d, 0xff, 0x80 /* turn off beep */
+ };
+
+ for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) {
+ reg = hwm_reg_values[i];
+ value = pnp_read_index(base, reg);
+ value &= 0xff & hwm_reg_values[i+1];
+ value |= 0xff & hwm_reg_values[i+2];
+
+ printk(BIOS_SPEW, "base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
+
+ pnp_write_index(base, reg, value);
+ }
+}
+
+static void w83627hf_init(struct device * dev)
+{
+ struct superio_winbond_w83627hf_dts_config *conf;
+ struct resource *res0, *res1;
+ struct pc_keyboard keyboard;
+
+#if 1
+ printk(BIOS_ERR, "dummy init XXXX\n");
+#endif
+
+ if (!dev->enabled) {
+ return;
+ }
+
+ conf = dev->device_configuration;
+ switch(dev->path.pnp.device) {
+ case W83627HF_SP1:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+#warning init_uart8250
+ //init_uart8250(res0->base, &conf->com1);
+ break;
+ case W83627HF_SP2:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+#warning init_uart8250
+ //init_uart8250(res0->base, &conf->com2);
+ break;
+ case W83627HF_KBC:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ res1 = find_resource(dev, PNP_IDX_IO1);
+ init_pc_keyboard(res0->base, res1->base, &keyboard);
+ break;
+ case W83627HF_HWM:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+#define HWM_INDEX_PORT 5
+ init_hwm(res0->base + HWM_INDEX_PORT);
+ break;
+ case W83627HF_ACPI:
+ init_acpi(dev);
+ break;
+ }
+}
+
+void w83627hf_pnp_set_resources(struct device * dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_resources(dev);
+ pnp_exit_ext_func_mode(dev);
+}
+
+void w83627hf_pnp_enable_resources(struct device * dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_enable_resources(dev);
+ switch(dev->path.pnp.device) {
+ case W83627HF_HWM:
+ printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n");
+ enable_hwm_smbus(dev);
+ break;
+ }
+ pnp_exit_ext_func_mode(dev);
+}
+
+void w83627hf_pnp_enable(struct device * dev)
+{
+ if (!dev->enabled) {
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_exit_ext_func_mode(dev);
+ }
+}
+static void phase2_setup_scan_bus(struct device *dev);
+struct device_operations w83627hf_ops = {
+ .phase2_setup_scan_bus = phase2_setup_scan_bus,
+ .phase4_read_resources = pnp_read_resources,
+ .phase4_set_resources = w83627hf_pnp_set_resources,
+ .phase4_enable_disable = w83627hf_pnp_enable_resources,
+ .phase5_enable_resources = w83627hf_pnp_enable,
+ .phase6_init = w83627hf_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &w83627hf_ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &w83627hf_ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &w83627hf_ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &w83627hf_ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ // No 4 { 0,},
+ { &w83627hf_ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
+ { &w83627hf_ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &w83627hf_ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, },
+ { &w83627hf_ops, W83627HF_GPIO2, },
+ { &w83627hf_ops, W83627HF_GPIO3, },
+ { &w83627hf_ops, W83627HF_ACPI, },
+ { &w83627hf_ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
+};
+
+static void phase2_setup_scan_bus(struct device *dev)
+{
+ pnp_enable_devices(dev, &w83627hf_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
Added: coreboot-v3/superio/via/vt1211/vt1211.h
===================================================================
--- coreboot-v3/superio/via/vt1211/vt1211.h (rev 0)
+++ coreboot-v3/superio/via/vt1211/vt1211.h 2008-10-31 18:44:57 UTC (rev 971)
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2007 Ronald G. Minnich <rminnich at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_VIA_VT1211_VT122_H
+#define SUPERIO_VIA_VT1211_VT122_H
+
+#define VT1211_FDC 0 /* Floppy */
+#define VT1211_PP 1 /* Parallel Port */
+#define VT1211_SP1 2 /* Com1 */
+#define VT1211_SP2 3 /* Com2 */
+#define VT1211_KBC 5 /* Keyboard & Mouse */
+#define VT1211_CIR 6
+#define VT1211_GAME_MIDI_GPIO1 7
+#define VT1211_GPIO2 8
+#define VT1211_GPIO3 9
+#define VT1211_ACPI 10
+#define VT1211_HWM 11 /* Hardware Monitor */
+
+#endif /* SUPERIO_VIA_VT1211_VT122_H */
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