[coreboot] unrv2b delay (v2)

Marc Jones marc.jones at amd.com
Thu Oct 30 23:03:38 CET 2008

Arne Georg Gleditsch wrote:
> Stefan Reinauer <stepan at coresystems.de> writes:
>>> I have thought about this a while back and have wanted to make a
>>> change. Disabling CAR should fixup the stack etc but for performance
>>> reasons we should setup/leave ROM and RAM caching enabled on the BSP.
>>> If you are interested in looking at that I think it would be great.
>> What CPU/chipset is this? On quite some ROM stays cacheable all the
>> time, afaik
> I've seen this performance issue on my Tyan test rig; s2912 mainboard,
> mcp55 southbridge and 83xx Opterons.  From the code in the
> serengeti_cheetah_fam10 target I'd expect the same behavior to manifest
> there.
I think that this is in all K8 and fam10 disable_car code.
The copy to memory is probably good. Running from the rom and 
decompressing from the rom is going to thrash. It may affect some 
cpu/chipset combinations more than others.


Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com

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