[coreboot] [PATCH] CN700/VT8237R stage2 (Corey Osgood)

[JasonZhao at viatech.com.cn]

Maybe you can try more times with different values of these MACRO?

default DCACHE_RAM_BASE=0xffef0000
default DCACHE_RAM_SIZE=0x8000
default XIP_ROM_SIZE = 128 * 1024

One time, we have our DDR2 init process stopped on one of VIA's board,
and after changing the XIP_ROM_SIZE=128K to 192K (128+64 in two
var-mtrr-seg), this problem disappear.


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Message: 2
Date: Wed, 29 Oct 2008 04:02:08 -0400
From: "Corey Osgood" <corey.osgood at gmail.com>
Subject: [coreboot] [PATCH] CN700/VT8237R stage2
To: Coreboot <coreboot at coreboot.org>
Message-ID:
	<dd3c80060810290102o7b28a867y4b103e8b6ee4c621 at mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"

Attached patches for cn700, vt8237(r/s), and the mainboard, Jetway J7F2,
along with a boot log. Currently, we're stuck in a reboot loop and I
have no
idea why, seems to be related to CAR disabling (this wasn't happening
when
disable_car was a noop). Carl-Daniel, any ideas?

-Corey
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