[coreboot] K8 HT architecture

Marc Jones Marc.Jones at amd.com
Fri Oct 24 20:14:08 CEST 2008

Carl-Daniel Hailfinger wrote:
> Hi,
> I'm trying to understand how HT is modeled into PCI space so that I can
> propose the "right" way to handle it in the dts.
> Depending on whether I run lspci -t under coreboot or factory BIOS,
> different topologies will be displayed. That means looking at lspci is
> not going to tell me how the hardware really works.
> Given a standard setup with three HT links from the CPU, where do I find
> which device?
> Is PCI device 18.0 sort of a PCI bridge which has multiple PCI buses (HT
> links) behind itself?

> Or is the hardware organized in a completely different way? I'm
> especially curious about the MP scenario as depicted above. Where do the
> PCI functions of 18.[0123] reside?

This is why you don't want to mix the ht links and the pci bus. The 
physical layout and the logical layout on pci are different. the lspci 
-t view is the correct view. That is how the devices are addressed. 
Several different physical layouts will get you the same logical layout 
because of how pci buses are scanned.

cpu --- pci
cpu --- pci

would be equivalent to this (although unlikely topology)
cpu --- pci
  | \--- pci

I think it would be a mistake to over complicate the dts with the 
physical connections. The dts should be easy for people to fill in to 
make a platform work. They don't know (or need to know) what ht links 
are connecting the cpu and what ones go to pci bus.


Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com

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