[coreboot] HT devices in v3

Marc Jones Marc.Jones at amd.com
Fri Oct 24 18:51:38 CEST 2008

Carl-Daniel Hailfinger wrote:
> On 24.10.2008 00:59, Marc Jones wrote:
>> Carl-Daniel Hailfinger wrote:
>>> Hypertransport representation in the dts is non-existent. I shall attack
>>> this in the next few days. Proposals have already been sent to the list,
>>> but the enthusiasm was limited.
>> I'm sorry I don't recall your proposal.
> No problem, I'll dig it up and resend.
>> The ht isn't really ht. It is really root level pci bus. Everything is
>> a pci bus.....
> Ah, that makes the structure a lot less complicated. However, are the HT
> links in a MP setup also handled as PCI buses? I plan to model them in
> the dts as well.

No, That is all the very complicated coherent ht init. If you want to 
put that in the dts I would just take it from the link map registers. 
Since it is all setup before memory/dts you can just read it and save 
it. The coherent ht bus is separate from the pci bus.


Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com

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