[coreboot] r3680 - trunk/coreboot-v2/src/southbridge/amd/sb600

[svn at coreboot.org]

Author: uwe
Date: 2008-10-21 18:27:38 +0200 (Tue, 21 Oct 2008)
New Revision: 3680

Modified:
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.c
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.h
   trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c
Log:
I/O ports are 16bit, so change 'unsigned long port_base' to 'u16 port_base'.
Also, use more readable #defines instead of hardcoded config ports for
PM/PM2 related functions, and simplify them a bit.

Build-tested with the AMD dbm690t target.

Signed-off-by: Uwe Hermann <uwe at hermann-uwe.de>
Acked-by: Marc Jones <marc.jones at amd.com>



Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.c	2008-10-21 15:08:18 UTC (rev 3679)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.c	2008-10-21 16:27:38 UTC (rev 3680)
@@ -60,13 +60,13 @@
 	}
 }
 
-static void pmio_write_index(unsigned long port_base, u8 reg, u8 value)
+static void pmio_write_index(u16 port_base, u8 reg, u8 value)
 {
 	outb(reg, port_base);
 	outb(value, port_base + 1);
 }
 
-static u8 pmio_read_index(unsigned long port_base, u8 reg)
+static u8 pmio_read_index(u16 port_base, u8 reg)
 {
 	outb(reg, port_base);
 	return inb(port_base + 1);
@@ -74,26 +74,22 @@
 
 void pm_iowrite(u8 reg, u8 value)
 {
-	unsigned long port_base = 0xcd6;
-	pmio_write_index(port_base, reg, value);
+	pmio_write_index(PM_INDEX, reg, value);
 }
 
 u8 pm_ioread(u8 reg)
 {
-	unsigned long port_base = 0xcd6;
-	return pmio_read_index(port_base, reg);
+	return pmio_read_index(PM_INDEX, reg);
 }
 
 void pm2_iowrite(u8 reg, u8 value)
 {
-	unsigned long port_base = 0xcd0;
-	pmio_write_index(port_base, reg, value);
+	pmio_write_index(PM2_INDEX, reg, value);
 }
 
 u8 pm2_ioread(u8 reg)
 {
-	unsigned long port_base = 0xcd0;
-	return pmio_read_index(port_base, reg);
+	return pmio_read_index(PM2_INDEX, reg);
 }
 
 static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos,

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.h
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.h	2008-10-21 15:08:18 UTC (rev 3679)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600.h	2008-10-21 16:27:38 UTC (rev 3680)
@@ -23,6 +23,12 @@
 #include <device/pci_ids.h>
 #include "chip.h"
 
+/* Power management index/data registers */
+#define PM_INDEX	0xcd6
+#define PM_DATA		0xcd7
+#define PM2_INDEX	0xcd0
+#define PM2_DATA	0xcd1
+
 extern void pm_iowrite(u8 reg, u8 value);
 extern u8 pm_ioread(u8 reg);
 extern void pm2_iowrite(u8 reg, u8 value);

Modified: trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c	2008-10-21 15:08:18 UTC (rev 3679)
+++ trunk/coreboot-v2/src/southbridge/amd/sb600/sb600_early_setup.c	2008-10-21 16:27:38 UTC (rev 3680)
@@ -18,24 +18,22 @@
  */
 
 #include <arch/cpu.h>
+#include "sb600.h"
 #include "sb600_smbus.c"
 
 #define SMBUS_IO_BASE 0x1000	/* Is it a temporary SMBus I/O base address? */
 	 /*SIZE 0x40 */
 
-
-/* Copied from sb600.c
-* 0xCD6-0xCD7 is power management I/O register.*/
 static void pmio_write(u8 reg, u8 value)
 {
-	outb(reg, 0xCD6);
-	outb(value, 0xCD6 + 1);
+	outb(reg, PM_INDEX);
+	outb(value, PM_INDEX + 1);
 }
 
 static u8 pmio_read(u8 reg)
 {
-	outb(reg, 0xCD6);
-	return inb(0xCD6 + 1);
+	outb(reg, PM_INDEX);
+	return inb(PM_INDEX + 1);
 }
 
 /* Get SB ASIC Revision.*/