[coreboot] r940 - in coreboot-v3: arch/x86 include/device

svn at coreboot.org svn at coreboot.org
Tue Oct 21 01:48:30 CEST 2008


Author: rminnich
Date: 2008-10-21 01:48:30 +0200 (Tue, 21 Oct 2008)
New Revision: 940

Modified:
   coreboot-v3/arch/x86/Makefile
   coreboot-v3/include/device/pci_ops.h
Log:

Unshared pci functions, since these can not be used when broken PCI 
expansion ROMs are active.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>

Acked-by: Marc Jones <marc.jones at amd.com>



Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile	2008-10-20 15:24:00 UTC (rev 939)
+++ coreboot-v3/arch/x86/Makefile	2008-10-20 23:48:30 UTC (rev 940)
@@ -194,7 +194,7 @@
 		       compute_ip_checksum.c string.c
 
 STAGE2_ARCH_X86_SRC  = archtables.c coreboot_table.c multiboot.c udelay_io.c
-STAGE2_ARCH_X86_SRC += pci_ops_auto.c
+STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c 
 STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c
 
 ifeq ($(CONFIG_PIRQ_TABLE),y)

Modified: coreboot-v3/include/device/pci_ops.h
===================================================================
--- coreboot-v3/include/device/pci_ops.h	2008-10-20 15:24:00 UTC (rev 939)
+++ coreboot-v3/include/device/pci_ops.h	2008-10-20 23:48:30 UTC (rev 940)
@@ -24,33 +24,19 @@
 #include <shared.h>
 
 u8 pci_read_config8(struct device * dev, unsigned where);
-EXPORT_SYMBOL(pci_read_config8);
 u16 pci_read_config16(struct device * dev, unsigned where);
-EXPORT_SYMBOL(pci_read_config16);
 u32 pci_read_config32(struct device * dev, unsigned where);
-EXPORT_SYMBOL(pci_read_config32);
 void pci_write_config8(struct device * dev, unsigned where, u8 val);
-EXPORT_SYMBOL(pci_write_config8);
 void pci_write_config16(struct device * dev, unsigned where, u16 val);
-EXPORT_SYMBOL(pci_write_config16);
 void pci_write_config32(struct device * dev, unsigned where, u32 val);
-EXPORT_SYMBOL(pci_write_config32);
 
 u8 pci_conf1_read_config8(u32 bdf, int where);
-EXPORT_SYMBOL(pci_conf1_read_config8);
 u16 pci_conf1_read_config16(u32 bdf, int where);
-EXPORT_SYMBOL(pci_conf1_read_config16);
 u32 pci_conf1_read_config32(u32 bdf, int where);
-EXPORT_SYMBOL(pci_conf1_read_config32);
 void pci_conf1_write_config8(u32 bdf, int where, u8 value);
-EXPORT_SYMBOL(pci_conf1_write_config8);
 void pci_conf1_write_config16(u32 bdf, int where, u16 value);
-EXPORT_SYMBOL(pci_conf1_write_config16);
 void pci_conf1_write_config32(u32 bdf, int where, u32 value);
-EXPORT_SYMBOL(pci_conf1_write_config32);
 int pci_conf1_find_on_bus(u16 bus, u16 vid, u16 did, u32 *busdevfn);
-EXPORT_SYMBOL(pci_conf1_find_on_bus);
 int pci_conf1_find_device(u16 vid, u16 did, u32 * dev);
-EXPORT_SYMBOL(pci_conf1_find_device);
 
 #endif /* DEVICE_PCI_OPS_H */





More information about the coreboot mailing list