[coreboot] [PATCH] workaround v2 VIA ROMCC breakage

Corey Osgood corey.osgood at gmail.com
Fri Oct 17 04:10:46 CEST 2008

On Thu, Oct 16, 2008 at 9:28 PM, Eric W. Biederman <ebiederm at xmission.com>wrote:

> Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> writes:
> > On 17.10.2008 02:50, Eric W. Biederman wrote:
> >> Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> writes:
> >>
> >>
> >>> I added a special case for ROMCC in the 0x...ULL constants in
> vt8237r.h.
> >>> Please see r3664.
> >>> The remaining segfault is being investigated by Eric.
> >>>
> >>
> >> It is reproducible, and it happens as the intermediate expression is
> being
> >> translated into intermediate code so it should be to weird to track.
>  I'm
> >> going to guess 4-5 hours to sort through it.  I will aim to look at it
> this
> >> weekend.
> >>
> >
> > Wow, that was unexpected. Thanks for investing your time!
> Yes. If the bug was down in the optimizer it would take to long to track.
> Eric

The break is caused by vt8237_early_spi_init(), most likely by spireg. Patch
to disable that function in ROMCC is attached, I know that via epia-cn,
pc2500, and jetway j7f2/4 don't use SPI, but I can't remember what the other
C7/CN700 board is right this moment to check. Thanks Carl-Daniel for fixing
the rest of vt8237, and Eric for your time :)

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